[Qemu-commits] [qemu/qemu] 265859: hw/block/pflash_cfi02: Explicit switch fallthrough...

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 2658594ff64828bf4230d9224b394034dae14028
      
https://github.com/qemu/qemu/commit/2658594ff64828bf4230d9224b394034dae14028
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-16 (Tue, 16 Jul 2019)

  Changed paths:
    M hw/block/pflash_cfi02.c

  Log Message:
  -----------
  hw/block/pflash_cfi02: Explicit switch fallthrough for ERASE commands

Previous to commit ddb6f2254, the DQ2 bit was incorrectly set
during PROGRAM command (0xA0). The commit reordered the switch
cases to only set the DQ2 bit for the ERASE commands using a
fallthrough, but did not explicit the fallthrough is intentional.

Mark the switch fallthrough with a comment interpretable by C
preprocessors and static analysis tools.

Reported-by: Coverity (CID 1403012)
Reviewed-by: Peter Maydell <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 611c749c3b86fe377c94ea301feab3d9ce3bf617
      
https://github.com/qemu/qemu/commit/611c749c3b86fe377c94ea301feab3d9ce3bf617
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-16 (Tue, 16 Jul 2019)

  Changed paths:
    M hw/block/pflash_cfi01.c

  Log Message:
  -----------
  hw/block/pflash_cfi01: Start state machine as READY to accept commands

When the state machine is ready to accept command, the bit 7 of
the status register (SR) is set to 1.
The guest polls the status register and check this bit before
writting command to the internal 'Write State Machine' (WSM).

Set SR.7 bit to 1 when the device is created.

There is no migration impact by this change.

Reference: Read Array Flowchart
  "Common Flash Interface (CFI) and Command Sets"
   (Intel Application Note 646)
   Appendix B "Basic Command Set"

Reviewed-by: John Snow <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Regression-tested-by: Laszlo Ersek <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: a1a4d49f60d2b899620ee2be4ebb991c4a90a026
      
https://github.com/qemu/qemu/commit/a1a4d49f60d2b899620ee2be4ebb991c4a90a026
  Author: Peter Maydell <address@hidden>
  Date:   2019-07-16 (Tue, 16 Jul 2019)

  Changed paths:
    M hw/block/pflash_cfi01.c
    M hw/block/pflash_cfi02.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/philmd-gitlab/tags/pflash-next-20190716' into staging

pflash-next patches for v4.1.0-rc1

Trivial pflash fixes for rc1.

# gpg: Signature made Tue 16 Jul 2019 16:59:53 BST
# gpg:                using RSA key E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <address@hidden>" 
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd-gitlab/tags/pflash-next-20190716:
  hw/block/pflash_cfi01: Start state machine as READY to accept commands
  hw/block/pflash_cfi02: Explicit switch fallthrough for ERASE commands

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/1a1c0995cd4f...a1a4d49f60d2