[Qemu-commits] [qemu/qemu] b48b06: hw/arm/boot: fix direct kernel boot with initrd

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: b48b0640093764f06ae63b5df515d16fc2e26013
      
https://github.com/qemu/qemu/commit/b48b0640093764f06ae63b5df515d16fc2e26013
  Author: Andrew Jones <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  hw/arm/boot: fix direct kernel boot with initrd

Fix the condition used to check whether the initrd fits
into RAM; in some cases if an initrd was also passed on
the command line we would get an error stating that it
was too big to fit into RAM after the kernel. Despite the
error the loader continued anyway, though, so also add an
exit(1) when the initrd is actually too big.

Fixes: 852dc64d665f ("hw/arm/boot: Diagnose layouts that put initrd or
DTB off the end of RAM")
Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: dd97ef044a71123ed53e62f5203e789a6ad3772a
      
https://github.com/qemu/qemu/commit/dd97ef044a71123ed53e62f5203e789a6ad3772a
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/arm/msf2-som.c

  Log Message:
  -----------
  hw/arm/msf2-som: Exit when the cpu is not the expected one

This machine correctly defines its default_cpu_type to cortex-m3
and report an error if the user requested another cpu_type,
however it does not exit, and this can confuse users trying
to use another core:

  $ qemu-system-arm -M emcraft-sf2 -cpu cortex-m4 -kernel test-m4.elf
  qemu-system-arm: This board can only be used with CPU cortex-m3-arm-cpu
  [output related to M3 core ...]

The CPU is indeed a M3 core:

  (qemu) info qom-tree
  /machine (emcraft-sf2-machine)
    /unattached (container)
      /device[0] (msf2-soc)
        /armv7m (armv7m)
          /cpu (cortex-m3-arm-cpu)

Add the missing exit() call to return to the shell.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4414942e7ea17e7769495b43010869ec4821ee40
      
https://github.com/qemu/qemu/commit/4414942e7ea17e7769495b43010869ec4821ee40
  Author: Jan Kiszka <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Add support for Cortex-A7

Allow cortex-a7 to be used with the virt board; it supports
the v7VE features and there is no reason to deny this type.

Signed-off-by: Jan Kiszka <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f0d877dc5ee6418c510acc9d286035cc6b50ab0b
      
https://github.com/qemu/qemu/commit/f0d877dc5ee6418c510acc9d286035cc6b50ab0b
  Author: Andrey Smirnov <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/arm/fsl-imx7.c
    M include/hw/arm/fsl-imx7.h

  Log Message:
  -----------
  i.mx7d: Add no-op/unimplemented APBH DMA module

Instantiate no-op APBH DMA module. Needed to boot latest Linux kernel.

Signed-off-by: Andrey Smirnov <address@hidden>
Cc: Peter Maydell <address@hidden>
Cc: Michael S. Tsirkin <address@hidden>
Cc: address@hidden
Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>


  Commit: 6ee51e961e9fadb2c2c1b374531e7aefa38e422d
      
https://github.com/qemu/qemu/commit/6ee51e961e9fadb2c2c1b374531e7aefa38e422d
  Author: Andrey Smirnov <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/arm/fsl-imx7.c
    M include/hw/arm/fsl-imx7.h

  Log Message:
  -----------
  i.mx7d: Add no-op/unimplemented PCIE PHY IP block

Add no-op/unimplemented PCIE PHY IP block. Needed by new kernels to
use PCIE.

Signed-off-by: Andrey Smirnov <address@hidden>
Cc: Peter Maydell <address@hidden>
Cc: Michael S. Tsirkin <address@hidden>
Cc: address@hidden
Cc: address@hidden
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4eb42b81c552f9cd4d13bfbf26bbfe95c9cc7072
      
https://github.com/qemu/qemu/commit/4eb42b81c552f9cd4d13bfbf26bbfe95c9cc7072
  Author: Andrey Smirnov <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/pci-host/designware.c

  Log Message:
  -----------
  pci: designware: Update MSI mapping unconditionally

Expression to calculate update_msi_mapping in code handling writes to
DESIGNWARE_PCIE_MSI_INTR0_ENABLE is missing an ! operator and should
be:

    !!root->msi.intr[0].enable ^ !!val;

so that MSI mapping is updated when enabled transitions from either
"none" -> "any" or "any" -> "none". Since that register shouldn't be
written to very often, change the code to update MSI mapping
unconditionally instead of trying to fix the update_msi_mapping logic.

Signed-off-by: Andrey Smirnov <address@hidden>
Cc: Peter Maydell <address@hidden>
Cc: Michael S. Tsirkin <address@hidden>
Cc: address@hidden
Cc: address@hidden
Acked-by: Michael S. Tsirkin <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 97b7e29bce63e382d0eee6dd101f22b1d18cc732
      
https://github.com/qemu/qemu/commit/97b7e29bce63e382d0eee6dd101f22b1d18cc732
  Author: Andrey Smirnov <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/pci-host/designware.c

  Log Message:
  -----------
  pci: designware: Update MSI mapping when MSI address changes

MSI mapping needs to be update when MSI address changes, so add the
code to do so.

Signed-off-by: Andrey Smirnov <address@hidden>
Cc: Peter Maydell <address@hidden>
Cc: Michael S. Tsirkin <address@hidden>
Cc: address@hidden
Cc: address@hidden
Acked-by: Michael S. Tsirkin <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 01b96ec8c499891b238432290792103eb5fef04a
      
https://github.com/qemu/qemu/commit/01b96ec8c499891b238432290792103eb5fef04a
  Author: Andrey Smirnov <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/pci-host/designware.c
    M include/hw/arm/fsl-imx7.h

  Log Message:
  -----------
  i.mx7d: pci: Update PCI IRQ mapping to match HW

Datasheet for i.MX7 is incorrect and i.MX7's PCI IRQ mapping matches
that of i.MX6:

    * INTD/MSI    122
    * INTC        123
    * INTB        124
    * INTA        125

Fix all of the relevant code to reflect that fact. Needed by latest
Linux kernels.

(Reference: Linux kernel commit 538d6e9d597584e80 from an
NXP employee confirming that the datasheet is incorrect and
with a report of a test against hardware.)

Signed-off-by: Andrey Smirnov <address@hidden>
Cc: Peter Maydell <address@hidden>
Cc: Michael S. Tsirkin <address@hidden>
Cc: address@hidden
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
[PMM: added ref to kernel commit confirming the datasheet error]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b456b1132edf15ea1fd890742e31f88fc013f3dd
      
https://github.com/qemu/qemu/commit/b456b1132edf15ea1fd890742e31f88fc013f3dd
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/arm/aspeed_soc.c
    M include/hw/arm/aspeed_soc.h

  Log Message:
  -----------
  aspeed: add a per SoC mapping for the interrupt space

This will simplify the definition of new SoCs, like the AST2600 which
should use a different CPU and a different IRQ number layout.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d783d1fe581dc250dcc44e629f2f52f617920465
      
https://github.com/qemu/qemu/commit/d783d1fe581dc250dcc44e629f2f52f617920465
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/arm/aspeed.c
    M hw/arm/aspeed_soc.c
    M include/hw/arm/aspeed_soc.h

  Log Message:
  -----------
  aspeed: add a per SoC mapping for the memory space

This will simplify the definition of new SoCs, like the AST2600 which
should use a slightly different address space and have a different set
of controllers.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 979672cf51533ac629b925fea096eb6bfe25261a
      
https://github.com/qemu/qemu/commit/979672cf51533ac629b925fea096eb6bfe25261a
  Author: Joel Stanley <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/timer/Makefile.objs
    A hw/timer/aspeed_rtc.c
    M hw/timer/trace-events
    A include/hw/timer/aspeed_rtc.h

  Log Message:
  -----------
  hw: timer: Add ASPEED RTC device

The RTC is modeled to provide time and date functionality. It is
initialised at zero to match the hardware.

There is no modelling of the alarm functionality, which includes the IRQ
line. As there is no guest code to exercise this function that is
acceptable for now.

Signed-off-by: Joel Stanley <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 75fb4577fc1b7ae87cb7842aa7fe59ae4de5e95e
      
https://github.com/qemu/qemu/commit/75fb4577fc1b7ae87cb7842aa7fe59ae4de5e95e
  Author: Joel Stanley <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/arm/aspeed_soc.c
    M include/hw/arm/aspeed_soc.h

  Log Message:
  -----------
  hw/arm/aspeed: Add RTC to SoC

All systems have an RTC.

The IRQ is hooked up but the model does not use it at this stage. There
is no guest code that uses it, so this limitation is acceptable.

Signed-off-by: Joel Stanley <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ece09beec45776c09b3219c93218c4355e49c2da
      
https://github.com/qemu/qemu/commit/ece09beec45776c09b3219c93218c4355e49c2da
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/arm/aspeed.c
    M hw/arm/aspeed_soc.c
    M include/hw/arm/aspeed_soc.h

  Log Message:
  -----------
  aspeed: introduce a configurable number of CPU per machine

The current models of the Aspeed SoCs only have one CPU but future
ones will support SMP. Introduce a new num_cpus field at the SoC class
level to define the number of available CPUs per SoC and also
introduce a 'num-cpus' property to activate the CPUs configured for
the machine.

The max_cpus limit of the machine should depend on the SoC definition
but, unfortunately, these values are not available when the machine
class is initialized. This is the reason why we add a check on
num_cpus in the AspeedSoC realize handler.

SMP support will be activated when models for such SoCs are implemented.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6734099048727f302dc2b8741ba38ef8f9dcd946
      
https://github.com/qemu/qemu/commit/6734099048727f302dc2b8741ba38ef8f9dcd946
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/arm/aspeed_soc.c
    M include/hw/arm/aspeed_soc.h

  Log Message:
  -----------
  aspeed: add support for multiple NICs

The Aspeed SoCs have two MACs. Extend the Aspeed model to support a
second NIC.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8137355e850f634715209087ab664b271996db42
      
https://github.com/qemu/qemu/commit/8137355e850f634715209087ab664b271996db42
  Author: Joel Stanley <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/timer/aspeed_timer.c

  Log Message:
  -----------
  aspeed/timer: Fix behaviour running Linux

The Linux kernel driver was updated in commit 4451d3f59f2a
("clocksource/drivers/fttmr010: Fix set_next_event handler) to fix an
issue observed on hardware:

 > RELOAD register is loaded into COUNT register when the aspeed timer
 > is enabled, which means the next event may be delayed because timer
 > interrupt won't be generated until <0xFFFFFFFF - current_count +
 > cycles>.

When running under Qemu, the system appeared "laggy". The guest is now
scheduling timer events too regularly, starving the host of CPU time.

This patch modifies the timer model to attempt to schedule the timer
expiry as the guest requests, but if we have missed the deadline we
re interrupt and try again, which allows the guest to catch up.

Provides expected behaviour with old and new guest code.

Fixes: c04bd47db6b9 ("hw/timer: Add ASPEED timer device model")
Signed-off-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
[clg: - merged a fix from Andrew Jeffery <address@hidden>
        "Fire interrupt on failure to meet deadline"
        https://lists.ozlabs.org/pipermail/openbmc/2019-January/014641.html
      - adapted commit log
      - checkpatch fixes ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 58044b5cf5f30eb298709696ddbafdf547c1291c
      
https://github.com/qemu/qemu/commit/58044b5cf5f30eb298709696ddbafdf547c1291c
  Author: Andrew Jeffery <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/timer/aspeed_timer.c

  Log Message:
  -----------
  aspeed/timer: Status register contains reload for stopped timer

>From the datasheet:

  This register stores the current status of counter #N. When timer
  enable bit TMC30[N * b] is disabled, the reload register will be
  loaded into this counter. When timer bit TMC30[N * b] is set, the
  counter will start to decrement. CPU can update this register value
  when enable bit is set.

Signed-off-by: Andrew Jeffery <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 696942b8bc6562a2b23c6ed8ae32ecdeb9bf4b60
      
https://github.com/qemu/qemu/commit/696942b8bc6562a2b23c6ed8ae32ecdeb9bf4b60
  Author: Andrew Jeffery <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/timer/aspeed_timer.c

  Log Message:
  -----------
  aspeed/timer: Fix match calculations

If the match value exceeds reload then we don't want to include it in
calculations for the next event.

Signed-off-by: Andrew Jeffery <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 055762479be1575377ecf2d8fceb9d8df2703d0f
      
https://github.com/qemu/qemu/commit/055762479be1575377ecf2d8fceb9d8df2703d0f
  Author: Christian Svensson <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/timer/aspeed_timer.c

  Log Message:
  -----------
  aspeed/timer: Ensure positive muldiv delta

If the host decrements the counter register that results in a negative
delta. This is then passed to muldiv64 which only handles unsigned
numbers resulting in bogus results.

This fix ensures the delta being operated on is positive.

Test case: kexec a kernel using aspeed_timer and it will freeze on the
second bootup when the kernel initializes the timer. With this patch
that no longer happens and the timer appears to run OK.

Signed-off-by: Christian Svensson <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 026498a8f19fec9cbdc7dd3857d53b794be02e2e
      
https://github.com/qemu/qemu/commit/026498a8f19fec9cbdc7dd3857d53b794be02e2e
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: remove the "ram" link

It has never been used as far as I can tell from the git history.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ad1a9782186d0ed1c02eb008f268d34599a54a42
      
https://github.com/qemu/qemu/commit/ad1a9782186d0ed1c02eb008f268d34599a54a42
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: add a RAM memory region container

The RAM memory region is defined after the SoC is realized when the
SDMC controller has checked that the defined RAM size for the machine
is correct. This is problematic for controller models requiring a link
on the RAM region, for DMA support in the SMC controller for instance.

Introduce a container memory region for the RAM that we can link into
the controllers early, before the SoC is realized. It will be
populated with the RAM region after the checks have be done.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6da4433fc5fa8aff1096cc651c8d313c70ee6f4d
      
https://github.com/qemu/qemu/commit/6da4433fc5fa8aff1096cc651c8d313c70ee6f4d
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/arm/aspeed_soc.c
    M hw/ssi/aspeed_smc.c
    M include/hw/ssi/aspeed_smc.h

  Log Message:
  -----------
  aspeed/smc: add a 'sdram_base' property

The DRAM address of a DMA transaction depends on the DRAM base address
of the SoC. Inform the SMC controller model with this value.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: aae7a18d475608b46a923899a6f3989f087e92fe
      
https://github.com/qemu/qemu/commit/aae7a18d475608b46a923899a6f3989f087e92fe
  Author: Adriana Kobylak <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/arm/aspeed.c

  Log Message:
  -----------
  aspeed: Add support for the swift-bmc board

The Swift board is an OpenPOWER system hosting POWER processors.
Add support for their BMC including the I2C devices as found on HW.

Signed-off-by: Adriana Kobylak <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 118c82e7ff4bd3aeaeca31caa64fb95351531ac4
      
https://github.com/qemu/qemu/commit/118c82e7ff4bd3aeaeca31caa64fb95351531ac4
  Author: Eddie James <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/arm/aspeed_soc.c
    M hw/misc/Makefile.objs
    A hw/misc/aspeed_xdma.c
    M hw/misc/trace-events
    M include/hw/arm/aspeed_soc.h
    A include/hw/misc/aspeed_xdma.h

  Log Message:
  -----------
  hw/misc/aspeed_xdma: New device

The XDMA engine embedded in the Aspeed SOCs performs PCI DMA operations
between the SOC (acting as a BMC) and a host processor in a server.

The XDMA engine exists on the AST2400, AST2500, and AST2600 SOCs, so
enable it for all of those. Add trace events on the important register
writes in the XDMA engine.

Signed-off-by: Eddie James <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
[clg: - changed title ]
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ebd205c0807a146bf272208f3d41728d5e985ceb
      
https://github.com/qemu/qemu/commit/ebd205c0807a146bf272208f3d41728d5e985ceb
  Author: Andrew Jeffery <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/intc/aspeed_vic.c

  Log Message:
  -----------
  aspeed: vic: Add support for legacy register interface

The legacy interface only supported up to 32 IRQs, which became
restrictive around the AST2400 generation. QEMU support for the SoCs
started with the AST2400 along with an effort to reimplement and
upstream drivers for Linux, so up until this point the consumers of the
QEMU ASPEED support only required the 64 IRQ register interface.

In an effort to support older BMC firmware, add support for the 32 IRQ
interface.

Signed-off-by: Andrew Jeffery <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3059c2f5a813ea2af0761705abc18848cd4e3c85
      
https://github.com/qemu/qemu/commit/3059c2f5a813ea2af0761705abc18848cd4e3c85
  Author: Joel Stanley <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/arm/aspeed_soc.c
    M hw/watchdog/wdt_aspeed.c
    M include/hw/watchdog/wdt_aspeed.h

  Log Message:
  -----------
  aspeed: Link SCU to the watchdog

The ast2500 uses the watchdog to reset the SDRAM controller. This
operation is usually performed by u-boot's memory training procedure,
and it is enabled by setting a bit in the SCU and then causing the
watchdog to expire. Therefore, we need the watchdog to be able to
access the SCU's register space.

This causes the watchdog to not perform a system reset when the bit is
set. In the future it could perform a reset of the SDMC model.

Signed-off-by: Joel Stanley <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 64580903c2b3aee08d74d64e6248a313b246cb69
      
https://github.com/qemu/qemu/commit/64580903c2b3aee08d74d64e6248a313b246cb69
  Author: Hongbo Zhang <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M MAINTAINERS
    M default-configs/aarch64-softmmu.mak
    M hw/arm/Kconfig
    M hw/arm/Makefile.objs
    A hw/arm/sbsa-ref.c

  Log Message:
  -----------
  hw/arm: Add arm SBSA reference machine, skeleton part

For AArch64, the existing "virt" machine is primarily meant to
run on KVM and execute virtualization workloads, but we need an
environment as faithful as possible to physical hardware, for supporting
firmware and OS development for physical Aarch64 machines.

This patch introduces new machine type 'sbsa-ref' with main features:
 - Based on 'virt' machine type.
 - A new memory map.
 - CPU type cortex-a57.
 - EL2 and EL3 are enabled.
 - GIC version 3.
 - System bus AHCI controller.
 - System bus EHCI controller.
 - CDROM and hard disc on AHCI bus.
 - E1000E ethernet card on PCIE bus.
 - VGA display adaptor on PCIE bus.
 - No virtio devices.
 - No fw_cfg device.
 - No ACPI table supplied.
 - Only minimal device tree nodes.

Arm Trusted Firmware and UEFI porting to this are done accordingly,
and the firmware should supply ACPI tables to the guest OS.  The
minimal device tree nodes supplied by QEMU for this platform are only
to pass the dynamic info reflecting command line input to firmware,
not for loading the guest OS.

To make the review easier, this task is split into two patches, the
fundamental skeleton part and the peripheral devices part; this patch is
the first part.

Signed-off-by: Hongbo Zhang <address@hidden>
Message-id: address@hidden
[PMM: commit message tweaks; moved some bits between patch 1 and 2
 to ensure patch 1 builds cleanly; removed unneeded lines from
 Kconfig stanza; only provide board for qemu-system-aarch64, not
 qemu-system-arm; added MAINTAINERS entry]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e9fdf453240ebb57894f5382bb2da6a97cdb2998
      
https://github.com/qemu/qemu/commit/e9fdf453240ebb57894f5382bb2da6a97cdb2998
  Author: Hongbo Zhang <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M hw/arm/sbsa-ref.c

  Log Message:
  -----------
  hw/arm: Add arm SBSA reference machine, devices part

Following the previous patch, this patch adds peripheral devices to the
newly introduced SBSA-ref machine.

Signed-off-by: Hongbo Zhang <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 87f4f183484dba7a460c59e99dac0dbb9f42ed87
      
https://github.com/qemu/qemu/commit/87f4f183484dba7a460c59e99dac0dbb9f42ed87
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M target/arm/Makefile.objs

  Log Message:
  -----------
  target/arm: Makefile cleanup (Aarch64)

Group Aarch64 rules together, TCG related ones at the bottom.
This will help when restricting TCG-only objects.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 07774d584267488c8c2f104ae5b552791961908a
      
https://github.com/qemu/qemu/commit/07774d584267488c8c2f104ae5b552791961908a
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M target/arm/Makefile.objs

  Log Message:
  -----------
  target/arm: Makefile cleanup (ARM)

Group ARM objects together, TCG related ones at the bottom.
This will help when restricting TCG-only objects.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7efefd9bbb70868445f6147b27068966b3734582
      
https://github.com/qemu/qemu/commit/7efefd9bbb70868445f6147b27068966b3734582
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M target/arm/Makefile.objs

  Log Message:
  -----------
  target/arm: Makefile cleanup (KVM)

Group KVM rules together.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b601e0cd78c2c57548a468c6fdb566d514c05b89
      
https://github.com/qemu/qemu/commit/b601e0cd78c2c57548a468c6fdb566d514c05b89
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M target/arm/Makefile.objs

  Log Message:
  -----------
  target/arm: Makefile cleanup (softmmu)

Group SOFTMMU objects together.
Since PSCI is TCG specific, keep it separate.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ed3baad15b0b0edc480373f9c1d805d6b8e7e78c
      
https://github.com/qemu/qemu/commit/ed3baad15b0b0edc480373f9c1d805d6b8e7e78c
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add copyright boilerplate

Reviewed-by: Robert Bradford <address@hidden>
Reviewed-by: Samuel Ortiz <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2c8ec397f8438eea5e52be4898dfcf12a1f88267
      
https://github.com/qemu/qemu/commit/2c8ec397f8438eea5e52be4898dfcf12a1f88267
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm/helper: Remove unused include

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9a223097e44d5320f5e0546710263f22d11f12fc
      
https://github.com/qemu/qemu/commit/9a223097e44d5320f5e0546710263f22d11f12fc
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M target/arm/helper.c
    M target/arm/op_helper.c
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Fix multiline comment syntax

Since commit 8c06fbdf36b checkpatch.pl enforce a new multiline
comment syntax. Since we'll move this code around, fix its style
first.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9798ac7162c8a720c5d28f4d1fc9e03c7ab4f015
      
https://github.com/qemu/qemu/commit/9798ac7162c8a720c5d28f4d1fc9e03c7ab4f015
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M target/arm/translate.c
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm: Fix coding style issues

Since we'll move this code around, fix its style first.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6cdca173ef81a9dbcee9e142f1a5a34ad9c44b75
      
https://github.com/qemu/qemu/commit/6cdca173ef81a9dbcee9e142f1a5a34ad9c44b75
  Author: Samuel Ortiz <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M target/arm/helper.c
    M target/arm/op_helper.c

  Log Message:
  -----------
  target/arm: Move the DC ZVA helper into op_helper

Those helpers are a software implementation of the ARM v8 memory zeroing
op code. They should be moved to the op helper file, which is going to
eventually be built only when TCG is enabled.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Robert Bradford <address@hidden>
Signed-off-by: Samuel Ortiz <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
[PMD: Rebased]
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 864806156a0e48255331636b3550bcbf2bd2d3d6
      
https://github.com/qemu/qemu/commit/864806156a0e48255331636b3550bcbf2bd2d3d6
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Move CPU state dumping routines to cpu.c

Suggested-by: Samuel Ortiz <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ebae861fc6c385a7bcac72dde4716be06e6776f1
      
https://github.com/qemu/qemu/commit/ebae861fc6c385a7bcac72dde4716be06e6776f1
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Declare get_phys_addr() function publicly

In the next commit we will split the TLB related routines of
this file, and this function will also be called in the new
file. Declare it in the "internals.h" header.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e21b551cb652663f2f2405a64d63ef6b4a1042b7
      
https://github.com/qemu/qemu/commit/e21b551cb652663f2f2405a64d63ef6b4a1042b7
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M target/arm/Makefile.objs
    M target/arm/cpu.c
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/op_helper.c
    A target/arm/tlb_helper.c

  Log Message:
  -----------
  target/arm: Move TLB related routines to tlb_helper.c

These routines are TCG specific.
The arm_deliver_fault() function is only used within the new
helper. Make it static.

Suggested-by: Alex Bennée <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 20e62dd8c831c9065ed4a8e64813c93ad61c50d7
      
https://github.com/qemu/qemu/commit/20e62dd8c831c9065ed4a8e64813c93ad61c50d7
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm/vfp_helper: Move code around

To ease the review of the next commit,
move the vfp_exceptbits_to_host() function directly after
vfp_exceptbits_from_host().  Amusingly the diff shows we
are moving vfp_get_fpscr().

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e9d652824b05845f143ef4797d707fae47d4b3ed
      
https://github.com/qemu/qemu/commit/e9d652824b05845f143ef4797d707fae47d4b3ed
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm/vfp_helper: Extract vfp_set_fpscr_to_host()

The vfp_set_fpscr() helper contains code specific to the host
floating point implementation (here the SoftFloat library).
Extract this code to vfp_set_fpscr_to_host().

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0c6ad94809b37a1f0f1f75d3cd0e4a24fb77e65c
      
https://github.com/qemu/qemu/commit/0c6ad94809b37a1f0f1f75d3cd0e4a24fb77e65c
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm/vfp_helper: Extract vfp_set_fpscr_from_host()

The vfp_set_fpscr() helper contains code specific to the host
floating point implementation (here the SoftFloat library).
Extract this code to vfp_set_fpscr_from_host().

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4a15527c9feecfd2fa2807d5e698abbc19feb35f
      
https://github.com/qemu/qemu/commit/4a15527c9feecfd2fa2807d5e698abbc19feb35f
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  target/arm/vfp_helper: Restrict the SoftFloat use to TCG

This code is specific to the SoftFloat floating-point
implementation, which is only used by TCG.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 21fbea8c8af72817d8e21570fa4edbfae417341b
      
https://github.com/qemu/qemu/commit/21fbea8c8af72817d8e21570fa4edbfae417341b
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Restrict PSCI to TCG

Under KVM, the kernel gets the HVC call and handle the PSCI requests.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b59f479beee77523a6918127052307d865db1f77
      
https://github.com/qemu/qemu/commit/b59f479beee77523a6918127052307d865db1f77
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Declare arm_log_exception() function publicly

In few commits we will split the M-profile functions from this
file, and this function will also be called in the new file.
Declare it in the "internals.h" header.
Since it is in the middle of a block of M profile functions,
move it previous to this block to ease the later refactor.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 787a7e76c2e93a48c47b324fea592c9910a70483
      
https://github.com/qemu/qemu/commit/787a7e76c2e93a48c47b324fea592c9910a70483
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-07-01 (Mon, 01 Jul 2019)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Declare some M-profile functions publicly

In the next commit we will split the M-profile functions from this
file. Some function will be called out of helper.c. Declare them in
the "internals.h" header.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c4e42a9c2b714de5cddabffe46c7789fcff49c30
      
https://github.com/qemu/qemu/commit/c4e42a9c2b714de5cddabffe46c7789fcff49c30
  Author: Peter Maydell <address@hidden>
  Date:   2019-07-02 (Tue, 02 Jul 2019)

  Changed paths:
    M MAINTAINERS
    M default-configs/aarch64-softmmu.mak
    M hw/arm/Kconfig
    M hw/arm/Makefile.objs
    M hw/arm/aspeed.c
    M hw/arm/aspeed_soc.c
    M hw/arm/boot.c
    M hw/arm/fsl-imx7.c
    M hw/arm/msf2-som.c
    A hw/arm/sbsa-ref.c
    M hw/arm/virt.c
    M hw/intc/aspeed_vic.c
    M hw/misc/Makefile.objs
    A hw/misc/aspeed_xdma.c
    M hw/misc/trace-events
    M hw/pci-host/designware.c
    M hw/ssi/aspeed_smc.c
    M hw/timer/Makefile.objs
    A hw/timer/aspeed_rtc.c
    M hw/timer/aspeed_timer.c
    M hw/timer/trace-events
    M hw/watchdog/wdt_aspeed.c
    M include/hw/arm/aspeed_soc.h
    M include/hw/arm/fsl-imx7.h
    A include/hw/misc/aspeed_xdma.h
    M include/hw/ssi/aspeed_smc.h
    A include/hw/timer/aspeed_rtc.h
    M include/hw/watchdog/wdt_aspeed.h
    M target/arm/Makefile.objs
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/op_helper.c
    A target/arm/tlb_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h
    M target/arm/vfp_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190701' 
into staging

target-arm queue:
 * hw/arm/boot: fix direct kernel boot with initrd
 * hw/arm/msf2-som: Exit when the cpu is not the expected one
 * i.mx7: fix bugs in PCI controller needed to boot recent kernels
 * aspeed: add RTC device
 * aspeed: fix some timer device bugs
 * aspeed: add swift-bmc board
 * aspeed: vic: Add support for legacy register interface
 * aspeed: add aspeed-xdma device
 * Add new sbsa-ref board for aarch64
 * target/arm: code refactoring in preparation for support of
   compilation with TCG disabled

# gpg: Signature made Mon 01 Jul 2019 17:38:10 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190701: (46 commits)
  target/arm: Declare some M-profile functions publicly
  target/arm: Declare arm_log_exception() function publicly
  target/arm: Restrict PSCI to TCG
  target/arm/vfp_helper: Restrict the SoftFloat use to TCG
  target/arm/vfp_helper: Extract vfp_set_fpscr_from_host()
  target/arm/vfp_helper: Extract vfp_set_fpscr_to_host()
  target/arm/vfp_helper: Move code around
  target/arm: Move TLB related routines to tlb_helper.c
  target/arm: Declare get_phys_addr() function publicly
  target/arm: Move CPU state dumping routines to cpu.c
  target/arm: Move the DC ZVA helper into op_helper
  target/arm: Fix coding style issues
  target/arm: Fix multiline comment syntax
  target/arm/helper: Remove unused include
  target/arm: Add copyright boilerplate
  target/arm: Makefile cleanup (softmmu)
  target/arm: Makefile cleanup (KVM)
  target/arm: Makefile cleanup (ARM)
  target/arm: Makefile cleanup (Aarch64)
  hw/arm: Add arm SBSA reference machine, devices part
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/d247c8e7f4fc...c4e42a9c2b71