[Qemu-commits] [qemu/qemu] 30efbf: SiFive RISC-V GPIO Device

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 30efbf330a45fc5b83457037927151adafc397ed
      
https://github.com/qemu/qemu/commit/30efbf330a45fc5b83457037927151adafc397ed
  Author: Fabien Chouteau <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M Makefile.objs
    M hw/riscv/Makefile.objs
    M hw/riscv/sifive_e.c
    A hw/riscv/sifive_gpio.c
    A hw/riscv/trace-events
    M include/hw/riscv/sifive_e.h
    A include/hw/riscv/sifive_gpio.h

  Log Message:
  -----------
  SiFive RISC-V GPIO Device

QEMU model of the GPIO device on the SiFive E300 series SOCs.

The pins are not used by a board definition yet, however this
implementation can already be used to trigger GPIO interrupts from the
software by configuring a pin as both output and input.

Signed-off-by: Fabien Chouteau <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: b86f4167630802128d94f3c89043d97d2f4c2546
      
https://github.com/qemu/qemu/commit/b86f4167630802128d94f3c89043d97d2f4c2546
  Author: Jonathan Behrens <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/op_helper.c

  Log Message:
  -----------
  target/riscv: Do not allow sfence.vma from user mode

The 'sfence.vma' instruction is privileged, and should only ever be allowed
when executing in supervisor mode or higher.

Signed-off-by: Jonathan Behrens <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 6e2716d8ca4edf3597307accef7af36e8ad966eb
      
https://github.com/qemu/qemu/commit/6e2716d8ca4edf3597307accef7af36e8ad966eb
  Author: Fabien Chouteau <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/insn_trans/trans_privileged.inc.c
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  RISC-V: fix single stepping over ret and other branching instructions

This patch introduces wrappers around the tcg_gen_exit_tb() and
tcg_gen_lookup_and_goto_ptr() functions that handle single stepping,
i.e. call gen_exception_debug() when single stepping is enabled.

Theses functions are then used instead of the originals, bringing single
stepping handling in places where it was previously ignored such as jalr
and system branch instructions (ecall, mret, sret, etc.).

Signed-off-by: Fabien Chouteau <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: e761799796ac2211b9706753c459e117e7be58fa
      
https://github.com/qemu/qemu/commit/e761799796ac2211b9706753c459e117e7be58fa
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/insn32.decode
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Name the argument sets for all of insn32 formats

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 81770255581bd210c57b86a6e808628ab8d0c543
      
https://github.com/qemu/qemu/commit/81770255581bd210c57b86a6e808628ab8d0c543
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/Makefile.objs
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Use --static-decode for decodetree

The generated functions are only used within translate.c
and do not need to be global, or declared.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: e1d455dd91c935c714412dafeb24db947429a929
      
https://github.com/qemu/qemu/commit/e1d455dd91c935c714412dafeb24db947429a929
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/insn16.decode
    M target/riscv/insn_trans/trans_rvc.inc.c

  Log Message:
  -----------
  target/riscv: Merge argument sets for insn32 and insn16

In some cases this allows us to directly use the insn32
translator function.  In some cases we still need a shim.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 6cafec92f1c862a9754ef6a28be68ba7178a284d
      
https://github.com/qemu/qemu/commit/6cafec92f1c862a9754ef6a28be68ba7178a284d
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/insn16.decode
    M target/riscv/insn_trans/trans_rvc.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Merge argument decode for RVC shifti

Special handling for IMM==0 is the only difference between
RVC shifti and RVI shifti.  This can be handled with !function.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: c2cfb97c01a3636867c1a4a24f8a99fd8c6bed28
      
https://github.com/qemu/qemu/commit/c2cfb97c01a3636867c1a4a24f8a99fd8c6bed28
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/insn16.decode
    M target/riscv/insn_trans/trans_rvc.inc.c
    M target/riscv/insn_trans/trans_rvi.inc.c

  Log Message:
  -----------
  target/riscv: Use pattern groups in insn16.decode

This eliminates about half of the complicated decode
bits within insn_trans/trans_rvc.inc.c.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 0e68e240a9bd3b44a91cd6012f0e2bf2a43b9fe2
      
https://github.com/qemu/qemu/commit/0e68e240a9bd3b44a91cd6012f0e2bf2a43b9fe2
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/Makefile.objs
    A target/riscv/insn16-32.decode
    A target/riscv/insn16-64.decode
    M target/riscv/insn16.decode
    R target/riscv/insn_trans/trans_rvc.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Split RVC32 and RVC64 insns into separate files

This eliminates all functions in insn_trans/trans_rvc.inc.c,
so the entire file can be removed.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 598aa1160c3d17ab9271daf1f69d093ebada3f25
      
https://github.com/qemu/qemu/commit/598aa1160c3d17ab9271daf1f69d093ebada3f25
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/riscv/translate.c

  Log Message:
  -----------
  target/riscv: Split gen_arith_imm into functional and temp

The tcg_gen_fooi_tl functions have some immediate constant
folding built in, which match up with some of the riscv asm
builtin macros, like mv and not.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 7f9188e210aff6522a960d9669a583a3a752ddc0
      
https://github.com/qemu/qemu/commit/7f9188e210aff6522a960d9669a583a3a752ddc0
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Remove spaces from register names

These extra spaces make the "-d op" dump look weird.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: e5ef9566af59e1cf99fb81fa6bbdf7d2cf494cb2
      
https://github.com/qemu/qemu/commit/e5ef9566af59e1cf99fb81fa6bbdf7d2cf494cb2
  Author: Jonathan Behrens <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  target/riscv: Remove unused include of riscv_htif.h for virt board riscv

Signed-off-by: Jonathan Behrens <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 77c62400e5eb8dced12c09e4a32ff3b0580f62b8
      
https://github.com/qemu/qemu/commit/77c62400e5eb8dced12c09e4a32ff3b0580f62b8
  Author: Alistair Francis <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M linux-user/riscv/target_elf.h

  Log Message:
  -----------
  linux-user/riscv: Add the CPU type as a comment

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: ceb2ffd56e3ec7caa8afc94b78257bac99cd738b
      
https://github.com/qemu/qemu/commit/ceb2ffd56e3ec7caa8afc94b78257bac99cd738b
  Author: Alistair Francis <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  riscv: virt: Allow specifying a CPU via commandline

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: c4e95030ba3532d13aa4e6f0738326f6f2d0c2bf
      
https://github.com/qemu/qemu/commit/c4e95030ba3532d13aa4e6f0738326f6f2d0c2bf
  Author: Alistair Francis <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Create settable CPU properties

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 8903bf6e6d73d03b988b4a8197132de2ad681ff5
      
https://github.com/qemu/qemu/commit/8903bf6e6d73d03b988b4a8197132de2ad681ff5
  Author: Alistair Francis <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M include/hw/riscv/virt.h
    M qemu-deprecated.texi
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  target/riscv: Add a base 32 and 64 bit CPU

At the same time deprecate the ISA string CPUs.

It is dobtful anyone specifies the CPUs, but we are keeping them for the
Spike machine (which is about to be depreated) so we may as well just
mark them as deprecated.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: d64db71cf7d9075beac140086d7b4afbe3fb7557
      
https://github.com/qemu/qemu/commit/d64db71cf7d9075beac140086d7b4afbe3fb7557
  Author: Alistair Francis <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M qemu-deprecated.texi

  Log Message:
  -----------
  target/riscv: Deprecate the generic no MMU CPUs

These can now be specified via the command line so we no longer need
these.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: cd69e3a60b7c97127f56ceba566c5a3d594f42b5
      
https://github.com/qemu/qemu/commit/cd69e3a60b7c97127f56ceba566c5a3d594f42b5
  Author: Alistair Francis <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M hw/riscv/spike.c
    M qemu-deprecated.texi

  Log Message:
  -----------
  riscv: spike: Add a generic spike machine

Add a generic spike machine (not tied to a version) and deprecate the
spike mahines that are tied to a specific version. As we can now specify
the CPU via the command line we no londer need specific versions of the
spike machines.

Signed-off-by: Alistair Francis <address@hidden>
Acked-by: Igor Mammedov <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 356d74192a035c71a78a22d24812a6df6099ae40
      
https://github.com/qemu/qemu/commit/356d74192a035c71a78a22d24812a6df6099ae40
  Author: Alistair Francis <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/cpu_bits.h

  Log Message:
  -----------
  target/riscv: Mark privilege level 2 as reserved

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 0a01f2eecba47a48c9d06e3fb9acbd2a8a842cfc
      
https://github.com/qemu/qemu/commit/0a01f2eecba47a48c9d06e3fb9acbd2a8a842cfc
  Author: Alistair Francis <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Trigger interrupt on MIP update asynchronously

The requirement of holding the iothread_mutex is burdersome when
swapping the background and foreground registers in the Hypervisor
extension. To avoid the requrirement let's set the interrupt
asynchronously.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 16fdb8ff64374ed51b246437e13043039a8eb9f9
      
https://github.com/qemu/qemu/commit/16fdb8ff64374ed51b246437e13043039a8eb9f9
  Author: Alistair Francis <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: Improve the scause logic

No functional change, just making the code easier to read.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 49aaa3e534f5422a56313bb93c1880e70fc1da7e
      
https://github.com/qemu/qemu/commit/49aaa3e534f5422a56313bb93c1880e70fc1da7e
  Author: Alistair Francis <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/cpu_bits.h

  Log Message:
  -----------
  target/riscv: Add the MPV and MTL mstatus bits

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 1f0419cb0475eebdbefea67483e85287f3af07a7
      
https://github.com/qemu/qemu/commit/1f0419cb0475eebdbefea67483e85287f3af07a7
  Author: Alistair Francis <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Allow setting mstatus virtulisation bits

Signed-off-by: Alistair Francis <address@hidden>
Revieweb-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 71f09a5bb48d0c51b87e70158407ec2db4a9c6e2
      
https://github.com/qemu/qemu/commit/71f09a5bb48d0c51b87e70158407ec2db4a9c6e2
  Author: Alistair Francis <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/cpu_bits.h

  Log Message:
  -----------
  target/riscv: Add Hypervisor CSR macros

Add the 1.10.1 Hypervisor CSRs and remove the 1.9.1 spec versions.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: d28b15a4d3b1e000ec7bf9090fe870cbc5f1eb2c
      
https://github.com/qemu/qemu/commit/d28b15a4d3b1e000ec7bf9090fe870cbc5f1eb2c
  Author: Alistair Francis <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/cpu_bits.h

  Log Message:
  -----------
  target/riscv: Add the HSTATUS register masks

Signed-off-by: Alistair Francis <address@hidden>
Reviwed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: e06431108b0b1ef6ca76398d2b0b792ea24ae6bc
      
https://github.com/qemu/qemu/commit/e06431108b0b1ef6ca76398d2b0b792ea24ae6bc
  Author: Alistair Francis <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/cpu_bits.h

  Log Message:
  -----------
  target/riscv: Add the HGATP register masks

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 4cc16b3b9282e04fab8e84d136540757e82af019
      
https://github.com/qemu/qemu/commit/4cc16b3b9282e04fab8e84d136540757e82af019
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/insn16-64.decode
    M target/riscv/insn16.decode

  Log Message:
  -----------
  target/riscv: Add checks for several RVC reserved operands

C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved
operands that were not diagnosed.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 087b051a51a0c2a5bc1e8d435a484a8896b4176b
      
https://github.com/qemu/qemu/commit/087b051a51a0c2a5bc1e8d435a484a8896b4176b
  Author: Jonathan Behrens <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: More accurate handling of `sip` CSR

According to the spec, "All bits besides SSIP, USIP, and UEIP in the sip
register are read-only." Further, if an interrupt is not delegated to mode x,
then "the corresponding bits in xip [...] should appear to be hardwired to
zero. This patch implements both of those requirements.

Signed-off-by: Jonathan Behrens <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 1e0d985fa9136a563168a3da66f3d17820404ee2
      
https://github.com/qemu/qemu/commit/1e0d985fa9136a563168a3da66f3d17820404ee2
  Author: Jonathan Behrens <address@hidden>
  Date:   2019-05-24 (Fri, 24 May 2019)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Only flush TLB if SATP.ASID changes

There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857

Signed-off-by: Jonathan Behrens <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 4bade28288b12a6268d2e1fc2e4fa1f77ccb1d89
      
https://github.com/qemu/qemu/commit/4bade28288b12a6268d2e1fc2e4fa1f77ccb1d89
  Author: Peter Maydell <address@hidden>
  Date:   2019-05-28 (Tue, 28 May 2019)

  Changed paths:
    M Makefile.objs
    M hw/riscv/Makefile.objs
    M hw/riscv/sifive_e.c
    A hw/riscv/sifive_gpio.c
    M hw/riscv/spike.c
    A hw/riscv/trace-events
    M hw/riscv/virt.c
    M include/hw/riscv/sifive_e.h
    A include/hw/riscv/sifive_gpio.h
    M include/hw/riscv/virt.h
    M linux-user/riscv/target_elf.h
    M qemu-deprecated.texi
    M target/riscv/Makefile.objs
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    A target/riscv/insn16-32.decode
    A target/riscv/insn16-64.decode
    M target/riscv/insn16.decode
    M target/riscv/insn32.decode
    M target/riscv/insn_trans/trans_privileged.inc.c
    R target/riscv/insn_trans/trans_rvc.inc.c
    M target/riscv/insn_trans/trans_rvi.inc.c
    M target/riscv/op_helper.c
    M target/riscv/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.1-sf0' 
into staging

RISC-V Patches for the 4.1 Soft Freeze, Part 1

This tag contains a handful of patches that I'd like to target for 4.1:

* An emulation for SiFive's GPIO device.
* A fix to disallow sfence.vma from userspace.
* Additional decodetree cleanups that should have no functional impact.
* C extension emulation fidelity fixes that were noticed as part of that
  cleanup process.
* A new "spike" target, along with the deprecation of a handful of old
  targets and CPUs.
* Some initial infastructure related to the hypervisor extension.
* An emulation fidelity fix that prevents prevents arbitrary bits in the
  SIP CSR from being set.
* A small performance improvement that avoids excessive TLB flushing
  when the ASID does not change.

This time I've used a new testing workflow: I've tested on both 32-bit
and 64-bit builds of OpenEmbedded, via the default OpenSBI-based boot
flow.

# gpg: Signature made Sat 25 May 2019 01:05:57 BST
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Palmer Dabbelt <address@hidden>" [unknown]
# gpg:                 aka "Palmer Dabbelt <address@hidden>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-4.1-sf0: (29 commits)
  target/riscv: Only flush TLB if SATP.ASID changes
  target/riscv: More accurate handling of `sip` CSR
  target/riscv: Add checks for several RVC reserved operands
  target/riscv: Add the HGATP register masks
  target/riscv: Add the HSTATUS register masks
  target/riscv: Add Hypervisor CSR macros
  target/riscv: Allow setting mstatus virtulisation bits
  target/riscv: Add the MPV and MTL mstatus bits
  target/riscv: Improve the scause logic
  target/riscv: Trigger interrupt on MIP update asynchronously
  target/riscv: Mark privilege level 2 as reserved
  riscv: spike: Add a generic spike machine
  target/riscv: Deprecate the generic no MMU CPUs
  target/riscv: Add a base 32 and 64 bit CPU
  target/riscv: Create settable CPU properties
  riscv: virt: Allow specifying a CPU via commandline
  linux-user/riscv: Add the CPU type as a comment
  target/riscv: Remove unused include of riscv_htif.h for virt board riscv
  target/riscv: Remove spaces from register names
  target/riscv: Split gen_arith_imm into functional and temp
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/2b01c1b38217...4bade28288b1