[Qemu-commits] [qemu/qemu] e1227b: tcg: Implement tcg_gen_gvec

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[Qemu-commits] [qemu/qemu] e1227b: tcg: Implement tcg_gen_gvec_3i()

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] e1227b: tcg: Implement tcg_gen_gvec_3i()
Date:	Tue, 14 May 2019 05:35:16 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: e1227bb6e59173117f094a6a13b998587b45c928
      
https://github.com/qemu/qemu/commit/e1227bb6e59173117f094a6a13b998587b45c928
  Author: David Hildenbrand <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/tcg-op-gvec.c
    M tcg/tcg-op-gvec.h

  Log Message:
  -----------
  tcg: Implement tcg_gen_gvec_3i()

Let's add tcg_gen_gvec_3i(), similar to tcg_gen_gvec_2i(), however
without introducing "gen_helper_gvec_3i *fnoi", as it isn't needed
for now.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: ac383dde33405106469d04a78de1d76f1a730cb1
      
https://github.com/qemu/qemu/commit/ac383dde33405106469d04a78de1d76f1a730cb1
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/optimize.c

  Log Message:
  -----------
  tcg: Do not recreate INDEX_op_neg_vec unless supported

Use tcg_can_emit_vec_op instead of just TCG_TARGET_HAS_neg_vec,
so that we check the type and vece for the actual operation.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: ce27c5d1a38e93da38653af71fb468c5eded4c7b
      
https://github.com/qemu/qemu/commit/ce27c5d1a38e93da38653af71fb468c5eded4c7b
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/tcg-op-vec.c

  Log Message:
  -----------
  tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded

PowerPC Altivec does not support add and subtract of 64-bit elements.
Prepare for that configuration by not assuming the operation is
universally supported.

Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 53229a7703eeb2bbe101a19a33ef22aaf960c65b
      
https://github.com/qemu/qemu/commit/53229a7703eeb2bbe101a19a33ef22aaf960c65b
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M target/arm/translate-sve.c
    M target/arm/translate.c
    M target/ppc/translate/vmx-impl.inc.c
    M tcg/tcg-op-gvec.c
    M tcg/tcg-op-gvec.h
    M tcg/tcg-op-vec.c
    M tcg/tcg.h

  Log Message:
  -----------
  tcg: Specify optional vector requirements with a list

Replace the single opcode in .opc with a null-terminated
array in .opt_opc.  We still require that all opcodes be
used with the same .vece.

Validate the contents of this list with CONFIG_DEBUG_TCG.
All tcg_gen_*_vec functions will check any list active
during .fniv expansion.  Swap the active list in and out
as we expand other opcodes, or take control away from the
front-end function.

Convert all existing vector aware front ends.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: d63e3b6e694ad6c887be135dddb9cd4893f1a844
      
https://github.com/qemu/qemu/commit/d63e3b6e694ad6c887be135dddb9cd4893f1a844
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Assert fixed_reg is read-only

The only fixed_reg is cpu_env, and it should not be modified
during any TB.  Therefore code that tries to special-case moves
into a fixed_reg is dead.  Remove it.

Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: c16f52b2c5d91c36e121795bd3b386cea0b7573c
      
https://github.com/qemu/qemu/commit/c16f52b2c5d91c36e121795bd3b386cea0b7573c
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/arm/tcg-target.inc.c

  Log Message:
  -----------
  tcg/arm: Use tcg_out_mov_reg in tcg_out_mov

We have a function that takes an additional condition parameter
over the standard backend interface.  It already takes care of
eliding no-op moves.

Signed-off-by: Richard Henderson <address@hidden>


  Commit: 78113e83e0007e869c9f0cb4c0497a77538988e3
      
https://github.com/qemu/qemu/commit/78113e83e0007e869c9f0cb4c0497a77538988e3
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/aarch64/tcg-target.inc.c
    M tcg/arm/tcg-target.inc.c
    M tcg/i386/tcg-target.inc.c
    M tcg/mips/tcg-target.inc.c
    M tcg/ppc/tcg-target.inc.c
    M tcg/riscv/tcg-target.inc.c
    M tcg/s390/tcg-target.inc.c
    M tcg/sparc/tcg-target.inc.c
    M tcg/tcg.c
    M tcg/tci/tcg-target.inc.c

  Log Message:
  -----------
  tcg: Return bool success from tcg_out_mov

This patch merely changes the interface, aborting on all failures,
of which there are currently none.

Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: David Hildenbrand <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 240c08d0998f402c325fce489de0d14831048128
      
https://github.com/qemu/qemu/commit/240c08d0998f402c325fce489de0d14831048128
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Support cross-class moves without instruction support

PowerPC Altivec does not support direct moves between vector registers
and general registers.  So when tcg_out_mov fails, we can use the
backing memory for the temporary to perform the move.

Acked-by: David Hildenbrand <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: e7632cfa8b76cdbbc1c76e8737338ef5844e7d60
      
https://github.com/qemu/qemu/commit/e7632cfa8b76cdbbc1c76e8737338ef5844e7d60
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/aarch64/tcg-target.inc.c
    M tcg/i386/tcg-target.inc.c
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Promote tcg_out_{dup,dupi}_vec to backend interface

The i386 backend already has these functions, and the aarch64 backend
could easily split out one.  Nothing is done with these functions yet,
but this will aid register allocation of INDEX_op_dup_vec in a later patch.

Adjust the aarch64 tcg_out_dupi_vec signature to match the new interface.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: bab1671f0fa928fd678a22f934739f06fd5fd035
      
https://github.com/qemu/qemu/commit/bab1671f0fa928fd678a22f934739f06fd5fd035
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/aarch64/tcg-target.inc.c
    M tcg/i386/tcg-target.inc.c
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Manually expand INDEX_op_dup_vec

This case is similar to INDEX_op_mov_* in that we need to do
different things depending on the current location of the source.

Signed-off-by: Richard Henderson <address@hidden>
---
v3: Added some commentary to the tcg_reg_alloc_* functions.


  Commit: d6ecb4a978b718dbe108a9fa9ecccc8b7f7cb579
      
https://github.com/qemu/qemu/commit/d6ecb4a978b718dbe108a9fa9ecccc8b7f7cb579
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/aarch64/tcg-target.inc.c
    M tcg/i386/tcg-target.inc.c
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Add tcg_out_dupm_vec to the backend interface

Currently stubbed out in all backends that support vectors.

Signed-off-by: Richard Henderson <address@hidden>


  Commit: 1e262b49b5331441f697461e4305fe06719758a7
      
https://github.com/qemu/qemu/commit/1e262b49b5331441f697461e4305fe06719758a7
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/i386/tcg-target.inc.c

  Log Message:
  -----------
  tcg/i386: Implement tcg_out_dupm_vec

At the same time, improve tcg_out_dupi_vec wrt broadcast
from the constant pool.

Signed-off-by: Richard Henderson <address@hidden>


  Commit: f23e5e15edfd49d5dd72cab2ed2d85ac354b2eeb
      
https://github.com/qemu/qemu/commit/f23e5e15edfd49d5dd72cab2ed2d85ac354b2eeb
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/aarch64/tcg-target.inc.c

  Log Message:
  -----------
  tcg/aarch64: Implement tcg_out_dupm_vec

The LD1R instruction does all the work.  Note that the only
useful addressing mode is a base register with no offset.

Signed-off-by: Richard Henderson <address@hidden>


  Commit: 37ee55a081b7863ffab2151068dd1b2f11376914
      
https://github.com/qemu/qemu/commit/37ee55a081b7863ffab2151068dd1b2f11376914
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/aarch64/tcg-target.inc.c
    M tcg/i386/tcg-target.inc.c
    M tcg/tcg-op-gvec.c
    M tcg/tcg-op-vec.c
    M tcg/tcg-op.h
    M tcg/tcg-opc.h
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Add INDEX_op_dupm_vec

Allow the backend to expand dup from memory directly, instead of
forcing the value into a temp first.  This is especially important
if integer/vector register moves do not exist.

Note that officially tcg_out_dupm_vec is allowed to fail.
If it did, we could fix this up relatively easily:

  VECE == 32/64:
    Load the value into a vector register, then dup.
    Both of these must work.

  VECE == 8/16:
    If the value happens to be at an offset such that an aligned
    load would place the desired value in the least significant
    end of the register, go ahead and load w/garbage in high bits.

    Load the value w/INDEX_op_ld{8,16}_i32.
    Attempt a move directly to vector reg, which may fail.
    Store the value into the backing store for OTS.
    Load the value into the vector reg w/TCG_TYPE_I32, which must work.
    Duplicate from the vector reg into itself, which must work.

All of which is well and good, except that all supported
hosts can support dupm for all vece, so all of the failure
paths would be dead code and untestable.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 5ee5c14cacda27e904cd6b0d9e7ffe1acff42838
      
https://github.com/qemu/qemu/commit/5ee5c14cacda27e904cd6b0d9e7ffe1acff42838
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M accel/tcg/tcg-runtime-gvec.c
    M accel/tcg/tcg-runtime.h
    M tcg/tcg-op-gvec.c
    M tcg/tcg-op-gvec.h
    M tcg/tcg-op-vec.c
    M tcg/tcg-op.h

  Log Message:
  -----------
  tcg: Add gvec expanders for variable shift

The gvec expanders perform a modulo on the shift count.  If the target
requires alternate behaviour, then it cannot use the generic gvec
expanders anyway, and will have to have its own custom code.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: a2ce146a06807fe1d1a81e878b8f249ff1e14038
      
https://github.com/qemu/qemu/commit/a2ce146a06807fe1d1a81e878b8f249ff1e14038
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/i386/tcg-target.h
    M tcg/i386/tcg-target.inc.c

  Log Message:
  -----------
  tcg/i386: Support vector variable shift opcodes

Signed-off-by: Richard Henderson <address@hidden>


  Commit: 79525dfd08262d8de10d271f17e5a4096ef96d16
      
https://github.com/qemu/qemu/commit/79525dfd08262d8de10d271f17e5a4096ef96d16
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/aarch64/tcg-target.h
    M tcg/aarch64/tcg-target.inc.c
    M tcg/aarch64/tcg-target.opc.h

  Log Message:
  -----------
  tcg/aarch64: Support vector variable shift opcodes

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: b4578cd91cda4cef1c413304353ca6dc5b957b60
      
https://github.com/qemu/qemu/commit/b4578cd91cda4cef1c413304353ca6dc5b957b60
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/tcg-op-gvec.c
    M tcg/tcg-op-gvec.h
    M tcg/tcg-op-vec.c
    M tcg/tcg-op.h

  Log Message:
  -----------
  tcg: Add gvec expanders for vector shift by scalar

Allow expansion either via shift by scalar or by replicating
the scalar for shift by vector.

Signed-off-by: Richard Henderson <address@hidden>
---
v3: Use a private structure for do_gvec_shifts.


  Commit: 0a8d7a3bf5a149a82450eef555fd61728703dd84
      
https://github.com/qemu/qemu/commit/0a8d7a3bf5a149a82450eef555fd61728703dd84
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/i386/tcg-target.h
    M tcg/i386/tcg-target.inc.c

  Log Message:
  -----------
  tcg/i386: Support vector scalar shift opcodes

Signed-off-by: Richard Henderson <address@hidden>


  Commit: ff1f11f7f8710a768f9313f24bd7f509d3db27e5
      
https://github.com/qemu/qemu/commit/ff1f11f7f8710a768f9313f24bd7f509d3db27e5
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M target/arm/translate.c
    M tcg/tcg-op.c
    M tcg/tcg-op.h

  Log Message:
  -----------
  tcg: Add support for integer absolute value

Remove a function of the same name from target/arm/.
Use a branchless implementation of abs gleaned from gcc.

Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: David Hildenbrand <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: bcefc90208f8a1d6f619d61c2647281d92277015
      
https://github.com/qemu/qemu/commit/bcefc90208f8a1d6f619d61c2647281d92277015
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M accel/tcg/tcg-runtime-gvec.c
    M accel/tcg/tcg-runtime.h
    M tcg/README
    M tcg/aarch64/tcg-target.h
    M tcg/i386/tcg-target.h
    M tcg/tcg-op-gvec.c
    M tcg/tcg-op-gvec.h
    M tcg/tcg-op-vec.c
    M tcg/tcg-opc.h
    M tcg/tcg.c
    M tcg/tcg.h

  Log Message:
  -----------
  tcg: Add support for vector absolute value

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 18f9b65f1a4225dd314cb9b0a8dea968c5bc2ef3
      
https://github.com/qemu/qemu/commit/18f9b65f1a4225dd314cb9b0a8dea968c5bc2ef3
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/i386/tcg-target.h
    M tcg/i386/tcg-target.inc.c

  Log Message:
  -----------
  tcg/i386: Support vector absolute value

Signed-off-by: Richard Henderson <address@hidden>


  Commit: a456394ae540f852cd0d10fd693fe9f33598dc01
      
https://github.com/qemu/qemu/commit/a456394ae540f852cd0d10fd693fe9f33598dc01
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/aarch64/tcg-target.h
    M tcg/aarch64/tcg-target.inc.c

  Log Message:
  -----------
  tcg/aarch64: Support vector absolute value

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 4e027a710673f5d4dc6cff88728bcfd32e4c47b0
      
https://github.com/qemu/qemu/commit/4e027a710673f5d4dc6cff88728bcfd32e4c47b0
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M target/arm/helper.h
    M target/arm/neon_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 73f671f1a2cbf98264c376359449e4e2a21b8853
      
https://github.com/qemu/qemu/commit/73f671f1a2cbf98264c376359449e4e2a21b8853
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M target/cris/translate.c

  Log Message:
  -----------
  target/cris: Use tcg_gen_abs_tl

Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: d577dbaac7553767232faabb6a3e291aebd348ae
      
https://github.com/qemu/qemu/commit/d577dbaac7553767232faabb6a3e291aebd348ae
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M target/ppc/translate/spe-impl.inc.c

  Log Message:
  -----------
  target/ppc: Use tcg_gen_abs_i32

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: fe21b785ff41709a03e614183c01a6fb1de3d1b7
      
https://github.com/qemu/qemu/commit/fe21b785ff41709a03e614183c01a6fb1de3d1b7
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: Use tcg_gen_abs_tl

Signed-off-by: Richard Henderson <address@hidden>


  Commit: fa45f61114a2ec538e05adc843f6128160cdc546
      
https://github.com/qemu/qemu/commit/fa45f61114a2ec538e05adc843f6128160cdc546
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M target/s390x/translate.c

  Log Message:
  -----------
  target/s390x: Use tcg_gen_abs_i64

Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 2f8036d2361d7ee31845d89353971a43e24a2917
      
https://github.com/qemu/qemu/commit/2f8036d2361d7ee31845d89353971a43e24a2917
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M target/tricore/translate.c

  Log Message:
  -----------
  target/tricore: Use tcg_gen_abs_tl

Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: e1c4786541d90fefc2e84d2db57e0a89c6893403
      
https://github.com/qemu/qemu/commit/e1c4786541d90fefc2e84d2db57e0a89c6893403
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: Use tcg_gen_abs_i32

Acked-by: Max Filippov <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: a7b6d286cfb5205b9f5330aefc5727269b3d810f
      
https://github.com/qemu/qemu/commit/a7b6d286cfb5205b9f5330aefc5727269b3d810f
  Author: Richard Henderson <address@hidden>
  Date:   2019-05-13 (Mon, 13 May 2019)

  Changed paths:
    M tcg/aarch64/tcg-target.inc.c

  Log Message:
  -----------
  tcg/aarch64: Do not advertise minmax for MO_64

The min/max instructions are not available for 64-bit elements.

Fixes: 93f332a50371
Signed-off-by: Richard Henderson <address@hidden>


  Commit: e329ad2ab72c43b56df88b34954c2c7d839bb373
      
https://github.com/qemu/qemu/commit/e329ad2ab72c43b56df88b34954c2c7d839bb373
  Author: Peter Maydell <address@hidden>
  Date:   2019-05-14 (Tue, 14 May 2019)

  Changed paths:
    M accel/tcg/tcg-runtime-gvec.c
    M accel/tcg/tcg-runtime.h
    M target/arm/helper.h
    M target/arm/neon_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate-sve.c
    M target/arm/translate.c
    M target/cris/translate.c
    M target/ppc/translate.c
    M target/ppc/translate/spe-impl.inc.c
    M target/ppc/translate/vmx-impl.inc.c
    M target/s390x/translate.c
    M target/tricore/translate.c
    M target/xtensa/translate.c
    M tcg/README
    M tcg/aarch64/tcg-target.h
    M tcg/aarch64/tcg-target.inc.c
    M tcg/aarch64/tcg-target.opc.h
    M tcg/arm/tcg-target.inc.c
    M tcg/i386/tcg-target.h
    M tcg/i386/tcg-target.inc.c
    M tcg/mips/tcg-target.inc.c
    M tcg/optimize.c
    M tcg/ppc/tcg-target.inc.c
    M tcg/riscv/tcg-target.inc.c
    M tcg/s390/tcg-target.inc.c
    M tcg/sparc/tcg-target.inc.c
    M tcg/tcg-op-gvec.c
    M tcg/tcg-op-gvec.h
    M tcg/tcg-op-vec.c
    M tcg/tcg-op.c
    M tcg/tcg-op.h
    M tcg/tcg-opc.h
    M tcg/tcg.c
    M tcg/tcg.h
    M tcg/tci/tcg-target.inc.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190513' into staging

Improve code generation for vector duplication.
Add vector expansions for shifts by non-constant scalar.
Add vector expansions for shifts by vector.
Add integer and vector expansions for absolute value.
Several patches in preparation for Altivec.
Bug fix for tcg/aarch64 vs min/max.

# gpg: Signature made Tue 14 May 2019 00:58:02 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Richard Henderson <address@hidden>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20190513: (31 commits)
  tcg/aarch64: Do not advertise minmax for MO_64
  target/xtensa: Use tcg_gen_abs_i32
  target/tricore: Use tcg_gen_abs_tl
  target/s390x: Use tcg_gen_abs_i64
  target/ppc: Use tcg_gen_abs_tl
  target/ppc: Use tcg_gen_abs_i32
  target/cris: Use tcg_gen_abs_tl
  target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs
  tcg/aarch64: Support vector absolute value
  tcg/i386: Support vector absolute value
  tcg: Add support for vector absolute value
  tcg: Add support for integer absolute value
  tcg/i386: Support vector scalar shift opcodes
  tcg: Add gvec expanders for vector shift by scalar
  tcg/aarch64: Support vector variable shift opcodes
  tcg/i386: Support vector variable shift opcodes
  tcg: Add gvec expanders for variable shift
  tcg: Add INDEX_op_dupm_vec
  tcg/aarch64: Implement tcg_out_dupm_vec
  tcg/i386: Implement tcg_out_dupm_vec
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/e24f44dbeab8...e329ad2ab72c
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