[Qemu-commits] [qemu/qemu] a036f5: target/arm: Fix non-parallel expansion of CASP

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: a036f5302c13634f3d375615b2949fd1fa1657b6
      
https://github.com/qemu/qemu/commit/a036f5302c13634f3d375615b2949fd1fa1657b6
  Author: Richard Henderson <address@hidden>
  Date:   2019-03-25 (Mon, 25 Mar 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Fix non-parallel expansion of CASP

The second word has been loaded from the unincremented
address since the first commit.

Fixes: 44ac14b06fa
Reported-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4261b2f915cbc1538c528d982a521c76dd46e66c
      
https://github.com/qemu/qemu/commit/4261b2f915cbc1538c528d982a521c76dd46e66c
  Author: Paolo Bonzini <address@hidden>
  Date:   2019-03-25 (Mon, 25 Mar 2019)

  Changed paths:
    M hw/gpio/nrf51_gpio.c

  Log Message:
  -----------
  nrf51_gpio: reflect pull-up/pull-down to IRQs

Some drivers do I2C bitbanging by keeping the output to 0 and flipping
the GPIO direction between input and output (see for example in Linux
gpio_set_open_drain_value_commit, in drivers/gpio/gpiolib.c).
When the GPIO is set to input, the pull-up resistor brings the output
to 1, while when the GPIO is set to output, the output driver brings
the output to 0.

Implement this for the nRF51 GPIO device model.  First, if both input and
output are floating, and there is a pull-up or pull-down resistor
configured, do not just set s->in, but also make any devices listening
on the output qemu_irq receive that value.  Second, if the pin is
driven both internally (output pin) and externally you don't get a
short circuit if both sides drive the pin to the same value.

Signed-off-by: Paolo Bonzini <address@hidden>
Acked-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
[PMM: wrapped long line]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: da77e0fad445eda22277c786b7d45cd96b7c3b2a
      
https://github.com/qemu/qemu/commit/da77e0fad445eda22277c786b7d45cd96b7c3b2a
  Author: Andrew Jones <address@hidden>
  Date:   2019-03-25 (Mon, 25 Mar 2019)

  Changed paths:
    M default-configs/arm-softmmu.mak

  Log Message:
  -----------
  target/arm: add PCI_TESTDEV back to default config

In the kconfig shuffle arm lost pci-testdev which is used by
kvm-unit-tests. Let's add it back.

Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: cbbb3041fe2f57a475cef5d6b0ef836118aad106
      
https://github.com/qemu/qemu/commit/cbbb3041fe2f57a475cef5d6b0ef836118aad106
  Author: Andrew Jones <address@hidden>
  Date:   2019-03-25 (Mon, 25 Mar 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: fix crash on pmu register access

Fix a QEMU NULL derefence that occurs when the guest attempts to
enable PMU counters with a non-v8 cpu model or a v8 cpu model
which has not configured a PMU.

Fixes: 4e7beb0cc0f3 ("target/arm: Add a timer to predict PMU counter overflow")
Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a46118fc16537a593119e5b316052a98514046bb
      
https://github.com/qemu/qemu/commit/a46118fc16537a593119e5b316052a98514046bb
  Author: Andrew Jones <address@hidden>
  Date:   2019-03-25 (Mon, 25 Mar 2019)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: cortex-a7 and cortex-a15 have pmus

cortex-a7 and cortex-a15 have pmus (PMUv2) and they advertise
them in ID_DFR0. Let's allow them to function. This also enables
the pmu cpu property to work with these cpu types, i.e. we can
now do '-cpu cortex-a15,pmu=off' to remove the pmu.

Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f2b2f53f6429b5abd7cd86bd65747f5f13e195eb
      
https://github.com/qemu/qemu/commit/f2b2f53f6429b5abd7cd86bd65747f5f13e195eb
  Author: Andrew Jones <address@hidden>
  Date:   2019-03-25 (Mon, 25 Mar 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: make pmccntr_op_start/finish static

These functions are not used outside helper.c

Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 50ccc488b0d4c3b8e2790c18bcd7329fc609a1c6
      
https://github.com/qemu/qemu/commit/50ccc488b0d4c3b8e2790c18bcd7329fc609a1c6
  Author: Peter Maydell <address@hidden>
  Date:   2019-03-25 (Mon, 25 Mar 2019)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/gpio/nrf51_gpio.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/translate-a64.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190325' 
into staging

target-arm queue:
 * Fix non-parallel expansion of CASP
 * nrf51_gpio: reflect pull-up/pull-down to IRQs
 * Fix crash if guest tries to enable non-existent PMU counters
 * Add PMUv2 to the Cortex-A15 and Cortex-A7
 * Make pmccntr_op_start/finish static

# gpg: Signature made Mon 25 Mar 2019 14:19:47 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190325:
  target/arm: make pmccntr_op_start/finish static
  target/arm: cortex-a7 and cortex-a15 have pmus
  target/arm: fix crash on pmu register access
  target/arm: add PCI_TESTDEV back to default config
  nrf51_gpio: reflect pull-up/pull-down to IRQs
  target/arm: Fix non-parallel expansion of CASP

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/adb3321bfdea...50ccc488b0d4