[Qemu-commits] [qemu/qemu] 1a987a: RISC-V: Add 32-bit gdb xml files.

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 1a987a1d5faaff6c3616a857c111aa3fd9d40ffa
      
https://github.com/qemu/qemu/commit/1a987a1d5faaff6c3616a857c111aa3fd9d40ffa
  Author: Jim Wilson <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M configure
    A gdb-xml/riscv-32bit-cpu.xml
    A gdb-xml/riscv-32bit-csr.xml
    A gdb-xml/riscv-32bit-fpu.xml

  Log Message:
  -----------
  RISC-V: Add 32-bit gdb xml files.

Signed-off-by: Jim Wilson <address@hidden>
Signed-off-by: Chih-Min Chao <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: c670970dc069ebaf941a786f0608fca701dcf7d0
      
https://github.com/qemu/qemu/commit/c670970dc069ebaf941a786f0608fca701dcf7d0
  Author: Jim Wilson <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M configure
    M gdb-xml/riscv-32bit-fpu.xml
    A gdb-xml/riscv-64bit-cpu.xml
    A gdb-xml/riscv-64bit-csr.xml
    A gdb-xml/riscv-64bit-fpu.xml

  Log Message:
  -----------
  RISC-V: Add 64-bit gdb xml files.

Signed-off-by: Jim Wilson <address@hidden>
Signed-off-by: Chih-Min Chao <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 8e73df6aa3f2f0e5c26c03a94a88406616291815
      
https://github.com/qemu/qemu/commit/8e73df6aa3f2f0e5c26c03a94a88406616291815
  Author: Jim Wilson <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M target/riscv/cpu_bits.h

  Log Message:
  -----------
  RISC-V: Fixes to CSR_* register macros.

This adds some missing CSR_* register macros, and documents some as being
priv v1.9.1 specific.

Signed-off-by: Jim Wilson <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 753e3fe207db08ce0ef0405e8452c3397c9b9308
      
https://github.com/qemu/qemu/commit/753e3fe207db08ce0ef0405e8452c3397c9b9308
  Author: Jim Wilson <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/csr.c

  Log Message:
  -----------
  RISC-V: Add debug support for accessing CSRs.

Add a debugger field to CPURISCVState.  Add riscv_csrrw_debug function
to set it.  Disable mode checks when debugger field true.

Signed-off-by: Jim Wilson <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 5371f5cd7170f29310575977f89e6e35d4d65168
      
https://github.com/qemu/qemu/commit/5371f5cd7170f29310575977f89e6e35d4d65168
  Author: Jim Wilson <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/gdbstub.c

  Log Message:
  -----------
  RISC-V: Add hooks to use the gdb xml files.

The gdb CSR xml file has registers in documentation order, not numerical
order, so we need a table to map the register numbers.  This also adds
fairly standard gdb hooks to access xml specified registers.

notice:
    The fpu xml from gdb 8.3 has unused register #, 65 and make first
    csr register # become 69. We register extra register on gdb to correct
    csr offset calculation

Signed-off-by: Jim Wilson <address@hidden>
Signed-off-by: Chih-Min Chao <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: aad5ac2311f3ad2c0be12d0eaaf4ef4398438fc2
      
https://github.com/qemu/qemu/commit/aad5ac2311f3ad2c0be12d0eaaf4ef4398438fc2
  Author: Alistair Francis <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  riscv: pmp: Log pmp access errors as guest errors

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 244df421333970e66bc48e48e7fb45fcb1017ea0
      
https://github.com/qemu/qemu/commit/244df421333970e66bc48e48e7fb45fcb1017ea0
  Author: Michael Clark <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M hw/riscv/sifive_plic.c

  Log Message:
  -----------
  RISC-V: Replace __builtin_popcount with ctpop8 in PLIC

The mode variable only uses the lower 4-bits (M,H,S,U) so
replace the GCC specific __builtin_popcount with ctpop8.

Cc: Palmer Dabbelt <address@hidden>
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: e3e7039cc24ecf47d81c091e8bb04552d6564ad8
      
https://github.com/qemu/qemu/commit/e3e7039cc24ecf47d81c091e8bb04552d6564ad8
  Author: Michael Clark <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M hw/riscv/sifive_plic.c
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c

  Log Message:
  -----------
  RISC-V: Allow interrupt controllers to claim interrupts

We can't allow the supervisor to control SEIP as this would allow the
supervisor to clear a pending external interrupt which will result in
lost a interrupt in the case a PLIC is attached. The SEIP bit must be
hardware controlled when a PLIC is attached.

This logic was previously hard-coded so SEIP was always masked even
if no PLIC was attached. This patch adds riscv_cpu_claim_interrupts
so that the PLIC can register control of SEIP. In the case of models
without a PLIC (spike), the SEIP bit remains software controlled.

This interface allows for hardware control of supervisor timer and
software interrupts by other interrupt controller models.

Cc: Palmer Dabbelt <address@hidden>
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: c124c152428559216c5d083e11a35e51f773c007
      
https://github.com/qemu/qemu/commit/c124c152428559216c5d083e11a35e51f773c007
  Author: Michael Clark <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M disas/riscv.c

  Log Message:
  -----------
  RISC-V: Remove unnecessary disassembler constraints

Remove machine generated constraints that are not
referenced by the pseudo-instruction constraints.

Cc: Palmer Dabbelt <address@hidden>
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: c02b78c7b4cecfe0a027abff8ecc3ec02e8b4a53
      
https://github.com/qemu/qemu/commit/c02b78c7b4cecfe0a027abff8ecc3ec02e8b4a53
  Author: Michael Clark <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M include/elf.h

  Log Message:
  -----------
  elf: Add RISC-V PSABI ELF header defines

Refer to the RISC-V PSABI specification for details:

- https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

Cc: Michael Tokarev <address@hidden>
Cc: Richard Henderson <address@hidden>
Cc: Alistair Francis <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 5836c3eccedb6dfab16b8f606f2de24b8938b69c
      
https://github.com/qemu/qemu/commit/5836c3eccedb6dfab16b8f606f2de24b8938b69c
  Author: Kito Cheng <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M linux-user/riscv/cpu_loop.c
    M target/riscv/cpu.h
    M target/riscv/cpu_user.h

  Log Message:
  -----------
  RISC-V: linux-user support for RVE ABI

This change checks elf_flags for EF_RISCV_RVE and if
present uses the RVE linux syscall ABI which uses t0
for the syscall number instead of a7.

Warn and exit if a non-RVE ABI binary is run on a
cpu with the RVE extension as it is incompatible.

Cc: Palmer Dabbelt <address@hidden>
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Alistair Francis <address@hidden>
Co-authored-by: Kito Cheng <address@hidden>
Co-authored-by: Michael Clark <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: d26f5a423438e579d3ff0ca35e44edb966a36233
      
https://github.com/qemu/qemu/commit/d26f5a423438e579d3ff0ca35e44edb966a36233
  Author: Michael Clark <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  RISC-V: Change local interrupts from edge to level

This effectively changes riscv_cpu_update_mip
from edge to level. i.e. cpu_interrupt or
cpu_reset_interrupt are called regardless of
the current interrupt level.

Fixes WFI doesn't return when a IPI is issued:

- https://github.com/riscv/riscv-qemu/issues/132

To test:

1) Apply RISC-V Linux CPU hotplug patch:

- http://lists.infradead.org/pipermail/linux-riscv/2018-May/000603.html

2) Enable CONFIG_CPU_HOTPLUG in linux .config

3) Try to offline and online cpus:

  echo 1 > /sys/devices/system/cpu/cpu2/online
  echo 0 > /sys/devices/system/cpu/cpu2/online
  echo 1 > /sys/devices/system/cpu/cpu2/online

Reported-by: Atish Patra <address@hidden>
Cc: Atish Patra <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: acbbb94e5730c9808830938e869d243014e2923a
      
https://github.com/qemu/qemu/commit/acbbb94e5730c9808830938e869d243014e2923a
  Author: Michael Clark <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c

  Log Message:
  -----------
  RISC-V: Add support for vectored interrupts

If vectored interrupts are enabled (bits[1:0]
of mtvec/stvec == 1) then use the following
logic for trap entry address calculation:

 pc = mtvec + cause * 4

In addition to adding support for vectored interrupts
this patch simplifies the interrupt delivery logic
by making sync/async cause decoding and encoding
steps distinct.

The cause code and the sign bit indicating sync/async
is split at the beginning of the function and fixed
cause is renamed to cause. The MSB setting for async
traps is delayed until setting mcause/scause to allow
redundant variables to be eliminated. Some variables
are renamed for conciseness and moved so that decls
are at the start of the block.

Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 929f0a7fc40d7123ddda4c9dbd78a1806999b4f7
      
https://github.com/qemu/qemu/commit/929f0a7fc40d7123ddda4c9dbd78a1806999b4f7
  Author: Michael Clark <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M Makefile.objs
    M target/riscv/cpu_helper.c
    A target/riscv/trace-events

  Log Message:
  -----------
  RISC-V: Convert trap debugging to trace events

Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: d9360e96885dbd69ce4aa925d1701c7a10cf54ae
      
https://github.com/qemu/qemu/commit/d9360e96885dbd69ce4aa925d1701c7a10cf54ae
  Author: Michael Clark <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  RISC-V: Update load reservation comment in do_interrupt

Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 8b1d0714bfdd1ac2704519200120e326cba31066
      
https://github.com/qemu/qemu/commit/8b1d0714bfdd1ac2704519200120e326cba31066
  Author: Alistair Francis <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  riscv: sifive_u: Allow up to 4 CPUs to be created

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 6b745d4fada5c73db44f596a62e29a5dbe3fc53f
      
https://github.com/qemu/qemu/commit/6b745d4fada5c73db44f596a62e29a5dbe3fc53f
  Author: Alistair Francis <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M target/riscv/cpu.c

  Log Message:
  -----------
  target/riscv: Remove unused struct

Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 4e85ea82c1b2cd7c27970b671cd4ca6ef6f78354
      
https://github.com/qemu/qemu/commit/4e85ea82c1b2cd7c27970b671cd4ca6ef6f78354
  Author: Bin Meng <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M hw/riscv/sifive_uart.c

  Log Message:
  -----------
  riscv: sifive_uart: Generate TX interrupt

At present the sifive uart model only generates RX interrupt. This
updates it to generate TX interrupt so that it is more useful.

Note the TX fifo is still unimplemented.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: a9ec1c76d57491602b4d3b521f898905825ca848
      
https://github.com/qemu/qemu/commit/a9ec1c76d57491602b4d3b521f898905825ca848
  Author: Bin Meng <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  riscv: sifive_u: Correct UART0's IRQ in the device tree

The UART0's interrupt vector is wrongly set to 1 in the device tree.
Use SIFIVE_U_UART0_IRQ instead.

Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: b98a66201dbc7cf3b962f4bb260f66100cc75578
      
https://github.com/qemu/qemu/commit/b98a66201dbc7cf3b962f4bb260f66100cc75578
  Author: Peter Maydell <address@hidden>
  Date:   2019-03-19 (Tue, 19 Mar 2019)

  Changed paths:
    M Makefile.objs
    M configure
    M disas/riscv.c
    A gdb-xml/riscv-32bit-cpu.xml
    A gdb-xml/riscv-32bit-csr.xml
    A gdb-xml/riscv-32bit-fpu.xml
    A gdb-xml/riscv-64bit-cpu.xml
    A gdb-xml/riscv-64bit-csr.xml
    A gdb-xml/riscv-64bit-fpu.xml
    M hw/riscv/sifive_plic.c
    M hw/riscv/sifive_u.c
    M hw/riscv/sifive_uart.c
    M include/elf.h
    M linux-user/riscv/cpu_loop.c
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/cpu_user.h
    M target/riscv/csr.c
    M target/riscv/gdbstub.c
    M target/riscv/pmp.c
    A target/riscv/trace-events

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-rc0-2' 
into staging

RISC-V Patches for 4.0-rc0, Part 2

This patch set contains three major sources of bug fixes:

* Jim has added support for GDB XML files, as well as fixing access to
  CSRs via the GDB stub.
* Alistair has rebased a large set of fixes from Michael that were still
  in his patch queue.  These fix bugs all over our tree, including:
    * Logging of PMP errors.
    * User ABI cleanups and fixes, most notably on RVE guests.
    * Fixes for interrupt emulation fidelity.
    * Improvements to the emulation fidelity of the sifive_u machine.
* Bin Meng has improved the emulation fidelity of the SiFive UART, which
  now supports both TX and RX interrupts (as well as setting the correct
  interrupt line).

# gpg: Signature made Tue 19 Mar 2019 12:42:11 GMT
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Palmer Dabbelt <address@hidden>" [unknown]
# gpg:                 aka "Palmer Dabbelt <address@hidden>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-4.0-rc0-2:
  riscv: sifive_u: Correct UART0's IRQ in the device tree
  riscv: sifive_uart: Generate TX interrupt
  target/riscv: Remove unused struct
  riscv: sifive_u: Allow up to 4 CPUs to be created
  RISC-V: Update load reservation comment in do_interrupt
  RISC-V: Convert trap debugging to trace events
  RISC-V: Add support for vectored interrupts
  RISC-V: Change local interrupts from edge to level
  RISC-V: linux-user support for RVE ABI
  elf: Add RISC-V PSABI ELF header defines
  RISC-V: Remove unnecessary disassembler constraints
  RISC-V: Allow interrupt controllers to claim interrupts
  RISC-V: Replace __builtin_popcount with ctpop8 in PLIC
  riscv: pmp: Log pmp access errors as guest errors
  RISC-V: Add hooks to use the gdb xml files.
  RISC-V: Add debug support for accessing CSRs.
  RISC-V: Fixes to CSR_* register macros.
  RISC-V: Add 64-bit gdb xml files.
  RISC-V: Add 32-bit gdb xml files.

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/86e2fca2d7f1...b98a66201dbc