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[Qemu-commits] [qemu/qemu] 161079: vfio/spapr: Fix indirect levels calcu
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From: |
Peter Maydell |
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Subject: |
[Qemu-commits] [qemu/qemu] 161079: vfio/spapr: Fix indirect levels calculation |
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Date: |
Tue, 12 Mar 2019 04:11:58 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 16107998761c1ce97d5c1d56a3e7092acb27d8d1
https://github.com/qemu/qemu/commit/16107998761c1ce97d5c1d56a3e7092acb27d8d1
Author: Alexey Kardashevskiy <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/vfio/spapr.c
M hw/vfio/trace-events
Log Message:
-----------
vfio/spapr: Fix indirect levels calculation
The current code assumes that we can address more bits on a PCI bus
for DMA than we really can but there is no way knowing the actual limit.
This makes a better guess for the number of levels and if the kernel
fails to allocate that, this increases the level numbers till succeeded
or reached the 64bit limit.
This adds levels to the trace point.
This may cause the kernel to warn about failed allocation:
[65122.837458] Failed to allocate a TCE memory, level shift=28
which might happen if MAX_ORDER is not large enough as it can vary:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/Kconfig?h=v5.0-rc2#n727
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3cdd801b0b65ec3fbb9280a2fa22976ad96645b0
https://github.com/qemu/qemu/commit/3cdd801b0b65ec3fbb9280a2fa22976ad96645b0
Author: Alexey Kardashevskiy <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/vfio/spapr.c
Log Message:
-----------
vfio/spapr: Rename local systempagesize variable
The "systempagesize" name suggests that it is the host system page size
while it is the smallest page size of memory backing the guest RAM so
let's rename it to stop confusion. This should cause no behavioral change.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 23ff81bdfd1e8119127779ea67c3a05ce4a6227d
https://github.com/qemu/qemu/commit/23ff81bdfd1e8119127779ea67c3a05ce4a6227d
Author: Greg Kurz <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: Simulate CAS for qtest
The RTAS event hotplug code for machine types 2.8 and newer depends on
the CAS negotiated ov5 in order to work properly. However, there's no
CAS when running under qtest. There has been a tentative to trick the
code by faking the OV5_HP_EVT bit, but it turned out to break other
assumptions in the code and the change got reverted.
Go for a more general approach and simulate a CAS when running under
qtest. For simplicity, this pseudo CAS simple simulates the case where
the guest supports the same features as the machine. It is done at
reset time, just before we reset the DRCs, which could potentially
exercise the unplug code.
This allows to test unplug on spapr with both older and newer machine
types.
Suggested-by: Michael Roth <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Tested-by: Michael Roth <address@hidden>
Reviewed-by: Michael Roth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c65ecfe2f3078156fd5e1e05867f02359a3ce678
https://github.com/qemu/qemu/commit/c65ecfe2f3078156fd5e1e05867f02359a3ce678
Author: Greg Kurz <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/spapr_ovec.c
Log Message:
-----------
Revert "spapr: support memory unplug for qtest"
Commit b8165118f52c broke CPU hotplug tests for old machine types:
$ QTEST_QEMU_BINARY=ppc64-softmmu/qemu-system-ppc64 ./tests/cpu-plug-test
-m=slow
/ppc64/cpu-plug/pseries-3.1/device-add/2x3x1&maxcpus=6: OK
/ppc64/cpu-plug/pseries-2.12-sxxm/device-add/2x3x1&maxcpus=6: OK
/ppc64/cpu-plug/pseries-3.0/device-add/2x3x1&maxcpus=6: OK
/ppc64/cpu-plug/pseries-2.10/device-add/2x3x1&maxcpus=6: OK
/ppc64/cpu-plug/pseries-2.11/device-add/2x3x1&maxcpus=6: OK
/ppc64/cpu-plug/pseries-2.12/device-add/2x3x1&maxcpus=6: OK
/ppc64/cpu-plug/pseries-2.9/device-add/2x3x1&maxcpus=6: OK
/ppc64/cpu-plug/pseries-2.7/device-add/2x3x1&maxcpus=6: **
ERROR:/home/thuth/devel/qemu/hw/ppc/spapr_events.c:313:rtas_event_log_to_source:
assertion failed: (source->enabled)
Broken pipe
/home/thuth/devel/qemu/tests/libqtest.c:143: kill_qemu() detected QEMU death
from signal 6 (Aborted) (core dumped)
Aborted (core dumped)
The approach of faking the availability of OV5_HP_EVT causes the
code to assume the hotplug event source is enabled, which is wrong
for older machines.
We've now fixed CAS under qtest with a different approach. Therefore,
this reverts commit b8165118f52ce5ee88565d3cec83d30374efdc96.
A subsequent patch will address the problem of CAS under qtest from
a different angle.
Reported-by: Thomas Huth <address@hidden>
Signed-off-by: Greg Kurz <address@hidden>
Message-Id: <address@hidden>
Tested-by: Michael Roth <address@hidden>
Reviewed-by: Michael Roth <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c982f5cf9ab9e60a8255f9cc72362c932c252471
https://github.com/qemu/qemu/commit/c982f5cf9ab9e60a8255f9cc72362c932c252471
Author: Suraj Jitindar Singh <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
M include/hw/ppc/spapr.h
Log Message:
-----------
target/ppc/spapr: Add SPAPR_CAP_LARGE_DECREMENTER
Add spapr_cap SPAPR_CAP_LARGE_DECREMENTER to be used to control the
availability of the large decrementer for a guest.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Message-Id: <address@hidden>
[dwg: Trivial style fix]
Signed-off-by: David Gibson <address@hidden>
Commit: a8dafa525181e57405b7ef4bf7c212bf5f6d8ca1
https://github.com/qemu/qemu/commit/a8dafa525181e57405b7ef4bf7c212bf5f6d8ca1
Author: Suraj Jitindar Singh <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/ppc.c
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/mmu-hash64.c
M target/ppc/translate.c
M target/ppc/translate_init.inc.c
Log Message:
-----------
target/ppc: Implement large decrementer support for TCG
Prior to POWER9 the decrementer was a 32-bit register which decremented
with each tick of the timebase. From POWER9 onwards the decrementer can
be set to operate in a mode called large decrementer where it acts as a
n-bit decrementing register which is visible as a 64-bit register, that
is the value of the decrementer is sign extended to 64 bits (where n is
implementation dependant).
The mode in which the decrementer operates is controlled by the LPCR_LD
bit in the logical paritition control register (LPCR).
>From POWER9 onwards the HDEC (hypervisor decrementer) was enlarged to
h-bits, also sign extended to 64 bits (where h is implementation
dependant). Note this isn't configurable and is always enabled.
On POWER9 the large decrementer and hdec are both 56 bits, as
represented by the lrg_decr_bits cpu class property. Since they are the
same size we only add one property for now, which could be extended in
the case they ever differ in the future.
We also add the lrg_decr_bits property for POWER5+/7/8 since it is used
to determine the size of the hdec, which is only generated on the
POWER5+ processor and later. On these processors it is 32 bits.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
[dwg: Small style fixes]
Signed-off-by: David Gibson <address@hidden>
Commit: 7d050527e3f5cadbf9db3bce09409fb4e9259997
https://github.com/qemu/qemu/commit/7d050527e3f5cadbf9db3bce09409fb4e9259997
Author: Suraj Jitindar Singh <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/spapr_caps.c
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
Log Message:
-----------
target/ppc: Implement large decrementer support for KVM
Implement support to allow KVM guests to take advantage of the large
decrementer introduced on POWER9 cpus.
To determine if the host can support the requested large decrementer
size, we check it matches that specified in the ibm,dec-bits device-tree
property. We also need to enable it in KVM by setting the LPCR_LD bit in
the LPCR. Note that to do this we need to try and set the bit, then read
it back to check the host allowed us to set it, if so we can use it but
if we were unable to set it the host cannot support it and we must not
use the large decrementer.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
[dwg: Small style fixes]
Signed-off-by: David Gibson <address@hidden>
Commit: edaa7995591eb51c9ae2c82267ca443f6921ff89
https://github.com/qemu/qemu/commit/edaa7995591eb51c9ae2c82267ca443f6921ff89
Author: Suraj Jitindar Singh <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
Log Message:
-----------
target/ppc/spapr: Enable the large decrementer for pseries-4.0
Enable the large decrementer by default for the pseries-4.0 machine type.
It is disabled again by default_caps_with_cpu() for pre-POWER9 cpus
since they don't support the large decrementer.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 399b2896d4948a1ec0278d896ea3a561df768d64
https://github.com/qemu/qemu/commit/399b2896d4948a1ec0278d896ea3a561df768d64
Author: Suraj Jitindar Singh <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/spapr_caps.c
M hw/ppc/spapr_hcall.c
M include/hw/ppc/spapr.h
M target/ppc/kvm.c
Log Message:
-----------
target/ppc/spapr: Add workaround option to SPAPR_CAP_IBS
The spapr_cap SPAPR_CAP_IBS is used to indicate the level of capability
for mitigations for indirect branch speculation. Currently the available
values are broken (default), fixed-ibs (fixed by serialising indirect
branches) and fixed-ccd (fixed by diabling the count cache).
Introduce a new value for this capability denoted workaround, meaning that
software can work around the issue by flushing the count cache on
context switch. This option is available if the hypervisor sets the
H_CPU_BEHAV_FLUSH_COUNT_CACHE flag in the cpu behaviours returned from
the KVM_PPC_GET_CPU_CHAR ioctl.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 8ff43ee404d3e295839d1fd4e9e6571ca7a62a66
https://github.com/qemu/qemu/commit/8ff43ee404d3e295839d1fd4e9e6571ca7a62a66
Author: Suraj Jitindar Singh <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
M hw/ppc/spapr_hcall.c
M include/hw/ppc/spapr.h
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
Log Message:
-----------
target/ppc/spapr: Add SPAPR_CAP_CCF_ASSIST
Introduce a new spapr_cap SPAPR_CAP_CCF_ASSIST to be used to indicate
the requirement for a hw-assisted version of the count cache flush
workaround.
The count cache flush workaround is a software workaround which can be
used to flush the count cache on context switch. Some revisions of
hardware may have a hardware accelerated flush, in which case the
software flush can be shortened. This cap is used to set the
availability of such hardware acceleration for the count cache flush
routine.
The availability of such hardware acceleration is indicated by the
H_CPU_CHAR_BCCTR_FLUSH_ASSIST flag being set in the characteristics
returned from the KVM_PPC_GET_CPU_CHAR ioctl.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Message-Id: <address@hidden>
[dwg: Small style fixes]
Signed-off-by: David Gibson <address@hidden>
Commit: 006e9d3618698eeef2f3e07628d22cb6f5c2a039
https://github.com/qemu/qemu/commit/006e9d3618698eeef2f3e07628d22cb6f5c2a039
Author: Suraj Jitindar Singh <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/spapr_caps.c
Log Message:
-----------
target/ppc/tcg: make spapr_caps apply cap-[cfpc/sbbc/ibs] non-fatal for tcg
The spapr_caps cap-cfpc, cap-sbbc and cap-ibs are used to control the
availability of certain mitigations to the guest. These haven't been
implemented under TCG, it is unlikely they ever will be, and it is unclear
as to whether they even need to be.
As such, make failure to apply these capabilities under TCG non-fatal.
Instead we print a warning message to the user but still allow the guest
to continue.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Message-Id: <address@hidden>
[dwg: Small style fix]
Signed-off-by: David Gibson <address@hidden>
Commit: 2782ad4c4102d57f7f8e135dce0c1adb0149de77
https://github.com/qemu/qemu/commit/2782ad4c4102d57f7f8e135dce0c1adb0149de77
Author: Suraj Jitindar Singh <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
target/ppc/spapr: Enable mitigations by default for pseries-4.0 machine type
There are currently 3 mitigations the availability of which is controlled
by the spapr-caps mechanism, cap-cfpc, cap-sbbc, and cap-ibs. Enable these
mitigations by default for the pseries-4.0 machine type.
By now machine firmware should have been upgraded to allow these
settings.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2586a4d7a07b6be3fc54d9618a154b5b25fbf977
https://github.com/qemu/qemu/commit/2586a4d7a07b6be3fc54d9618a154b5b25fbf977
Author: Fabiano Rosas <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M target/ppc/excp_helper.c
Log Message:
-----------
target/ppc: Move exception vector offset computation into a function
Signed-off-by: Fabiano Rosas <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2cbd158131e5a5e392417fb4511075a5d2af1bdd
https://github.com/qemu/qemu/commit/2cbd158131e5a5e392417fb4511075a5d2af1bdd
Author: Fabiano Rosas <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M target/ppc/kvm.c
Log Message:
-----------
target/ppc: Move handling of hardware breakpoints to a separate function
This is in preparation for a refactoring of the kvm_handle_debug
function in the next patch.
Signed-off-by: Fabiano Rosas <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 468e3a1a9495bdbf679b1344de7e390e90696a56
https://github.com/qemu/qemu/commit/468e3a1a9495bdbf679b1344de7e390e90696a56
Author: Fabiano Rosas <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M target/ppc/kvm.c
Log Message:
-----------
target/ppc: Refactor kvm_handle_debug
There are four scenarios being handled in this function:
- single stepping
- hardware breakpoints
- software breakpoints
- fallback (no debug supported)
A future patch will add code to handle specific single step and
software breakpoints cases so let's split each scenario into its own
function now to avoid hurting readability.
Signed-off-by: Fabiano Rosas <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f2a3b549e357041f86d7e61432e4d7e522859b58
https://github.com/qemu/qemu/commit/f2a3b549e357041f86d7e61432e4d7e522859b58
Author: Alexander Graf <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M pc-bios/u-boot.e500
M roms/u-boot
Log Message:
-----------
PPC: E500: Update u-boot to v2019.01
Quite a while has passed since we last updated U-Boot for e500. This patch
bumps it to the last released version 2019.01 to make sure users don't feel
like they're using out of date software.
Signed-off-by: Alexander Graf <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 176dcceedd084bc2db0a3e92123e2cfb453336e7
https://github.com/qemu/qemu/commit/176dcceedd084bc2db0a3e92123e2cfb453336e7
Author: Suraj Jitindar Singh <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_hcall.c
Log Message:
-----------
target/ppc/spapr: Clear partition table entry when allocating hash table
If we allocate a hash page table then we know that the guest won't be
using process tables, so set the partition table entry maintained for
the guest to zero. If this isn't done, then the guest radix bit will
remain set in the entry. This means that when the guest calls
H_REGISTER_PROCESS_TABLE there will be a mismatch between then flags
and the value in spapr->patb_entry, and the call will fail. The guest
will then panic:
Failed to register process table (rc=-4)
kernel BUG at arch/powerpc/platforms/pseries/lpar.c:959
The result being that it isn't possible to boot a hash guest on a P9
system.
Also fix a bug in the flags parsing in h_register_process_table() which
was introduced by the same patch, and simplify the handling to make it
less likely that errors will be introduced in the future. The effect
would have been setting the host radix bit LPCR_HR for a hash guest
using process tables, which currently isn't supported and so couldn't
have been triggered.
Fixes: 00fd075e18 "target/ppc/spapr: Set LPCR:HR when using Radix mode"
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e075623aa517b0690ec978772df008d7e00ebce5
https://github.com/qemu/qemu/commit/e075623aa517b0690ec978772df008d7e00ebce5
Author: David Gibson <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr: Force SPAPR_MEMORY_BLOCK_SIZE to be a hwaddr (64-bit)
SPAPR_MEMORY_BLOCK_SIZE is logically a difference in memory addresses, and
hence of type hwaddr which is 64-bit. Previously it wasn't marked as such
which means that it could be treated as 32-bit. That will work in some
circumstances but if multiplied by another 32-bit value it could lead to
a 32-bit overflow and an incorrect result.
One specific instance of this in spapr_lmb_dt_populate() was spotted by
Coverity (CID 1399145).
Reported-by: Peter Maydell <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 68f9f7084146b48acb68c606b81edcb04d69d41c
https://github.com/qemu/qemu/commit/68f9f7084146b48acb68c606b81edcb04d69d41c
Author: Suraj Jitindar Singh <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/spapr.c
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
Log Message:
-----------
target/ppc/spapr: Enable H_PAGE_INIT in-kernel handling
The H_CALL H_PAGE_INIT can be used to zero or copy a page of guest
memory. Enable the in-kernel H_PAGE_INIT handler.
The in-kernel handler takes half the time to complete compared to
handling the H_CALL in userspace.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 7abb479c7abd1f03da09f34cd77d25ecf66aac82
https://github.com/qemu/qemu/commit/7abb479c7abd1f03da09f34cd77d25ecf66aac82
Author: Andrew Randrianasulu <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M MAINTAINERS
M default-configs/ppc-softmmu.mak
M hw/i2c/Kconfig
M hw/i2c/Makefile.objs
A hw/i2c/mpc_i2c.c
M hw/ppc/e500.c
Log Message:
-----------
PPC: E500: Add FSL I2C controller and integrate RTC with it
Original commit message:
This patch adds an emulation model for i2c controller found on most of the FSL
SoCs.
It also integrates the RTC (ds1338) that sits on the i2c Bus with e500 machine
model.
Patch was originally written by Amit Singh Tomar <address@hidden>
see http://patchwork.ozlabs.org/patch/431475/
I only fixed it enough for application on top of current qemu master
20b084c4b1401b7f8fbc385649d48c67b6f43d44, and hopefully fixed checkpatch errors
Tested by booting Linux kernel 4.20.12. Now e500 machine doesn't need
network time protocol daemon because it will have working RTC
(before all timestamps on files were from 2016)
Signed-off-by: Amit Singh Tomar <address@hidden>
Signed-off-by: Andrew Randrianasulu <address@hidden>
Message-Id: <address@hidden>
[dwg: Add Kconfig stanza to define the new symbol, update MAINTAINERS]
Signed-off-by: David Gibson <address@hidden>
Commit: d514c48d41fba59ac492433071bad70c445db566
https://github.com/qemu/qemu/commit/d514c48d41fba59ac492433071bad70c445db566
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
ppc/xive: hardwire the Physical CAM line of the thread context
By default on P9, the HW CAM line (23bits) is hardwired to :
0x000||0b1||4Bit chip number||7Bit Thread number.
When the block group mode is enabled at the controller level (PowerNV),
the CAM line is changed for CAM compares to :
4Bit chip number||0x001||7Bit Thread number
This will require changes in xive_presenter_tctx_match() possibly.
This is a lowlevel functionality of the HW controller and it is not
strictly needed. Leave it for later.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 051e2973bf24f0f6e622e35de7c9d1803e5c23d3
https://github.com/qemu/qemu/commit/051e2973bf24f0f6e622e35de7c9d1803e5c23d3
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/ppc.c
M include/hw/ppc/ppc.h
Log Message:
-----------
ppc: externalize ppc_get_vcpu_by_pir()
We will use it to get the CPU interrupt presenter in XIVE when the
TIMA is accessed from the indirect page.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f9b9db38601f3e997eea783b8d513fcc301f3283
https://github.com/qemu/qemu/commit/f9b9db38601f3e997eea783b8d513fcc301f3283
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/intc/xive.c
M include/hw/ppc/xive.h
Log Message:
-----------
ppc/xive: export the TIMA memory accessors
The PowerNV machine can perform indirect loads and stores on the TIMA
on behalf of another CPU. Give the controller the possibility to call
the TIMA memory accessors with a XiveTCTX of its choice.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: a58a18adee0421bd704265ec14a6805f734d3dab
https://github.com/qemu/qemu/commit/a58a18adee0421bd704265ec14a6805f734d3dab
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/intc/xive.c
M include/hw/ppc/xive.h
Log Message:
-----------
ppc/pnv: export the xive_router_notify() routine
The PowerNV machine with need to encode the block id in the source
interrupt number before forwarding the source event notification to
the Router.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 956b8f468da280ad597fb3fe31a9b1ada441a897
https://github.com/qemu/qemu/commit/956b8f468da280ad597fb3fe31a9b1ada441a897
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
M include/hw/ppc/pnv_core.h
Log Message:
-----------
ppc/pnv: change the CPU machine_data presenter type to Object *
The POWER9 PowerNV machine will use a XIVE interrupt presenter type.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2dfa91a2aa5a84aa0e7b68517e58793717d41b32
https://github.com/qemu/qemu/commit/2dfa91a2aa5a84aa0e7b68517e58793717d41b32
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/intc/Makefile.objs
A hw/intc/pnv_xive.c
A hw/intc/pnv_xive_regs.h
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
A include/hw/ppc/pnv_xive.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: add a XIVE interrupt controller model for POWER9
This is a simple model of the POWER9 XIVE interrupt controller for the
PowerNV machine which only addresses the needs of the skiboot
firmware. The PowerNV model reuses the common XIVE framework developed
for sPAPR as the fundamentals aspects are quite the same. The
difference are outlined below.
The controller initial BAR configuration is performed using the XSCOM
bus from there, MMIO are used for further configuration.
The MMIO regions exposed are :
- Interrupt controller registers
- ESB pages for IPIs and ENDs
- Presenter MMIO (Not used)
- Thread Interrupt Management Area MMIO, direct and indirect
The virtualization controller MMIO region containing the IPI ESB pages
and END ESB pages is sub-divided into "sets" which map portions of the
VC region to the different ESB pages. These are modeled with custom
address spaces and the XiveSource and XiveENDSource objects are sized
to the maximum allowed by HW. The memory regions are resized at
run-time using the configuration of EDT set translation table provided
by the firmware.
The XIVE virtualization structure tables (EAT, ENDT, NVTT) are now in
the machine RAM and not in the hypervisor anymore. The firmware
(skiboot) configures these tables using Virtual Structure Descriptor
defining the characteristics of each table : SBE, EAS, END and
NVT. These are later used to access the virtual interrupt entries. The
internal cache of these tables in the interrupt controller is updated
and invalidated using a set of registers.
Still to address to complete the model but not fully required is the
support for block grouping. Escalation support will be necessary for
KVM guests.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: eb859a27e1ebeeeaff096a0c041d9f75c9f7a722
https://github.com/qemu/qemu/commit/eb859a27e1ebeeeaff096a0c041d9f75c9f7a722
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: introduce a new dt_populate() operation to the chip model
The POWER9 and POWER8 processors have a different set of devices and a
different device tree layout.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d8e4aad533573b6237b5da6ceb06027fc4eac9c7
https://github.com/qemu/qemu/commit/d8e4aad533573b6237b5da6ceb06027fc4eac9c7
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: introduce a new pic_print_info() operation to the chip model
The POWER9 and POWER8 processors have different interrupt controllers,
and reporting their state requires calling different helper routines.
However, the interrupt presenters are still handled in the higher
level pic_print_info() routine because they are not related to the
chip.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 4836b45510aa84da52a29bf5a23794f71a29d98b
https://github.com/qemu/qemu/commit/4836b45510aa84da52a29bf5a23794f71a29d98b
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
ppc/xive: activate HV support
The NSR register of the HV ring has a different, although similar, bit
layout. TM_QW3_NSR_HE_PHYS bit should now be raised when the
Hypervisor interrupt line is signaled. Other bits TM_QW3_NSR_HE_POOL
and TM_QW3_NSR_HE_LSI are not modeled. LSI are for special interrupts
reserved for HW bringup and the POOL bit is used when signaling a
group of VPs. This is not currently implemented in Linux but it is in
pHyp.
The most important special commands on the HV TIMA page are added to
let the core manage interrupts : acking and changing the CPU priority.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: cdbaf8cd9af5e1377a09b059a4ba749bfb58a8d5
https://github.com/qemu/qemu/commit/cdbaf8cd9af5e1377a09b059a4ba749bfb58a8d5
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv_lpc.c
M hw/ppc/pnv_psi.c
Log Message:
-----------
ppc/pnv: fix logging primitives using Ox
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 029699aa0483d195f96cdbece8a0f8d02081bb70
https://github.com/qemu/qemu/commit/029699aa0483d195f96cdbece8a0f8d02081bb70
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv_psi.c
Log Message:
-----------
ppc/pnv: psi: add a PSIHB_REG macro
This is a simple helper to translate XSCOM addresses to MMIO addresses
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f7eb6a0a9b9326d3daae4bf0d9c664c8e79bea39
https://github.com/qemu/qemu/commit/f7eb6a0a9b9326d3daae4bf0d9c664c8e79bea39
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv_psi.c
Log Message:
-----------
ppc/pnv: psi: add a reset handler
Reset all regs but keep the MMIO BAR enabled as it is at realize time.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5f3666672255cbd00ce96fb5688dfca25a4c4d55
https://github.com/qemu/qemu/commit/5f3666672255cbd00ce96fb5688dfca25a4c4d55
Author: Alexey Kardashevskiy <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/spapr_iommu.c
M hw/ppc/spapr_rtas_ddw.c
M include/hw/ppc/spapr.h
Log Message:
-----------
spapr_iommu: Do not replay mappings from just created DMA window
On sPAPR vfio_listener_region_add() is called in 2 situations:
1. a new listener is registered from vfio_connect_container();
2. a new IOMMU Memory Region is added from rtas_ibm_create_pe_dma_window().
In both cases vfio_listener_region_add() calls
memory_region_iommu_replay() to notify newly registered IOMMU notifiers
about existing mappings which is totally desirable for case 1.
However for case 2 it is nothing but noop as the window has just been
created and has no valid mappings so replaying those does not do anything.
It is barely noticeable with usual guests but if the window happens to be
really big, such no-op replay might take minutes and trigger RCU stall
warnings in the guest.
For example, a upcoming GPU RAM memory region mapped at 64TiB (right
after SPAPR_PCI_LIMIT) causes a 64bit DMA window to be at least 128TiB
which is (128<<40)/0x10000=2.147.483.648 TCEs to replay.
This mitigates the problem by adding an "skipping_replay" flag to
sPAPRTCETable and defining sPAPR own IOMMU MR replay() hook which does
exactly the same thing as the generic one except it returns early if
@skipping_replay==true.
Another way of fixing this would be delaying replay till the very first
H_PUT_TCE but this does not work if in-kernel H_PUT_TCE handler is
enabled (a likely case).
When "ibm,create-pe-dma-window" is complete, the guest will map only
required regions of the huge DMA window.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e7d3b272ed49a531c1c852fe979a33ee3d45d19f
https://github.com/qemu/qemu/commit/e7d3b272ed49a531c1c852fe979a33ee3d45d19f
Author: Mark Cave-Ayland <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M target/ppc/cpu.h
M target/ppc/translate.c
Log Message:
-----------
target/ppc: introduce single fpr_offset() function
Instead of having multiple copies of the offset calculation logic, move it to a
single fpr_offset() function.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 45141dfd2372bd07532417e27b713ef6edbca12e
https://github.com/qemu/qemu/commit/45141dfd2372bd07532417e27b713ef6edbca12e
Author: Mark Cave-Ayland <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M target/ppc/cpu.h
M target/ppc/translate/vsx-impl.inc.c
Log Message:
-----------
target/ppc: introduce single vsrl_offset() function
Instead of having multiple copies of the offset calculation logic, move it to a
single vsrl_offset() function.
This commit also renames the existing get_vsr()/set_vsr() functions to
get_vsrl()/set_vsrl() which better describes their purpose.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: da7815ef31ff371427991cc90a3beef2ce0cc861
https://github.com/qemu/qemu/commit/da7815ef31ff371427991cc90a3beef2ce0cc861
Author: Mark Cave-Ayland <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M target/ppc/cpu.h
M target/ppc/internal.h
Log Message:
-----------
target/ppc: move Vsr* macros from internal.h to cpu.h
It isn't possible to include internal.h from cpu.h so move the Vsr* macros
into cpu.h alongside the other VMX/VSX register access functions.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c82a8a8542bee54824ea83856d33ad7656570a06
https://github.com/qemu/qemu/commit/c82a8a8542bee54824ea83856d33ad7656570a06
Author: Mark Cave-Ayland <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M target/ppc/cpu.h
M target/ppc/translate/vmx-impl.inc.c
M target/ppc/translate/vsx-impl.inc.c
Log Message:
-----------
target/ppc: introduce avr_full_offset() function
All TCG vector operations require pointers to the base address of the vector
rather than separate access to the top and bottom 64-bits. Convert the VMX TCG
instructions to use a new avr_full_offset() function instead of avr64_offset()
which can then itself be written as a simple wrapper onto vsr_full_offset().
This same function can also reused in cpu_avr_ptr() to avoid having more than
one copy of the offset calculation logic.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 37da91f163d2ec808cca4f1662499dbe07f858e1
https://github.com/qemu/qemu/commit/37da91f163d2ec808cca4f1662499dbe07f858e1
Author: Mark Cave-Ayland <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M target/ppc/cpu.h
M target/ppc/translate.c
M target/ppc/translate/vmx-impl.inc.c
Log Message:
-----------
target/ppc: improve avr64_offset() and use it to simplify
get_avr64()/set_avr64()
By using the VsrD macro in avr64_offset() the same offset calculation can be
used regardless of the host endian. This allows get_avr64() and set_avr64() to
be simplified accordingly.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 8a14d31b00ae82ed430806bac96962b73fe6967f
https://github.com/qemu/qemu/commit/8a14d31b00ae82ed430806bac96962b73fe6967f
Author: Mark Cave-Ayland <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M target/ppc/cpu.h
M target/ppc/internal.h
M target/ppc/machine.c
Log Message:
-----------
target/ppc: switch fpr/vsrl registers so all VSX registers are in host endian
order
When VSX support was initially added, the fpr registers were added at
offset 0 of the VSR register and the vsrl registers were added at offset
1. This is in contrast to the VMX registers (the last 32 VSX registers) which
are stored in host-endian order.
Switch the fpr/vsrl registers so that the lower 32 VSX registers are now also
stored in host endian order to match the VMX registers. This ensures that TCG
vector operations involving mixed VMX and VSX registers will function
correctly.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d59d1182b14fcdad350108012fb015e6c2d355f0
https://github.com/qemu/qemu/commit/d59d1182b14fcdad350108012fb015e6c2d355f0
Author: Mark Cave-Ayland <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M target/ppc/cpu.h
M target/ppc/translate/vsx-impl.inc.c
Log Message:
-----------
target/ppc: introduce vsr64_offset() to simplify get_cpu_vsr{l,h}() and
set_cpu_vsr{l,h}()
Now that all VSX registers are stored in host endian order, there is no need
to go via different accessors depending upon the register number. Instead we
introduce vsr64_offset() and use it directly from within get_cpu_vsr{l,h}() and
set_cpu_vsr{l,h}().
This also allows us to rewrite avr64_offset() and fpr_offset() in terms of the
new vsr64_offset() function to more clearly express the relationship between the
VSX, FPR and VMX registers, and also remove vsrl_offset() which is no longer
required.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 484d366e02732c8de6f92e53e2ee9bb93dd4ca23
https://github.com/qemu/qemu/commit/484d366e02732c8de6f92e53e2ee9bb93dd4ca23
Author: Mark Cave-Ayland <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/mac_oldworld.c
Log Message:
-----------
mac_oldworld: use node name instead of alias name for hd device in
FWPathProvider
When using -drive to configure the hd drive for the Old World machine, the node
name "disk" should be used instead of the "hd" alias.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 31bc6fa7fa8124ff8fb08373f9402985c806919f
https://github.com/qemu/qemu/commit/31bc6fa7fa8124ff8fb08373f9402985c806919f
Author: Mark Cave-Ayland <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/mac_newworld.c
Log Message:
-----------
mac_newworld: use node name instead of alias name for hd device in
FWPathProvider
When using -drive to configure the hd drive for the New World machine, the node
name "disk" should be used instead of the "hd" alias.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ae85605531cde2856d0b37804dc9a32028d89a34
https://github.com/qemu/qemu/commit/ae85605531cde2856d0b37804dc9a32028d89a34
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_psi.c
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_psi.h
Log Message:
-----------
ppc/pnv: add a PSI bridge class model
To ease the introduction of the PSI bridge model for POWER9, abstract
the POWER chip differences in a PnvPsi class model and introduce a
specific Pnv8Psi type for POWER8. POWER8 interface to the interrupt
controller is still XICS whereas POWER9 uses the new XIVE model.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c38536bc80fa0b8f44db50a3190bfd241143ab0b
https://github.com/qemu/qemu/commit/c38536bc80fa0b8f44db50a3190bfd241143ab0b
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_psi.c
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_psi.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: add a PSI bridge model for POWER9
The PSI bridge on POWER9 is very similar to POWER8. The BAR is still
set through XSCOM but the controls are now entirely done with MMIOs.
More interrupts are defined and the interrupt controller interface has
changed to XIVE. The POWER9 model is a first example of the usage of
the notify() handler of the XiveNotifier interface, linking the PSI
XiveSource to its owning device model.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 6f89f48e56723005b64260d2ab079a015db3ed64
https://github.com/qemu/qemu/commit/6f89f48e56723005b64260d2ab079a015db3ed64
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv_lpc.c
Log Message:
-----------
ppc/pnv: lpc: fix OPB address ranges
The PowerNV LPC Controller exposes different sets of registers for
each of the functional units it encompasses, among which the OPB
(On-Chip Peripheral Bus) Master and Arbitrer and the LPC HOST
Controller.
The mapping addresses of each register range are correct but the sizes
are too large. Fix the sizes and define the OPB Arbitrer range to fill
the gap between the OPB Master registers and the LPC HOST Controller
registers.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 82514be28b02d8f347ceda9008df6bb5c2f0acef
https://github.com/qemu/qemu/commit/82514be28b02d8f347ceda9008df6bb5c2f0acef
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_lpc.c
M include/hw/ppc/pnv_lpc.h
Log Message:
-----------
ppc/pnv: add a LPC Controller class model
It will ease the introduction of the LPC Controller model for POWER9.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 64d011d56ea2cd72f8f8c937526f851685296231
https://github.com/qemu/qemu/commit/64d011d56ea2cd72f8f8c937526f851685296231
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: add a 'dt_isa_nodename' to the chip
The ISA bus has a different DT nodename on POWER9. Compute the name
when the PnvChip is realized, that is before it is used by the machine
to populate the device tree with the ISA devices.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 15376c66fab71fc66d2b1c9ade3359474746ddba
https://github.com/qemu/qemu/commit/15376c66fab71fc66d2b1c9ade3359474746ddba
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_lpc.c
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_lpc.h
Log Message:
-----------
ppc/pnv: add a LPC Controller model for POWER9
The LPC Controller on POWER9 is very similar to the one found on
POWER8 but accesses are now done via on MMIOs, without the XSCOM and
ECCB logic. The device tree is populated differently so we add a
specific POWER9 routine for the purpose.
SerIRQ routing is yet to be done.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 8207b90604b60fb70e6c99adcabe9424a7fc90d1
https://github.com/qemu/qemu/commit/8207b90604b60fb70e6c99adcabe9424a7fc90d1
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv_lpc.c
M include/hw/ppc/pnv_lpc.h
Log Message:
-----------
ppc/pnv: add SerIRQ routing registers
This is just a simple reminder that SerIRQ routing should be
addressed.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 3233838cd18014bc18f5c449e70af97d927475da
https://github.com/qemu/qemu/commit/3233838cd18014bc18f5c449e70af97d927475da
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_occ.c
M include/hw/ppc/pnv_occ.h
Log Message:
-----------
ppc/pnv: add a OCC model class
To ease the introduction of the OCC model for POWER9, provide a new
class attributes to define XSCOM operations per CPU family and a PSI
IRQ number.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 6598a70d00cd3a58acbd290d52067902c64d4480
https://github.com/qemu/qemu/commit/6598a70d00cd3a58acbd290d52067902c64d4480
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_occ.c
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_occ.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: add a OCC model for POWER9
The OCC on POWER9 is very similar to the one found on POWER8. Provide
the same routines with P9 values for the registers and IRQ number.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 90ef386c74b1b2c485b69a1bdb24895bebd45502
https://github.com/qemu/qemu/commit/90ef386c74b1b2c485b69a1bdb24895bebd45502
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv_core.c
M include/hw/ppc/pnv_core.h
Log Message:
-----------
ppc/pnv: extend XSCOM core support for POWER9
Provide a new class attribute to define XSCOM operations per CPU
family and add a couple of XSCOM addresses controlling the power
management states of the core on POWER9.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 5dad902ce09877a97a6f32e5f6c75b4f8506bd73
https://github.com/qemu/qemu/commit/5dad902ce09877a97a6f32e5f6c75b4f8506bd73
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_core.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: POWER9 XSCOM quad support
The POWER9 processor does not support per-core frequency control. The
cores are arranged in groups of four, along with their respective L2
and L3 caches, into a structure known as a Quad. The frequency must be
managed at the Quad level.
Provide a basic Quad model to fake the settings done by the firmware
on the Non-Cacheable Unit (NCU). Each core pair (EX) needs a special
BAR setting for the TIMA area of XIVE because it resides on the same
address on all chips.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e5a0c52ac25809e4a812408bc5cce27b63ac9c71
https://github.com/qemu/qemu/commit/e5a0c52ac25809e4a812408bc5cce27b63ac9c71
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M tests/pnv-xscom-test.c
Log Message:
-----------
ppc/pnv: activate XSCOM tests for POWER9
We now have enough support to let the XSCOM test run on POWER9.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: bc56511668355fed8768a45a64142ed66f697de0
https://github.com/qemu/qemu/commit/bc56511668355fed8768a45a64142ed66f697de0
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv_xscom.c
Log Message:
-----------
ppc/pnv: add more dummy XSCOM addresses
To improve OPAL/skiboot support. We don't need to strictly model these
XSCOM accesses.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e5694793ee94d762749e8cbee75dbdbb8a84a24b
https://github.com/qemu/qemu/commit/e5694793ee94d762749e8cbee75dbdbb8a84a24b
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: add a "ibm,opal/power-mgt" device tree node on POWER9
Activate only stop0 and stop1 levels. We should not need more levels
when under QEMU.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: da874d90adb05c2f4364ed3590bbc2947f00cadb
https://github.com/qemu/qemu/commit/da874d90adb05c2f4364ed3590bbc2947f00cadb
Author: Cédric Le Goater <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M target/ppc/translate_init.inc.c
Log Message:
-----------
target/ppc: add HV support for POWER9
We now have enough support to boot a PowerNV machine with a POWER9
processor. Allow HV mode on POWER9.
Signed-off-by: Cédric Le Goater <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: cde0a41c12cd03e860b8d13d0a0452397415c9ce
https://github.com/qemu/qemu/commit/cde0a41c12cd03e860b8d13d0a0452397415c9ce
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
Log Message:
-----------
target/ppc: Optimize xviexpdp() using deposit_i64()
The t0 tcg_temp register is now unused, remove it.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: dd977e4f45cba191fd65c84204cbceffc3bab48a
https://github.com/qemu/qemu/commit/dd977e4f45cba191fd65c84204cbceffc3bab48a
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M target/ppc/translate/vsx-impl.inc.c
Log Message:
-----------
target/ppc: Optimize x[sv]xsigdp using deposit_i64()
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ce2918cbc31e190e7d644c684dcc2bbcb6b9a9df
https://github.com/qemu/qemu/commit/ce2918cbc31e190e7d644c684dcc2bbcb6b9a9df
Author: David Gibson <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/char/spapr_vty.c
M hw/intc/spapr_xive.c
M hw/intc/xics_kvm.c
M hw/intc/xics_spapr.c
M hw/net/spapr_llan.c
M hw/nvram/spapr_nvram.c
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_drc.c
M hw/ppc/spapr_events.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_iommu.c
M hw/ppc/spapr_irq.c
M hw/ppc/spapr_ovec.c
M hw/ppc/spapr_pci.c
M hw/ppc/spapr_pci_vfio.c
M hw/ppc/spapr_rng.c
M hw/ppc/spapr_rtas.c
M hw/ppc/spapr_rtas_ddw.c
M hw/ppc/spapr_rtc.c
M hw/ppc/spapr_vio.c
M hw/scsi/spapr_vscsi.c
M include/hw/pci-host/spapr.h
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_cpu_core.h
M include/hw/ppc/spapr_drc.h
M include/hw/ppc/spapr_irq.h
M include/hw/ppc/spapr_ovec.h
M include/hw/ppc/spapr_vio.h
M include/hw/ppc/spapr_xive.h
M include/hw/ppc/xics_spapr.h
M target/ppc/kvm.c
Log Message:
-----------
spapr: Use CamelCase properly
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <address@hidden>
Commit: ba3b40de424304c497ca4ff990dd24e37aff5f5b
https://github.com/qemu/qemu/commit/ba3b40de424304c497ca4ff990dd24e37aff5f5b
Author: David Gibson <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M tests/boot-serial-test.c
M tests/prom-env-test.c
M tests/pxe-test.c
Log Message:
-----------
Suppress test warnings about missing Spectre/Meltdown mitigations with TCG
The new pseries-4.0 machine type defaults to enabling Spectre/Meltdown
mitigations. Unfortunately those mitigations aren't implemented for TCG
because we're not yet sure if they're necessary or how to implement them.
We don't fail fatally, but we do warn in this case, because it is quite
plausible that Spectre/Meltdown can be exploited through TCG (at least for
the guest to get access to the qemu address space).
This create noise in our testcases though. So, modify the affected tests
to explicitly disable the mitigations to suppress these warnings.
Signed-off-by: David Gibson <address@hidden>
Commit: 013002f0fbf62545c0f5ea4c5c2d554a85919647
https://github.com/qemu/qemu/commit/013002f0fbf62545c0f5ea4c5c2d554a85919647
Author: Alexey Kardashevskiy <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M hw/vfio/common.c
M include/hw/vfio/vfio-common.h
Log Message:
-----------
vfio: Make vfio_get_region_info_cap public
This makes vfio_get_region_info_cap() to be used in quirks.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Acked-by: Alex Williamson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: bc76b7148993269608c19fd3f2fc6ed3e22bf838
https://github.com/qemu/qemu/commit/bc76b7148993269608c19fd3f2fc6ed3e22bf838
Author: Peter Maydell <address@hidden>
Date: 2019-03-12 (Tue, 12 Mar 2019)
Changed paths:
M MAINTAINERS
M default-configs/ppc-softmmu.mak
M hw/char/spapr_vty.c
M hw/i2c/Kconfig
M hw/i2c/Makefile.objs
A hw/i2c/mpc_i2c.c
M hw/intc/Makefile.objs
A hw/intc/pnv_xive.c
A hw/intc/pnv_xive_regs.h
M hw/intc/spapr_xive.c
M hw/intc/xics_kvm.c
M hw/intc/xics_spapr.c
M hw/intc/xive.c
M hw/net/spapr_llan.c
M hw/nvram/spapr_nvram.c
M hw/ppc/e500.c
M hw/ppc/mac_newworld.c
M hw/ppc/mac_oldworld.c
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
M hw/ppc/pnv_lpc.c
M hw/ppc/pnv_occ.c
M hw/ppc/pnv_psi.c
M hw/ppc/pnv_xscom.c
M hw/ppc/ppc.c
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_drc.c
M hw/ppc/spapr_events.c
M hw/ppc/spapr_hcall.c
M hw/ppc/spapr_iommu.c
M hw/ppc/spapr_irq.c
M hw/ppc/spapr_ovec.c
M hw/ppc/spapr_pci.c
M hw/ppc/spapr_pci_vfio.c
M hw/ppc/spapr_rng.c
M hw/ppc/spapr_rtas.c
M hw/ppc/spapr_rtas_ddw.c
M hw/ppc/spapr_rtc.c
M hw/ppc/spapr_vio.c
M hw/scsi/spapr_vscsi.c
M hw/vfio/common.c
M hw/vfio/spapr.c
M hw/vfio/trace-events
M include/hw/pci-host/spapr.h
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_core.h
M include/hw/ppc/pnv_lpc.h
M include/hw/ppc/pnv_occ.h
M include/hw/ppc/pnv_psi.h
A include/hw/ppc/pnv_xive.h
M include/hw/ppc/pnv_xscom.h
M include/hw/ppc/ppc.h
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_cpu_core.h
M include/hw/ppc/spapr_drc.h
M include/hw/ppc/spapr_irq.h
M include/hw/ppc/spapr_ovec.h
M include/hw/ppc/spapr_vio.h
M include/hw/ppc/spapr_xive.h
M include/hw/ppc/xics_spapr.h
M include/hw/ppc/xive.h
M include/hw/vfio/vfio-common.h
M pc-bios/u-boot.e500
M roms/u-boot
M target/ppc/cpu-qom.h
M target/ppc/cpu.h
M target/ppc/excp_helper.c
M target/ppc/internal.h
M target/ppc/kvm.c
M target/ppc/kvm_ppc.h
M target/ppc/machine.c
M target/ppc/mmu-hash64.c
M target/ppc/translate.c
M target/ppc/translate/vmx-impl.inc.c
M target/ppc/translate/vsx-impl.inc.c
M target/ppc/translate_init.inc.c
M tests/boot-serial-test.c
M tests/pnv-xscom-test.c
M tests/prom-env-test.c
M tests/pxe-test.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.0-20190312' into
staging
ppc patch queue for 2019-03-10
This pull requests supersedes ppc-for-4.0-20190310. Changes are:
* Fixed a bunch of minor style problems
* Suppressed warnings about Spectre/Meltdown mitigations with TCG
* Added one more patch, a preliminary fix towards the not-quite-ready
support for NVLink VFIO passthrough.
This is a final pull request before the 4.0 soft freeze. Changes
include:
* A Great Renaming to use camel case properly in spapr code
* Optimization of some vector instructions
* Support for POWER9 cpus in the powernv machine
* Fixes a regression from the last pull request in handling VSX
instructions with mixed operands from the FPR and VMX parts of the
register array
* Optimization hack to avoid scanning all the (empty) entries on a
new IOMMU window
* Add FSL I2C controller model for E500
* Support for KVM acceleration of the H_PAGE_INIT hypercall on spapr
* Update u-boot image for E500
* Enable Specre/Meltdown mitigations by default on the new machine type
* Enable large decrementer support for POWER9
# gpg: Signature made Tue 12 Mar 2019 08:14:51 GMT
# gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>" [full]
# gpg: aka "David Gibson (Red Hat) <address@hidden>" [full]
# gpg: aka "David Gibson (ozlabs.org) <address@hidden>" [full]
# gpg: aka "David Gibson (kernel.org) <address@hidden>"
[unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-4.0-20190312: (62 commits)
vfio: Make vfio_get_region_info_cap public
Suppress test warnings about missing Spectre/Meltdown mitigations with TCG
spapr: Use CamelCase properly
target/ppc: Optimize x[sv]xsigdp using deposit_i64()
target/ppc: Optimize xviexpdp() using deposit_i64()
target/ppc: add HV support for POWER9
ppc/pnv: add a "ibm,opal/power-mgt" device tree node on POWER9
ppc/pnv: add more dummy XSCOM addresses
ppc/pnv: activate XSCOM tests for POWER9
ppc/pnv: POWER9 XSCOM quad support
ppc/pnv: extend XSCOM core support for POWER9
ppc/pnv: add a OCC model for POWER9
ppc/pnv: add a OCC model class
ppc/pnv: add SerIRQ routing registers
ppc/pnv: add a LPC Controller model for POWER9
ppc/pnv: add a 'dt_isa_nodename' to the chip
ppc/pnv: add a LPC Controller class model
ppc/pnv: lpc: fix OPB address ranges
ppc/pnv: add a PSI bridge model for POWER9
ppc/pnv: add a PSI bridge class model
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/377b155bde45...bc76b7148993
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Peter Maydell <=