[Qemu-commits] [qemu/qemu] 83a717: RISC-V: Split out mstatus_fs from tb_flags

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 83a71719903cbfb683fd916bb555620e8b272140
      
https://github.com/qemu/qemu/commit/83a71719903cbfb683fd916bb555620e8b272140
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-11 (Mon, 11 Feb 2019)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/translate.c

  Log Message:
  -----------
  RISC-V: Split out mstatus_fs from tb_flags

Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 533b8f8877d4e3e8bf2b57e633a84afe27c14429
      
https://github.com/qemu/qemu/commit/533b8f8877d4e3e8bf2b57e633a84afe27c14429
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-11 (Mon, 11 Feb 2019)

  Changed paths:
    M target/riscv/csr.c
    M target/riscv/translate.c

  Log Message:
  -----------
  RISC-V: Mark mstatus.fs dirty

Modifed from Richard Henderson's patch [1] to integrate
with the new control and status register implementation.

[1] https://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg07034.html

Note: the f* CSRs already mark mstatus.FS dirty using
env->mstatus |= mstatus.FS so the bug in the first
spin of this patch has been fixed in a prior commit.

Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>

Co-authored-by: Richard Henderson <address@hidden>
Co-authored-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 7f2b5ff125d518a7fff9f6a4c633e3063fd75ec3
      
https://github.com/qemu/qemu/commit/7f2b5ff125d518a7fff9f6a4c633e3063fd75ec3
  Author: Michael Clark <address@hidden>
  Date:   2019-02-11 (Mon, 11 Feb 2019)

  Changed paths:
    M target/riscv/csr.c
    M target/riscv/op_helper.c

  Log Message:
  -----------
  RISC-V: Implement mstatus.TSR/TW/TVM

This adds the necessary minimum to support S-mode
virtualization for priv ISA >= v1.10

Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Co-authored-by: Matthew Suozzo <address@hidden>
Co-authored-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: fb73883964099011d34c052658e5ad8be049da61
      
https://github.com/qemu/qemu/commit/fb73883964099011d34c052658e5ad8be049da61
  Author: Michael Clark <address@hidden>
  Date:   2019-02-11 (Mon, 11 Feb 2019)

  Changed paths:
    M linux-user/riscv/signal.c
    M target/riscv/cpu.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/fpu_helper.c
    M target/riscv/op_helper.c

  Log Message:
  -----------
  RISC-V: Use riscv prefix consistently on cpu helpers

* Add riscv prefix to raise_exception function
* Add riscv prefix to CSR read/write functions
* Add riscv prefix to signal handler function
* Add riscv prefix to get fflags function
* Remove redundant declaration of riscv_cpu_init
  and rename cpu_riscv_init to riscv_cpu_init
* rename riscv_set_mode to riscv_cpu_set_mode

Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: d75377bf7bffc21f3d2b4779d8121ccab349d335
      
https://github.com/qemu/qemu/commit/d75377bf7bffc21f3d2b4779d8121ccab349d335
  Author: Alistair Francis <address@hidden>
  Date:   2019-02-11 (Mon, 11 Feb 2019)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  RISC-V: Add priv_ver to DisasContext

The gen methods should access state from DisasContext. Add priv_ver
field to the DisasContext struct.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: db9f3fd69d5bccfd25f84d5cec805308406b7b8f
      
https://github.com/qemu/qemu/commit/db9f3fd69d5bccfd25f84d5cec805308406b7b8f
  Author: Michael Clark <address@hidden>
  Date:   2019-02-11 (Mon, 11 Feb 2019)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  RISC-V: Add misa to DisasContext

gen methods should access state from DisasContext. Add misa
field to the DisasContext struct and remove CPURISCVState
argument from all gen methods.

Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: d77c3401e694900a15dd8a658ae524f33fc8bc50
      
https://github.com/qemu/qemu/commit/d77c3401e694900a15dd8a658ae524f33fc8bc50
  Author: Michael Clark <address@hidden>
  Date:   2019-02-11 (Mon, 11 Feb 2019)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  RISC-V: Add misa.MAFD checks to translate

Add misa checks for M, A, F and D extensions and if they are
not present generate illegal instructions. This improves
emulation accurary for harts with a limited set of extensions.

Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: f18637cd611cd42bfe1eb4dafa337051fc4f6061
      
https://github.com/qemu/qemu/commit/f18637cd611cd42bfe1eb4dafa337051fc4f6061
  Author: Michael Clark <address@hidden>
  Date:   2019-02-11 (Mon, 11 Feb 2019)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/csr.c

  Log Message:
  -----------
  RISC-V: Add misa runtime write support

This patch adds support for writing misa. misa is validated based
on rules in the ISA specification. 'E' is mutually exclusive with
all other extensions. 'D' depends on 'F' so 'D' bit is dropped
if 'F' is not present. A conservative approach to consistency is
taken by flushing the translation cache on misa writes. misa_mask
is added to the CPU struct to store the original set of extensions.

Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 7d04ac38959f8115f2a029d81db1c8aac179aa95
      
https://github.com/qemu/qemu/commit/7d04ac38959f8115f2a029d81db1c8aac179aa95
  Author: Palmer Dabbelt <address@hidden>
  Date:   2019-02-11 (Mon, 11 Feb 2019)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer

Michael is no longer employed by SiFive and does not want to continue
maintianing the RISC-V port.

Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: ff9f31d9a0d45da83f34207b7ccace850cfc465b
      
https://github.com/qemu/qemu/commit/ff9f31d9a0d45da83f34207b7ccace850cfc465b
  Author: Xi Wang <address@hidden>
  Date:   2019-02-11 (Mon, 11 Feb 2019)

  Changed paths:
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: fix counter-enable checks in ctr()

Access to a counter in U-mode is permitted only if the corresponding
bit is set in both mcounteren and scounteren.  The current code
ignores mcounteren and checks scounteren only for U-mode access.

Signed-off-by: Xi Wang <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 40e46e516d90c2dfe8e8de3741c1c65f1b526502
      
https://github.com/qemu/qemu/commit/40e46e516d90c2dfe8e8de3741c1c65f1b526502
  Author: Alistair Francis <address@hidden>
  Date:   2019-02-11 (Mon, 11 Feb 2019)

  Changed paths:
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c

  Log Message:
  -----------
  riscv: Ensure the kernel start address is correctly cast

Cast the kernel start address to the target bit length.

This ensures that we calculate the initrd offset to a valid address for
the architecture.

Steps to reproduce the original problem (reported by Alex):
  Build U-Boot for the virt machine for riscv32. Then run it with

    $ qemu-system-riscv32 -M virt -kernel u-boot -nographic -initrd <a file>

  You can find the initrd address with

    U-Boot# fdt addr $fdtcontroladdr
    U-Boot# fdt ls /chosen

  Then take a peek at that address:

    U-Boot# md.b <addr>

  and you will see that there is nothing there without this patch. The
  reason is that the binary was loaded to a negative address.

Signed-off-by: Alistair Francis <address@hidden>
Suggested-by: Alexander Graf <address@hidden>
Reported-by: Alexander Graf <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 4856c2c70c87d7a76c8ea208e7568f5637e78840
      
https://github.com/qemu/qemu/commit/4856c2c70c87d7a76c8ea208e7568f5637e78840
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-14 (Thu, 14 Feb 2019)

  Changed paths:
    M MAINTAINERS
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M linux-user/riscv/signal.c
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/cpu_bits.h
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/fpu_helper.c
    M target/riscv/op_helper.c
    M target/riscv/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-sf1' 
into staging

RISC-V Patches for the 4.0 Soft Freeze, Part 1

This patch set contains a handful of patches I've collected over the
last few weeks.  There's nothing really fundamental, but I thought it
would be good to send these out now as there are some other patch sets
on the mailing list that are getting ready to go.

As far as the actual patches, there's:

* A set that cleans up our FS dirty-mode handling.
* Support for writing MISA.
* The removal of Michael as a maintainer.
* A fix to {m,s}counteren handling.
* A fix to make sure the kernel's start address is computed correctly on
  32-bit targets.

This makes my "RISC-V Patches for 3.2, Part 3" pull request defunct, as
it contains the same patches but based on a newer master.  As usual,
I've tested this using a Fedora boot on the latest Linux.  This patch
set does not include Bastian's decodetree patches because there were
some merge conflicts and while I've cleaned them up I want to get a
round of review first.

# gpg: Signature made Wed 13 Feb 2019 15:37:50 GMT
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Palmer Dabbelt <address@hidden>" [unknown]
# gpg:                 aka "Palmer Dabbelt <address@hidden>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-4.0-sf1:
  riscv: Ensure the kernel start address is correctly cast
  target/riscv: fix counter-enable checks in ctr()
  MAINTAINERS: Remove Michael Clark as a RISC-V Maintainer
  RISC-V: Add misa runtime write support
  RISC-V: Add misa.MAFD checks to translate
  RISC-V: Add misa to DisasContext
  RISC-V: Add priv_ver to DisasContext
  RISC-V: Use riscv prefix consistently on cpu helpers
  RISC-V: Implement mstatus.TSR/TW/TVM
  RISC-V: Mark mstatus.fs dirty
  RISC-V: Split out mstatus_fs from tb_flags

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/190ff538293e...4856c2c70c87