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[Qemu-commits] [qemu/qemu] 583b28: pseries: Update SLOF firmware image


From: Peter Maydell
Subject: [Qemu-commits] [qemu/qemu] 583b28: pseries: Update SLOF firmware image
Date: Mon, 04 Feb 2019 04:41:10 -0800

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 583b28d45bf978832be024276fda8fdfe571c447
      
https://github.com/qemu/qemu/commit/583b28d45bf978832be024276fda8fdfe571c447
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M pc-bios/README
    M pc-bios/slof.bin
    M roms/SLOF

  Log Message:
  -----------
  pseries: Update SLOF firmware image

This includes spapr-vio and usb-storage fixes, phandles fix for NVLink2
pass through support and other compile improvements.

The full list of changes is:
  * vio-vscsi: Support multiple channels / buses
  * board-qemu/slof/vio-vscsi: Scan up to 64 SCSI IDs
  * usb/storage: Implement block write support
  * usb/storage: Invert the logic of the IF-statements
  * fdt: Fix phandles for NVLink/NVLink2
  * fdt: Factor out code to replace a phandle in place
  * pci: use appropriate base class ids
  * Makefile: Set a proper DRIVER_NAME when building from a git tree
  * romfs/tools: Silence more compiler warnings with GCC 8.1
  * romfs/tools: Silence GCC 8.1 compiler warning with FLASHFS_MAGIC
  * romfs/tools: Remove superfluous union around the rom header struct
  * make.rules: Compile SLOF with -fno-asynchronous-unwind-tables

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b296b664abc732532afb732f1d02d22cae9c847a
      
https://github.com/qemu/qemu/commit/b296b664abc732532afb732f1d02d22cae9c847a
  Author: BALATON Zoltan <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/i2c/smbus_eeprom.c
    M include/hw/i2c/smbus.h

  Log Message:
  -----------
  smbus: Add a helper to generate SPD EEPROM data

There are several boards with SPD EEPROMs that are now using
duplicated or slightly different hard coded data. Add a helper to
generate SPD data for a memory module of given type and size that
could be used by these boards (either as is or with further changes if
needed) which should help cleaning this up and avoid further duplication.

Signed-off-by: BALATON Zoltan <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 08fd99179a8c5d34c7065e2ad76c7f8b6afe239e
      
https://github.com/qemu/qemu/commit/08fd99179a8c5d34c7065e2ad76c7f8b6afe239e
  Author: BALATON Zoltan <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/ppc/sam460ex.c

  Log Message:
  -----------
  sam460ex: Clean up SPD EEPROM creation

Get rid of code from MIPS Malta board used to create SPD EEPROM data
(parts of which was not even needed for sam460ex) and use the generic
spd_data_generate() function to simplify this.

Signed-off-by: BALATON Zoltan <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 7d8ccf58d5ee83b140220e34b58ac7d4b5dc6a21
      
https://github.com/qemu/qemu/commit/7d8ccf58d5ee83b140220e34b58ac7d4b5dc6a21
  Author: BALATON Zoltan <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/ppc/ppc440_bamboo.c
    M hw/ppc/ppc4xx_devs.c
    M hw/ppc/sam460ex.c
    M include/hw/ppc/ppc4xx.h

  Log Message:
  -----------
  ppc4xx: Use ram_addr_t in ppc4xx_sdram_adjust()

To avoid overflow if larger values are added later use ram_addr_t for
the sdram_bank_sizes parameter to match ram_size to which it is compared.

Signed-off-by: BALATON Zoltan <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0a57fbee209f9d799f53dbcd77f3062649b61b08
      
https://github.com/qemu/qemu/commit/0a57fbee209f9d799f53dbcd77f3062649b61b08
  Author: BALATON Zoltan <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/ppc/ppc440_uc.c

  Log Message:
  -----------
  ppc4xx: Rename ppc4xx_sdram_t in ppc440_uc.c to ppc440_sdram_t

There's already a struct with the same name in ppc4xx_devs.c. They are
not used outside their files so don't clash but they are also not
identical so rename the ppc440 specific one to distinguish them.

Signed-off-by: BALATON Zoltan <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 70812bf70973f02366421c1549fab4036853aea3
      
https://github.com/qemu/qemu/commit/70812bf70973f02366421c1549fab4036853aea3
  Author: BALATON Zoltan <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/ppc/ppc440_uc.c
    M hw/ppc/ppc4xx_devs.c

  Log Message:
  -----------
  ppc4xx: Pass array index to function instead of pointer into the array

The sdram_set_bcr() function in ppc440_uc.c takes a pointer into an
array then calculates its index from that. It's simpler and easier to
just pass the index which simplifies both the function and its callers.
Do similar cleanup in ppc4xx_devs.c to similar function.

Signed-off-by: BALATON Zoltan <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 6a9938a3797a6008ee54bf4ec9b41973c1efc3b9
      
https://github.com/qemu/qemu/commit/6a9938a3797a6008ee54bf4ec9b41973c1efc3b9
  Author: BALATON Zoltan <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/ppc/ppc440_uc.c
    M hw/ppc/sam460ex.c

  Log Message:
  -----------
  sam460ex: Fix support for memory larger than 1GB

Fix the encoding of larger memory modules in the SoC registers which
allows specifying more than 1GB memory for sam460ex. Well, only 2GB
due to SoC and firmware restrictions which was the only missing value
compared to what the real hardware supports. The SoC should support up
to 4GB but when setting that the firmware hangs during memory test.
This may be an overflow bug in the firmware which I did not try to
debug but this may affect real hardware as well.

Signed-off-by: BALATON Zoltan <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 6bf6f3a1d1e6d288c3abac40001aa30153b07404
      
https://github.com/qemu/qemu/commit/6bf6f3a1d1e6d288c3abac40001aa30153b07404
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/intc/xive.c
    M include/hw/ppc/xive.h

  Log Message:
  -----------
  ppc/xive: fix remaining XiveFabric names

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 52b73c09bfee1b7feae6f6c281bab5bf0f94964e
      
https://github.com/qemu/qemu/commit/52b73c09bfee1b7feae6f6c281bab5bf0f94964e
  Author: Greg Kurz <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M target/ppc/kvm.c

  Log Message:
  -----------
  target/ppc/kvm: Drop useless include directive

It has been there since the enablement of PR KVM for PAPR, ie, commit
f61b4bedaf35 in 2011. Not sure why at that time, but it is definitely
not needed with the current code.

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4f10ed277da91b2cb1b6e8a2de18792ce7881832
      
https://github.com/qemu/qemu/commit/4f10ed277da91b2cb1b6e8a2de18792ce7881832
  Author: BALATON Zoltan <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/ppc/ppc440_uc.c

  Log Message:
  -----------
  ppc440: Avoid reporting error when reading non-existent RAM slot

When reading base register of RAM slot with no RAM we should not try
to calculate register value because that will result printing an error
due to invalid RAM size. Just return 0 without the error in this case.

Signed-off-by: BALATON Zoltan <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4882206430532af27aa2ffd30df2818e4661e981
      
https://github.com/qemu/qemu/commit/4882206430532af27aa2ffd30df2818e4661e981
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/ppc/spapr_vio.c
    M qemu-deprecated.texi

  Log Message:
  -----------
  spapr/vio: remove the "irq" property"

commit efe2add7cb7f ("spapr/vio: deprecate the "irq" property") was
merged in QEMU version 3.0. The "irq" property" can be removed for
QEMU version 4.0.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 1ac24c91bbfada5303a3d7ac1d50a05c489053a1
      
https://github.com/qemu/qemu/commit/1ac24c91bbfada5303a3d7ac1d50a05c489053a1
  Author: Thomas Huth <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  hw/ppc/spapr: Encode the SCSI channel (bus) in the SRP LUNs

In hw/scsi/spapr_vio.c we declare that the controller supports multiple
buses by specifying "max_channel = 7" there. So in the code that fixes
up the device tree nodes, we must encode the channel number (a.k.a. bus
number in the "Logical unit addressing format" table of SAM5) into the
64-bit LUN, too.

Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1663160
Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 21df5e4ffafd067090882c312c5978ee7bb2f46f
      
https://github.com/qemu/qemu/commit/21df5e4ffafd067090882c312c5978ee7bb2f46f
  Author: Greg Kurz <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Forbid setting ic-mode for old machine types

Machine types 3.0 and older only know about the legacy XICS backend.
Make it clear by erroring out if the user tries to set ic-mode on
such machines.

Signed-off-by: Greg Kurz <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: d8e81d6e6093738c23b457b607c44a75a6952dc8
      
https://github.com/qemu/qemu/commit/d8e81d6e6093738c23b457b607c44a75a6952dc8
  Author: David Hildenbrand <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/ppc/spapr_pci.c

  Log Message:
  -----------
  spapr/pci: Fix primary bus number for PCI bridges

While looking at the s390x implementation, looks like spapr has a
similar BUG when building the topology.

The primary bus number corresponds always to the bus number of the
bus the bridge is attached to.

Right now, if we have two bridges attached to the same bus (e.g. root
bus) this is however not the case. The first bridge will have primary
bus 0, the second bridge primary bus 1, which is wrong. Fix the assignment.

While at it, drop setting the PCI_SUBORDINATE_BUS temporarily to 0xff.
Setting it temporarily to that value (as discussed e.g. in [1]), is
only relevant for a running system that probes the buses. The value is
effectively unused for us just doing a DFS.

[1] http://www.science.unitn.it/~fiorella/guidelinux/tlk/node76.html

Signed-off-by: David Hildenbrand <address@hidden>
Reviewed-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 40a5056c4130efc60ab0639e93d6d0c509326e8a
      
https://github.com/qemu/qemu/commit/40a5056c4130efc60ab0639e93d6d0c509326e8a
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/intc/spapr_xive.c
    M hw/intc/xive.c
    M include/hw/ppc/xive.h

  Log Message:
  -----------
  xive: add a get_tctx() method to the XiveRouter

It provides a mean to retrieve the XiveTCTX of a CPU. This will become
necessary with future changes which move the interrupt presenter
object pointers under the PowerPCCPU machine_data.

The PowerNV machine has an extra requirement on TIMA accesses that
this new method addresses. The machine can perform indirect loads and
stores on the TIMA on behalf of another CPU. The PIR being defined in
the controller registers, we need a way to peek in the controller
model to find the PIR value.

The XiveTCTX is moved above the XiveRouter definition to avoid forward
typedef declarations.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 8907fc25cf1824c11276f60354bb08bd24c37d4c
      
https://github.com/qemu/qemu/commit/8907fc25cf1824c11276f60354bb08bd24c37d4c
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/ppc/pnv.c
    M hw/ppc/pnv_core.c
    M include/hw/ppc/pnv_core.h

  Log Message:
  -----------
  ppc/pnv: introduce a CPU machine_data

Include the interrupt presenter under the machine_data as we plan to
remove it from under PowerPCCPU

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a28b9a5a8db6a650dbad5811f33615c361c72151
      
https://github.com/qemu/qemu/commit/a28b9a5a8db6a650dbad5811f33615c361c72151
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/intc/spapr_xive.c
    M hw/intc/xics_spapr.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_cpu_core.c
    M hw/ppc/spapr_irq.c
    M include/hw/ppc/spapr_cpu_core.h

  Log Message:
  -----------
  spapr: move the interrupt presenters under machine_data

Next step is to remove them from under the PowerPCCPU

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9c86cb0d79f8658171a6a3b7903773f33559d51a
      
https://github.com/qemu/qemu/commit/9c86cb0d79f8658171a6a3b7903773f33559d51a
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M target/ppc/internal.h

  Log Message:
  -----------
  target/ppc: implement complete set of Vsr* macros

This prepares us for eliminating the use of direct array access within the VMX
instruction implementations.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 467657b3b70fff20704e9aa8d7ab989e768eeb96
      
https://github.com/qemu/qemu/commit/467657b3b70fff20704e9aa8d7ab989e768eeb96
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M target/ppc/cpu.h

  Log Message:
  -----------
  ppc: remove the interrupt presenters from under PowerPCCPU

These fields have now been replaced by equivalents under the machine
data.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 52144b69e4e164c1fc48d872faf3b28162fb7b30
      
https://github.com/qemu/qemu/commit/52144b69e4e164c1fc48d872faf3b28162fb7b30
  Author: Thomas Huth <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/ppc/Makefile.objs
    M hw/ppc/ppc.c
    M hw/ppc/ppc405_uc.c

  Log Message:
  -----------
  hw/ppc: Move ppc40x_*reset() functions from ppc405_uc.c to ppc.c

Currently, it is not possible to build a QEMU binary without the
ppc405_uc.c file, even if you do not want to have the embedded machines
in the binary. This is bad since it's quite a bit of code and this code
pulls in some more dependencies (e.g. via the usage of serial_mm_init())
which would not be needed otherwise - especially with the upcoming
Kconfig-style configuration system for QEMU.

The only functions from this file which are really always required for
linking are the ppc40x_*reset() functions, so move these functions to
ppc.c, close to the ppc40x_set_irq() function that calls them. Now we
can flag ppc405_uc.c and ppc4xx_devs.c with the CONFIG_PPC4XX config
switch, too.

And while we're at it, replace the printf()s in these ppc40x_*reset()
functions with proper calls to qemu_log_mask().

Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 2313abf0fe017eedd7f7eba2438db859147b2b1f
      
https://github.com/qemu/qemu/commit/2313abf0fe017eedd7f7eba2438db859147b2b1f
  Author: Thomas Huth <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: XIVE is an interrupt controller, not a machine

The "XIVE" section is currently listed in the "PowerPC Machines"
section, which is weird, since this is an interrupt controller
device. Move it to the "Devices" section instead.

Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: ce6fc61736d9796d519a163f9181da738677888f
      
https://github.com/qemu/qemu/commit/ce6fc61736d9796d519a163f9181da738677888f
  Author: Thomas Huth <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Merge the two e500 sections

There is currently a "e500" machine section and a "ppce500" device
section in the maintainers file - with some oddities: The wildcard
in the device section also covers the files from the machine section.
And hw/pci-host/ppce500.c is in the device section, while its header
is in the machine section.
This is really quite confusing, and I don't see a reason why we really
need two sections here, so let's simply merge them.

Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: df269271a92452313459f04fbc388f0be018cf70
      
https://github.com/qemu/qemu/commit/df269271a92452313459f04fbc388f0be018cf70
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: Drop unused parameters from fdt building helper

spapr_load_rtas() handles now RTAS address and size information in the FDT
so drop them from spapr_build_fdt().

While we are here, fix a small typo.

Fixes: 3f5dabceba24 "pseries: Consolidate construction of /rtas device tree 
node"
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 40e3dd069c5f050ebc39c63b51938b15380f8aa1
      
https://github.com/qemu/qemu/commit/40e3dd069c5f050ebc39c63b51938b15380f8aa1
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: add myself as maintainer for Mac Old World and New World machines

I've unofficially been doing most of the work on the Mac machines for a while
now, so update MAINTAINERS to reflect this. David is still happy to be listed
as a reviewer as per our discussion at KVM forum.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Acked-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 200280af0e19bfaeb9431eb0ee1ee2d8bf8d3a0a
      
https://github.com/qemu/qemu/commit/200280af0e19bfaeb9431eb0ee1ee2d8bf8d3a0a
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M pc-bios/qemu_vga.ndrv
    M roms/QemuMacDrivers

  Log Message:
  -----------
  QemuMacDrivers: update qemu_vga.ndrv to 90c488d built from submodule

This update to qemu_vga.ndrv includes the following changes:

- Build guest resolution list from QEMU EDID data if enabled
- Fixes to re-enable 256 color mode

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 6e66d0c6484c7f5b30b7a08d83bd3d369ba58682
      
https://github.com/qemu/qemu/commit/6e66d0c6484c7f5b30b7a08d83bd3d369ba58682
  Author: Thomas Huth <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  hw/ppc/spapr: Add support for "-vga cirrus"

The cirrus VGA card has been enabled in the PPC builds with
commit 29f9cef39eb1ae55e82c ("ppc: Include vga cirrus card into
the compiling process") last year. It also works on the pseries
machine, even SLOF contains support for this card, so we can
also support this for the "-vga" parameter here.

Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: d81c20404e2254e2f56d649c978c7fd6b28c3394
      
https://github.com/qemu/qemu/commit/d81c20404e2254e2f56d649c978c7fd6b28c3394
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M target/ppc/int_helper.c

  Log Message:
  -----------
  target/ppc: rework vmrg{l,h}{b,h,w} instructions to use Vsr* macros

The current implementations make use of the endian-specific macros MRGLO/MRGHI
and also reference HI_IDX and LO_IDX directly to calculate array offsets.

Rework the implementation to use the Vsr* macros so that these per-endian
references can be removed.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 4fbc89edc192931364d183dc4051f54dd1f58cf3
      
https://github.com/qemu/qemu/commit/4fbc89edc192931364d183dc4051f54dd1f58cf3
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M target/ppc/int_helper.c

  Log Message:
  -----------
  target/ppc: rework vmul{e,o}{s,u}{b,h,w} instructions to use Vsr* macros

The current implementations make use of the endian-specific macros HI_IDX and
LO_IDX directly to calculate array offsets.

Rework the implementation to use the Vsr* macros so that these per-endian
references can be removed.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 3c385a93b3fdc5972adbf03fd87a9cf091d0f098
      
https://github.com/qemu/qemu/commit/3c385a93b3fdc5972adbf03fd87a9cf091d0f098
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M target/ppc/int_helper.c

  Log Message:
  -----------
  target/ppc: eliminate use of HI_IDX and LO_IDX macros from int_helper.c

The original purpose of these macros was to correctly reference the high and low
parts of the VSRs regardless of the host endianness.

Replace these direct references to high and low parts with the relevant VsrD
macro instead, and completely remove the now-unused HI_IDX and LO_IDX macros.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 730d2ca3f0a79cf598b1142c94c83876561594d8
      
https://github.com/qemu/qemu/commit/730d2ca3f0a79cf598b1142c94c83876561594d8
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M target/ppc/int_helper.c

  Log Message:
  -----------
  target/ppc: eliminate use of EL_IDX macros from int_helper.c

These macros can be eliminated by instead using the relavant Vsr* macros in
the few locations where they appear.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 634c583526ffcd3db8753d4684c5e0a51e74cbbf
      
https://github.com/qemu/qemu/commit/634c583526ffcd3db8753d4684c5e0a51e74cbbf
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M target/ppc/int_helper.c

  Log Message:
  -----------
  target/ppc: simplify VEXT_SIGNED macro in int_helper.c

As pointed out by Richard: it does not need the mask argument, nor does it need
the recast argument. The masking is implied by the cast argument, and the
recast is implied by the assignment.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 0ef83bf29e95bf4ec7ad22ea66153c331e14a099
      
https://github.com/qemu/qemu/commit/0ef83bf29e95bf4ec7ad22ea66153c331e14a099
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M target/ppc/int_helper.c

  Log Message:
  -----------
  target/ppc: remove ROTRu32 and ROTRu64 macros from int_helper.c

Richard points out that these macros suffer from a -fsanitize=shift bug in that
they improperly handle n == 0 turning it into a shift by 32/64 respectively.
Replace them with QEMU's existing ror32() and ror64() functions instead.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 60594fea298d1e014700cc63a92ee43258c8c504
      
https://github.com/qemu/qemu/commit/60594fea298d1e014700cc63a92ee43258c8c504
  Author: Mark Cave-Ayland <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M target/ppc/int_helper.c

  Log Message:
  -----------
  target/ppc: remove various HOST_WORDS_BIGENDIAN hacks in int_helper.c

Following on from the previous work, there are numerous endian-related hacks
in int_helper.c that can now be replaced with Vsr* macros.

There are also a few places where the VECTOR_FOR_INORDER_I macro can be
replaced with a normal iterator since the processing order is irrelevant.

Signed-off-by: Mark Cave-Ayland <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 382b6f22258f3e68c6a4226790eae96e5527e791
      
https://github.com/qemu/qemu/commit/382b6f22258f3e68c6a4226790eae96e5527e791
  Author: Alexey Kardashevskiy <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/ppc/spapr_pci.c

  Log Message:
  -----------
  spapr_pci: Fix endianness in assigned-addresses property

reg->phys_hi and assigned->phys_hi are big endian but we do an extra
byteswap anyway when copying reg->phys_hi to assigned->phys_hi.
To make things slightly more messy, we also add a relocatable bit (b_n())
although in the right endianness.

This fixes endianness of assigned->phys_hi.

This is unlikely to produce any visible difference though as we should end up
there only in the case of PCI hotplug and even then I am not sure if
(d->io_regions[i].addr == PCI_BAR_UNMAPPED) == true.

Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: eac57b405afabcdf6aea82ef5f4cf44cd45c04cb
      
https://github.com/qemu/qemu/commit/eac57b405afabcdf6aea82ef5f4cf44cd45c04cb
  Author: Thomas Huth <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M hw/ppc/mac_newworld.c
    M hw/ppc/mac_oldworld.c
    M hw/ppc/ppc.c
    M hw/ppc/ppc_booke.c

  Log Message:
  -----------
  hw/ppc: Don't include m48t59.h if it is not necessary

These files don't use anything from m48t59.h, so no need to include
this header here.

Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 2044c3e7116eeac0449dcb4a4130cc8f8b9310da
      
https://github.com/qemu/qemu/commit/2044c3e7116eeac0449dcb4a4130cc8f8b9310da
  Author: Murilo Opsfelder Araujo <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M util/mmap-alloc.c

  Log Message:
  -----------
  mmap-alloc: unfold qemu_ram_mmap()

Unfold parts of qemu_ram_mmap() for the sake of understanding, moving
declarations to the top, and keeping architecture-specifics in the
ifdef-else blocks.  No changes in the function behaviour.

Give ptr and ptr1 meaningful names:
  ptr  -> guardptr : pointer to the PROT_NONE guard region
  ptr1 -> ptr      : pointer to the mapped memory returned to caller

Signed-off-by: Murilo Opsfelder Araujo <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 53adb9d43e1abba187387a51f238e878e934c647
      
https://github.com/qemu/qemu/commit/53adb9d43e1abba187387a51f238e878e934c647
  Author: Murilo Opsfelder Araujo <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M exec.c
    M include/qemu/mmap-alloc.h
    M util/mmap-alloc.c
    M util/oslib-posix.c

  Log Message:
  -----------
  mmap-alloc: fix hugetlbfs misaligned length in ppc64

The commit 7197fb4058bcb68986bae2bb2c04d6370f3e7218 ("util/mmap-alloc:
fix hugetlb support on ppc64") fixed Huge TLB mappings on ppc64.

However, we still need to consider the underlying huge page size
during munmap() because it requires that both address and length be a
multiple of the underlying huge page size for Huge TLB mappings.
Quote from "Huge page (Huge TLB) mappings" paragraph under NOTES
section of the munmap(2) manual:

  "For munmap(), addr and length must both be a multiple of the
  underlying huge page size."

On ppc64, the munmap() in qemu_ram_munmap() does not work for Huge TLB
mappings because the mapped segment can be aligned with the underlying
huge page size, not aligned with the native system page size, as
returned by getpagesize().

This has the side effect of not releasing huge pages back to the pool
after a hugetlbfs file-backed memory device is hot-unplugged.

This patch fixes the situation in qemu_ram_mmap() and
qemu_ram_munmap() by considering the underlying page size on ppc64.

After this patch, memory hot-unplug releases huge pages back to the
pool.

Fixes: 7197fb4058bcb68986bae2bb2c04d6370f3e7218
Signed-off-by: Murilo Opsfelder Araujo <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: a61faa3d02159d24d4fa984733dbc0c905508752
      
https://github.com/qemu/qemu/commit/a61faa3d02159d24d4fa984733dbc0c905508752
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-04 (Mon, 04 Feb 2019)

  Changed paths:
    M MAINTAINERS
    M exec.c
    M hw/i2c/smbus_eeprom.c
    M hw/intc/spapr_xive.c
    M hw/intc/xics_spapr.c
    M hw/intc/xive.c
    M hw/ppc/Makefile.objs
    M hw/ppc/mac_newworld.c
    M hw/ppc/mac_oldworld.c
    M hw/ppc/pnv.c
    M hw/ppc/pnv_core.c
    M hw/ppc/ppc.c
    M hw/ppc/ppc405_uc.c
    M hw/ppc/ppc440_bamboo.c
    M hw/ppc/ppc440_uc.c
    M hw/ppc/ppc4xx_devs.c
    M hw/ppc/ppc_booke.c
    M hw/ppc/sam460ex.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_cpu_core.c
    M hw/ppc/spapr_irq.c
    M hw/ppc/spapr_pci.c
    M hw/ppc/spapr_vio.c
    M include/hw/i2c/smbus.h
    M include/hw/ppc/pnv_core.h
    M include/hw/ppc/ppc4xx.h
    M include/hw/ppc/spapr_cpu_core.h
    M include/hw/ppc/xive.h
    M include/qemu/mmap-alloc.h
    M pc-bios/README
    M pc-bios/qemu_vga.ndrv
    M pc-bios/slof.bin
    M qemu-deprecated.texi
    M roms/QemuMacDrivers
    M roms/SLOF
    M target/ppc/cpu.h
    M target/ppc/int_helper.c
    M target/ppc/internal.h
    M target/ppc/kvm.c
    M util/mmap-alloc.c
    M util/oslib-posix.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.0-20190204' into 
staging

ppc patch queue 2019-02-04

Here's the next batch of ppc target and spapr related changes.
Highlights are:
 * A number of endianness handling cleanups from Mark Cave-Ayland
 * Updated Mac VGA driver
 * Updated SLOF image
 * Some XIVE cleanups and small fixes
 * ppc4xx cleanups and fixes from BALATON Zoltan

There are a few chances not technically in the ppc target code:
 * Several MAINTAINERS updates
 * Fixes for unmapping of hugepages on power hosts

The latter is included because it's primarily of interest for ppc KVM setups.

# gpg: Signature made Mon 04 Feb 2019 07:52:26 GMT
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>" [full]
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>" [full]
# gpg:                 aka "David Gibson (kernel.org) <address@hidden>" 
[unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-4.0-20190204: (37 commits)
  mmap-alloc: fix hugetlbfs misaligned length in ppc64
  mmap-alloc: unfold qemu_ram_mmap()
  hw/ppc: Don't include m48t59.h if it is not necessary
  spapr_pci: Fix endianness in assigned-addresses property
  target/ppc: remove various HOST_WORDS_BIGENDIAN hacks in int_helper.c
  target/ppc: remove ROTRu32 and ROTRu64 macros from int_helper.c
  target/ppc: simplify VEXT_SIGNED macro in int_helper.c
  target/ppc: eliminate use of EL_IDX macros from int_helper.c
  target/ppc: eliminate use of HI_IDX and LO_IDX macros from int_helper.c
  target/ppc: rework vmul{e,o}{s,u}{b,h,w} instructions to use Vsr* macros
  target/ppc: rework vmrg{l,h}{b,h,w} instructions to use Vsr* macros
  hw/ppc/spapr: Add support for "-vga cirrus"
  QemuMacDrivers: update qemu_vga.ndrv to 90c488d built from submodule
  MAINTAINERS: add myself as maintainer for Mac Old World and New World machines
  spapr: Drop unused parameters from fdt building helper
  MAINTAINERS: Merge the two e500 sections
  MAINTAINERS: XIVE is an interrupt controller, not a machine
  hw/ppc: Move ppc40x_*reset() functions from ppc405_uc.c to ppc.c
  ppc: remove the interrupt presenters from under PowerPCCPU
  target/ppc: implement complete set of Vsr* macros
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/b3fc0af1ff5e...a61faa3d0215



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