[Qemu-commits] [qemu/qemu] 287a7f: hw/arm/nrf51_soc: set object owner in memory_regio...

[Peter Maydell]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 287a7f6e39cfc44a39909862365fddfc90778968
      
https://github.com/qemu/qemu/commit/287a7f6e39cfc44a39909862365fddfc90778968
  Author: kumar sourav <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/nrf51_soc.c

  Log Message:
  -----------
  hw/arm/nrf51_soc: set object owner in memory_region_init_ram

set object owner in memory_region_init_ram() instead
of NULL.

Signed-off-by: kumar sourav <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3693f217d38f053fa5a7fcd2841c07926c026218
      
https://github.com/qemu/qemu/commit/3693f217d38f053fa5a7fcd2841c07926c026218
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/armv7m.c
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  armv7m: Don't assume the NVIC's CPU is CPU 0

Currently the ARMv7M NVIC object's realize method assumes that the
CPU the NVIC is attached to is CPU 0, because it thinks there can
only ever be one CPU in the system. To allow a dual-Cortex-M33
setup we need to remove this assumption; instead the armv7m
wrapper object tells the NVIC its CPU, in the same way that it
already tells the CPU what the NVIC is.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: e4c81e3a451f9ce692f2644b395facbbdc3891cb
      
https://github.com/qemu/qemu/commit/e4c81e3a451f9ce692f2644b395facbbdc3891cb
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/armv7m.c

  Log Message:
  -----------
  armv7m: Make cpu object a child of the armv7m container

Rather than just creating the CPUs with object_new, make them child
objects of the armv7m container. This will allow the cluster code to
find the CPUs if an armv7m object is made a child of a cluster object.
object_new_with_props() will do the parenting for us.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 66647809f56cc8c7c8a39032e54106f3cd4283f4
      
https://github.com/qemu/qemu/commit/66647809f56cc8c7c8a39032e54106f3cd4283f4
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/armv7m.c
    M include/hw/arm/armv7m.h

  Log Message:
  -----------
  armv7m: Pass through start-powered-off CPU property

Expose "start-powered-off" as a property of the ARMv7M container,
which we just pass through to the CPU object in the same way that we
do for "init-svtor" and "idau". (We want this for the SSE-200, which
powers up only the first CPU at reset and leaves the second powered
down.)

As with the other CPU properties here, we can't just use alias
properties, because the CPU QOM object is not created until armv7m
realize time.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 93dbd10347871133b3e005d6826defbd41d63371
      
https://github.com/qemu/qemu/commit/93dbd10347871133b3e005d6826defbd41d63371
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/iotkit.c
    M hw/arm/mps2-tz.c
    M include/hw/arm/iotkit.h

  Log Message:
  -----------
  hw/arm/iotkit: Rename IoTKit to ARMSSE

The Arm IoTKit was effectively the forerunner of a series of
subsystems for embedded SoCs, named the SSE-050, SSE-100 and SSE-200:
https://developer.arm.com/products/system-design/subsystems
These are generally quite similar, though later iterations have
extra devices that earlier ones do not.

We want to add a model of the SSE-200, which means refactoring the
IoTKit code into an abstract base class and subclasses (using the
same design that the bcm283x SoC and Aspeed SoC family
implementations do). As a first step, rename the IoTKit struct and
QOM macros to ARMSSE, which is what we're going to name the base
class. We temporarily retain TYPE_IOTKIT to avoid changing the
code that instantiates a TYPE_IOTKIT device here and then changing
it back again when it is re-introduced as a subclass.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 4c3690b591b9b8f62c7ddc7fabf4f60e29b0921d
      
https://github.com/qemu/qemu/commit/4c3690b591b9b8f62c7ddc7fabf4f60e29b0921d
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/iotkit.c
    M include/hw/arm/iotkit.h

  Log Message:
  -----------
  hw/arm/iotkit: Refactor into abstract base class and subclass

The Arm SSE-200 Subsystem for Embedded is a revised and
extended version of the older IoTKit SoC. Prepare for
adding a model of it by refactoring the IoTKit code into
an abstract base class which contains the functionality,
driven by a class data block specific to each subclass.
(This is the same approach used by the existing bcm283x
SoC family implementation.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 13628891b397386a10a8e3288f31d6ee6ab0bfc3
      
https://github.com/qemu/qemu/commit/13628891b397386a10a8e3288f31d6ee6ab0bfc3
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/iotkit.c

  Log Message:
  -----------
  hw/arm/iotkit: Rename 'iotkit' local variables and functions

Rename various internal uses of 'iotkit' in hw/arm/iotkit.c to
'armsse', for consistency. The remaining occurences are:
 * related to the devices TYPE_IOTKIT_SYSCTL, TYPE_IOTKIT_SYSINFO,
   etc, which this refactor is not touching
 * references that apply specifically to the IoTKit (like
   the lack of a private CPU region)
 * the vmstate, which keeps its old "iotkit" name for
   migration compatibility reasons

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 6eee5d241a87615a31d46bb043101eceeaa4a799
      
https://github.com/qemu/qemu/commit/6eee5d241a87615a31d46bb043101eceeaa4a799
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M MAINTAINERS
    M default-configs/arm-softmmu.mak
    M hw/arm/Makefile.objs
    A hw/arm/armsse.c
    R hw/arm/iotkit.c
    M hw/arm/mps2-tz.c
    A include/hw/arm/armsse.h
    R include/hw/arm/iotkit.h

  Log Message:
  -----------
  hw/arm/iotkit: Rename files to hw/arm/armsse.[ch]

Rename the files that used to be iotkit.[ch] to
armsse.[ch] to reflect the fact they new cover
multiple Arm subsystems for embedded.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 0a78d7ebf8524fdcf701e6e228d8a5720a0ffd1e
      
https://github.com/qemu/qemu/commit/0a78d7ebf8524fdcf701e6e228d8a5720a0ffd1e
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/armsse.c
    M hw/misc/iotkit-secctl.c
    M include/hw/misc/iotkit-secctl.h

  Log Message:
  -----------
  hw/misc/iotkit-secctl: Support 4 internal MPCs

The SSE-200 has 4 banks of SRAM, each with its own internal
Memory Protection Controller. The interrupt status for these
extra MPCs appears in the same security controller SECMPCINTSTATUS
register as the MPC for the IoTKit's single SRAM bank. Enhance the
iotkit-secctl device to allow 4 MPCs. (If the particular IoTKit/SSE
variant in use does not have all 4 MPCs then the unused inputs will
simply result in the SECMPCINTSTATUS bits being zero as required.)

The hardcoded constant "1"s in armsse.c indicate the actual number
of SRAM MPCs the IoTKit has, and will be replaced in the following
commit.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: f0cab7fe88e1751209d6f3d8b9bac04b09b2e7ea
      
https://github.com/qemu/qemu/commit/f0cab7fe88e1751209d6f3d8b9bac04b09b2e7ea
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/armsse.c
    M include/hw/arm/armsse.h

  Log Message:
  -----------
  hw/arm/armsse: Make number of SRAM banks parameterised

The SSE-200 has four banks of SRAM, each with its own
Memory Protection Controller, where the IoTKit has only one.
Make the number of SRAM banks a field in ARMSSEInfo.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 4b635cf7a95e5012113570a87e134962a0271a27
      
https://github.com/qemu/qemu/commit/4b635cf7a95e5012113570a87e134962a0271a27
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/armsse.c
    M include/hw/arm/armsse.h

  Log Message:
  -----------
  hw/arm/armsse: Make SRAM bank size configurable

For the IoTKit the SRAM bank size is always 32K (15 bits); for the
SSE-200 this is a configurable parameter, which defaults to 32K but
can be changed when it is built into a particular SoC. For instance
the Musca-B1 board sets it to 128K (17 bits).

Make the bank size a QOM property. We follow the SSE-200 hardware in
naming the parameter SRAM_ADDR_WIDTH, which specifies the number of
address bits of a single SRAM bank.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 91c1e9fcbd7548db3687db946a778b8f34d1343c
      
https://github.com/qemu/qemu/commit/91c1e9fcbd7548db3687db946a778b8f34d1343c
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/armsse.c
    M include/hw/arm/armsse.h

  Log Message:
  -----------
  hw/arm/armsse: Support dual-CPU configuration

The SSE-200 has two Cortex-M33 CPUs. These see the same view
of memory, with the exception of the "private CPU region" which
has per-CPU devices. Internal device interrupts for SSE-200
devices are mostly wired up to both CPUs, with the exception of
a few per-CPU devices. External GPIO inputs on the SSE-200
device are provided for the second CPU's interrupts above 32,
as is already the case for the first CPU.

Refactor the code to support creation of multiple CPUs.
For the moment we leave all CPUs with the same view of
memory: this will not work in the multiple-CPU case, but
we will fix this in the following commit.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: d847ca5128351ea3be3a92be74d7bac74e59f048
      
https://github.com/qemu/qemu/commit/d847ca5128351ea3be3a92be74d7bac74e59f048
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/armsse.c
    M include/hw/arm/armsse.h

  Log Message:
  -----------
  hw/arm/armsse: Give each CPU its own view of memory

Give each CPU its own container memory region. This is necessary
for two reasons:
 * some devices are instantiated one per CPU and the CPU sees only
   its own device
 * since a memory region can only be put into one container, we must
   give each armv7m object a different MemoryRegion as its 'memory'
   property, or a dual-CPU configuration will assert on realize when
   the second armv7m object tries to put the MR into a container when
   it is already in the first armv7m object's container

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 7cd3a2e0d53ea0dc5e2811082a4f64b52c220ded
      
https://github.com/qemu/qemu/commit/7cd3a2e0d53ea0dc5e2811082a4f64b52c220ded
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/armsse.c
    M include/hw/arm/armsse.h

  Log Message:
  -----------
  hw/arm/armsse: Put each CPU in its own cluster object

Create a cluster object to hold each CPU in the SSE. They are
logically distinct and may be configured differently (for instance
one may not have an FPU where the other does).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: dde0c4910395445da6b2b756193f89ab578d31a1
      
https://github.com/qemu/qemu/commit/dde0c4910395445da6b2b756193f89ab578d31a1
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/armsse.c
    M hw/misc/iotkit-sysinfo.c
    M include/hw/misc/iotkit-sysinfo.h

  Log Message:
  -----------
  iotkit-sysinfo: Make SYS_VERSION and SYS_CONFIG configurable

The SYS_VERSION and SYS_CONFIG register values differ between the
IoTKit and SSE-200. Make them configurable via QOM properties rather
than hard-coded, and set them appropriately in the ARMSSE code that
instantiates the IOTKIT_SYSINFO device.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: f8574705f62b38a610d398573828b57da24b1adb
      
https://github.com/qemu/qemu/commit/f8574705f62b38a610d398573828b57da24b1adb
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/armsse.c
    M include/hw/arm/armsse.h

  Log Message:
  -----------
  hw/arm/armsse: Add unimplemented-device stubs for MHUs

The SSE-200 has two Message Handling Units (MHUs), which sit behind
the APB PPC0. Wire up some unimplemented-device stubs for these,
since we don't yet implement a real model of this device.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: e0b00f1b92d700171cfe39fac39de9fa75c1aecd
      
https://github.com/qemu/qemu/commit/e0b00f1b92d700171cfe39fac39de9fa75c1aecd
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/armsse.c
    M include/hw/arm/armsse.h

  Log Message:
  -----------
  hw/arm/armsse: Add unimplemented-device stubs for PPUs

Add unimplemented-device stubs for the various Power Policy Unit
devices that the SSE-200 has.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 2357bca5328e9f6b1e0f14a3ac62a7f8b1aef557
      
https://github.com/qemu/qemu/commit/2357bca5328e9f6b1e0f14a3ac62a7f8b1aef557
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/armsse.c
    M include/hw/arm/armsse.h

  Log Message:
  -----------
  hw/arm/armsse: Add unimplemented-device stub for cache control registers

The SSE-200 gives each CPU a register bank to use to control its
L1 instruction cache. Put in an unimplemented-device stub for this.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: c1f572579eefe18e56c7135e2a7c0698f0488b92
      
https://github.com/qemu/qemu/commit/c1f572579eefe18e56c7135e2a7c0698f0488b92
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/armsse.c
    M include/hw/arm/armsse.h

  Log Message:
  -----------
  hw/arm/armsse: Add unimplemented-device stub for CPU local control registers

The SSE-200 has a "CPU local security control" register bank; add an
unimplemented-device stub for it. (The register bank has only one
interesting register, which allows the guest to lock down changes
to various CPU registers so they cannot be modified further. We
don't support that in our Cortex-M33 model anyway.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 5aeb36896600ff92aee1083ed17e80f069befb93
      
https://github.com/qemu/qemu/commit/5aeb36896600ff92aee1083ed17e80f069befb93
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M MAINTAINERS
    M default-configs/arm-softmmu.mak
    M hw/misc/Makefile.objs
    A hw/misc/armsse-cpuid.c
    M hw/misc/trace-events
    A include/hw/misc/armsse-cpuid.h

  Log Message:
  -----------
  hw/misc/armsse-cpuid: Implement SSE-200 CPU_IDENTITY register block

The SSE-200 has a CPU_IDENTITY register block, which is a set of
read-only registers. As well as the usual PID/CID registers, there
is a single CPUID register which indicates whether the CPU is CPU 0
or CPU 1. Implement a model of this register block.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: ade67dcd4ac1786637d25bb04a13c836357f44fc
      
https://github.com/qemu/qemu/commit/ade67dcd4ac1786637d25bb04a13c836357f44fc
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/armsse.c
    M include/hw/arm/armsse.h

  Log Message:
  -----------
  hw/arm/armsse: Add CPU_IDENTITY block to SSE-200

Instantiate a copy of the CPU_IDENTITY register block for each CPU
in an SSE-200.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 0829d24e6646e23507917859eea96f163eb62637
      
https://github.com/qemu/qemu/commit/0829d24e6646e23507917859eea96f163eb62637
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/armsse.c
    M include/hw/arm/armsse.h

  Log Message:
  -----------
  hw/arm/armsse: Add SSE-200 model

Add a model of the SSE-200, now we have put in all
the code that lets us make it different from the IoTKit.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 4a30dc1c236888ffab1f5e30a5c76b35df917ab9
      
https://github.com/qemu/qemu/commit/4a30dc1c236888ffab1f5e30a5c76b35df917ab9
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Add IRQ infrastructure to support SSE-200

In preparation for adding support for the AN521 MPS2 image, we need
to handle wiring up the MPS2 device interrupt lines to both CPUs in
the SSE-200, rather than just the one that the IoTKit has.

Abstract out a "connect to the IoTKit interrupt line" function
and make it connect to a splitter which feeds both sets of inputs
for the SSE-200 case.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 23f9242332baee5020daaa5c4f4ddc72e12bc9f0
      
https://github.com/qemu/qemu/commit/23f9242332baee5020daaa5c4f4ddc72e12bc9f0
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Add mps2-an521 model

Add a model of the MPS2 FPGA image described in Application Note
AN521. This is identical to the AN505 image, except that it uses
the SSE-200 rather than the IoTKit and so has two Cortex-M33 CPUs.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 08d5e3bde6b4ad32996bf69d93aa66ae43d3f3ff
      
https://github.com/qemu/qemu/commit/08d5e3bde6b4ad32996bf69d93aa66ae43d3f3ff
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm/translate-a64: Don't underdecode system instructions

The "system instructions" and "system register move" subcategories
of "branches, exception generating and system instructions" for A64
only apply if bits [23:22] are zero; other values are currently
unallocated. Correctly UNDEF these unallocated encodings.

Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden


  Commit: a80c4256543987ca88407349ee012a673a10a2ae
      
https://github.com/qemu/qemu/commit/a80c4256543987ca88407349ee012a673a10a2ae
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm/translate-a64: Don't underdecode PRFM

The PRFM prefetch insn in the load/store with imm9 encodings
requires idx field 0b00; we were underdecoding this by
only checking !is_unpriv (which is equivalent to idx != 2).
Correctly UNDEF the unallocated encodings where idx == 0b01
and 0b11 as well as 0b10.

Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden


  Commit: e1f220811dbd5d85fb02ff286358f9ee6188938f
      
https://github.com/qemu/qemu/commit/e1f220811dbd5d85fb02ff286358f9ee6188938f
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm/translate-a64: Don't underdecode SIMD ld/st multiple

In the AdvSIMD load/store multiple structures encodings,
the non-post-indexed case should have zeroes in [20:16]
(which is the Rm field for the post-indexed case).
Correctly UNDEF the currently unallocated encodings which
have non-zeroes in those bits.

Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden


  Commit: 9c72b68ad746a51f63822cffab4d144b5957823a
      
https://github.com/qemu/qemu/commit/9c72b68ad746a51f63822cffab4d144b5957823a
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm/translate-a64: Don't underdecode SIMD ld/st single

In the AdvSIMD load/store single structure encodings, the
non-post-indexed case should have zeroes in [20:16] (which is the
Rm field for the post-indexed case). Bit 31 must also be zero
(a check we got right in ldst_multiple but not here). Correctly
UNDEF these unallocated encodings.

Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden


  Commit: 4f61106614410945b1d1c93081544ad5b13044fc
      
https://github.com/qemu/qemu/commit/4f61106614410945b1d1c93081544ad5b13044fc
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm/translate-a64: Don't underdecode add/sub extended register

In the "add/subtract (extended register)" encoding group, the "opt"
field in bits [23:22] must be zero. Correctly UNDEF the unallocated
encodings where this field is not zero.

Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden


  Commit: c1e20801f5ee53472dbf2757df605543f3f4ce0b
      
https://github.com/qemu/qemu/commit/c1e20801f5ee53472dbf2757df605543f3f4ce0b
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm/translate-a64: Don't underdecode FP insns

In the encoding groups
 * floating-point data-processing (1 source)
 * floating-point data-processing (2 source)
 * floating-point data-processing (3 source)
 * floating-point immediate
 * floating-point compare
 * floating-ponit conditional compare
 * floating-point conditional select

bit 31 is M and bit 29 is S (and bit 30 is 0, already checked at
this point in the decode). None of these groups allocate any
encoding for M=1 or S=1. We checked this in disas_fp_compare(),
disas_fp_ccomp() and disas_fp_csel(), but missed it in disas_fp_1src(),
disas_fp_2src(), disas_fp_3src() and disas_fp_imm().

We also missed that in the fp immediate encoding the imm5 field
must be all zeroes.

Correctly UNDEF the unallocated encodings here.

Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden


  Commit: 4977986ca38fb1d5357532e1a8032b984047a369
      
https://github.com/qemu/qemu/commit/4977986ca38fb1d5357532e1a8032b984047a369
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm/translate-a64: Don't underdecode SDOT and UDOT

In the AdvSIMD scalar x indexed element and vector x indexed element
encoding group, the SDOT and UDOT instructions are vector only,
and their opcode is unallocated in the scalar group. Correctly
UNDEF this unallocated encoding.

Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden


  Commit: 5601be3b01d73e21c09331599e2ce62df016ff94
      
https://github.com/qemu/qemu/commit/5601be3b01d73e21c09331599e2ce62df016ff94
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M exec.c

  Log Message:
  -----------
  exec.c: Don't reallocate IOMMUNotifiers that are in use

The tcg_register_iommu_notifier() code has a GArray of
TCGIOMMUNotifier structs which it has registered by passing
memory_region_register_iommu_notifier() a pointer to the embedded
IOMMUNotifier field. Unfortunately, if we need to enlarge the
array via g_array_set_size() this can cause a realloc(), which
invalidates the pointer that memory_region_register_iommu_notifier()
put into the MemoryRegion's iommu_notify list. This can result
in segfaults.

Switch the GArray to holding pointers to the TCGIOMMUNotifier
structs, so that we can individually allocate and free them.

Cc: address@hidden
Fixes: 1f871c5e6b0f30644a60a ("exec.c: Handle IOMMUs in 
address_space_translate_for_iotlb()")
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 4dfabb6d568e6b315594d7d464dacaf3368aff60
      
https://github.com/qemu/qemu/commit/4dfabb6d568e6b315594d7d464dacaf3368aff60
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm/translate-a64: Fix FCMLA decoding error

The FCMLA (by element) instruction exists in the
"vector x indexed element" encoding group, but not in
the "scalar x indexed element" group. Correctly UNDEF
the unallocated encodings.

Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden


  Commit: eaefb97a8b97dbf42c016fe65b68b92f99a346f6
      
https://github.com/qemu/qemu/commit/eaefb97a8b97dbf42c016fe65b68b92f99a346f6
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm/translate-a64: Fix mishandling of size in FCMLA decode

In disas_simd_indexed(), for the case of "complex fp", each indexable
element is a complex pair, so the total size is twice that indicated
in the 'size' field in the encoding. We were trying to do this
"double the size" operation with a left shift by 1, but this is
incorrect because the 'size' field is a MO_8/MO_16/MO_32/MO_64
value, and doubling the size should be done by a simple increment.

This meant we were mishandling FCMLA (by element) of values where
the real and imaginary parts are 32-bit floats, and would incorrectly
UNDEF this encoding. (No other insns take this code path, and for
16-bit floats it happens that 1 << 1 and 1 + 1 are both the same).

Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden


  Commit: f4efb4b2a17528837cb445f9bdfaef8df4a5acf7
      
https://github.com/qemu/qemu/commit/f4efb4b2a17528837cb445f9bdfaef8df4a5acf7
  Author: Aaron Lindsay OS <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Send interrupts on PMU counter overflow

Whenever we notice that a counter overflow has occurred, send an
interrupt. This is made more reliable with the addition of a timer in a
follow-on commit.

Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4e7beb0cc0f3fb05f1c055113debaa0c7d34fc89
      
https://github.com/qemu/qemu/commit/4e7beb0cc0f3fb05f1c055113debaa0c7d34fc89
  Author: Aaron Lindsay OS <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add a timer to predict PMU counter overflow

Make PMU overflow interrupts more accurate by using a timer to predict
when they will overflow rather than waiting for an event to occur which
allows us to otherwise check them.

Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ef682cdb4aded5c65a018e175482e875de66059d
      
https://github.com/qemu/qemu/commit/ef682cdb4aded5c65a018e175482e875de66059d
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Enable API, APK bits in SCR, HCR

These bits become writable with the ARMv8.3-PAuth extension.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 42f6ed919325413392bea247a1e6f135deb469cd
      
https://github.com/qemu/qemu/commit/42f6ed919325413392bea247a1e6f135deb469cd
  Author: Julia Suvorova <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/boot.c
    M include/qom/cpu.h
    M target/arm/arm-powerctl.c
    M target/arm/cpu.c
    M target/arm/cpu64.c

  Log Message:
  -----------
  arm: Clarify the logic of set_pc()

Until now, the set_pc logic was unclear, which raised questions about
whether it should be used directly, applying a value to PC or adding
additional checks, for example, set the Thumb bit in Arm cpu. Let's set
the set_pc logic for “Configure the PC, as was done in the ELF file”
and implement synchronize_with_tb hook for preserving PC to cpu_tb_exec.

Signed-off-by: Julia Suvorova <address@hidden>
Acked-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 276c6e813719568bdc9743e87ff8f42115006206
      
https://github.com/qemu/qemu/commit/276c6e813719568bdc9743e87ff8f42115006206
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Always enable pac keys for user-only

Drop the pac properties.  This approach cannot work as written
because the properties are applied before arm_cpu_reset, which
zeros SCTLR_EL1 (amongst everything else).

We can re-introduce the properties if they turn out to be useful.
But since linux 5.0 enables all of the keys, they may not be.

Fixes: 1ae9cfbd470
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0083a1fad683053720b5c19e3e192b6deafa7a82
      
https://github.com/qemu/qemu/commit/0083a1fad683053720b5c19e3e192b6deafa7a82
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M linux-user/elfload.c

  Log Message:
  -----------
  aarch64-linux-user: Update HWCAP bits from linux 5.0-rc1

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 29d26ab2b0722138b52050a61970b952b74243f2
      
https://github.com/qemu/qemu/commit/29d26ab2b0722138b52050a61970b952b74243f2
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M linux-user/elfload.c

  Log Message:
  -----------
  aarch64-linux-user: Enable HWCAP bits for PAuth

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 87877543b14feebf1bc4fd336d41901b036acf98
      
https://github.com/qemu/qemu/commit/87877543b14feebf1bc4fd336d41901b036acf98
  Author: Richard Henderson <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M linux-user/aarch64/cpu_loop.c
    M linux-user/aarch64/target_syscall.h

  Log Message:
  -----------
  linux-user: Initialize aarch64 pac keys

Initialize the keys to a non-zero value on process start.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f6768aa1b4c6a80448eabd22bb9b4123c709caea
      
https://github.com/qemu/qemu/commit/f6768aa1b4c6a80448eabd22bb9b4123c709caea
  Author: Remi Denis-Courmont <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: fix AArch64 virtual address space size

Since QEMU does not support the ARMv8.2-LVA, Large Virtual Address,
extension (yet), the VA address space is 48-bits plus a sign bit. User
mode can only handle the positive half of the address space, so that
makes a limit of 48 bits.

(With LVA, it would be 53 and 52 bits respectively.)

The incorrectly large address space conflicts with PAuth instructions,
which use bits 48-54 and 56-63 for the pointer authentication code. This
also conflicts with (as yet unsupported by QEMU) data tagging and with
the ARMv8.5-MTE extension.

Signed-off-by: Remi Denis-Courmont <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1cf86a8618644beb860951ff4383457ee88a7f4a
      
https://github.com/qemu/qemu/commit/1cf86a8618644beb860951ff4383457ee88a7f4a
  Author: Remi Denis-Courmont <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: fix decoding of B{,L}RA{A,B}

A flawed test lead to the instructions always being treated as
unallocated encodings.

Fixes: https://bugs.launchpad.net/bugs/1813460
Signed-off-by: Remi Denis-Courmont <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c0d4eb83526e2ba5a8def0710d183a9387090ab6
      
https://github.com/qemu/qemu/commit/c0d4eb83526e2ba5a8def0710d183a9387090ab6
  Author: Steffen Görtz <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/nvram/Makefile.objs
    A hw/nvram/nrf51_nvm.c
    A include/hw/nvram/nrf51_nvm.h

  Log Message:
  -----------
  hw/nvram/nrf51_nvm: Add nRF51 non-volatile memories

The nRF51 contains three regions of non-volatile memory (NVM):
- CODE (R/W): contains code
- FICR (R): Factory information like code size, chip id etc.
- UICR (R/W): Changeable configuration data. Lock bits, Code
  protection configuration, Bootloader address, Nordic SoftRadio
  configuration, Firmware configuration.

Read and write access to the memories is managed by the
Non-volatile memory controller.

Memory schema:
 [ CPU ] -+- [ NVM, either FICR, UICR or CODE ]
          |      |
          \- [ NVMC ]

Signed-off-by: Steffen Görtz <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Tested-by: Joel Stanley <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4d744b25d37804279f94800b62f3d765177d6493
      
https://github.com/qemu/qemu/commit/4d744b25d37804279f94800b62f3d765177d6493
  Author: Steffen Görtz <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M hw/arm/nrf51_soc.c
    M include/hw/arm/nrf51_soc.h

  Log Message:
  -----------
  arm: Instantiate NRF51 special NVM's and NVMC

Instantiates UICR, FICR, FLASH and NVMC in nRF51 SOC.

Signed-off-by: Steffen Görtz <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7743b70ffe7a8ce168adce2cf50ad156b1fefb8c
      
https://github.com/qemu/qemu/commit/7743b70ffe7a8ce168adce2cf50ad156b1fefb8c
  Author: Steffen Görtz <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M tests/microbit-test.c

  Log Message:
  -----------
  tests/microbit-test: Add tests for nRF51 NVMC

Signed-off-by: Steffen Görtz <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Acked-by: Thomas Huth <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e83d74286cad2b9b967e1ba0ce5c8d16cba9679f
      
https://github.com/qemu/qemu/commit/e83d74286cad2b9b967e1ba0ce5c8d16cba9679f
  Author: Peter Maydell <address@hidden>
  Date:   2019-02-01 (Fri, 01 Feb 2019)

  Changed paths:
    M MAINTAINERS
    M default-configs/arm-softmmu.mak
    M exec.c
    M hw/arm/Makefile.objs
    A hw/arm/armsse.c
    M hw/arm/armv7m.c
    M hw/arm/boot.c
    R hw/arm/iotkit.c
    M hw/arm/mps2-tz.c
    M hw/arm/nrf51_soc.c
    M hw/intc/armv7m_nvic.c
    M hw/misc/Makefile.objs
    A hw/misc/armsse-cpuid.c
    M hw/misc/iotkit-secctl.c
    M hw/misc/iotkit-sysinfo.c
    M hw/misc/trace-events
    M hw/nvram/Makefile.objs
    A hw/nvram/nrf51_nvm.c
    A include/hw/arm/armsse.h
    M include/hw/arm/armv7m.h
    R include/hw/arm/iotkit.h
    M include/hw/arm/nrf51_soc.h
    A include/hw/misc/armsse-cpuid.h
    M include/hw/misc/iotkit-secctl.h
    M include/hw/misc/iotkit-sysinfo.h
    A include/hw/nvram/nrf51_nvm.h
    M include/qom/cpu.h
    M linux-user/aarch64/cpu_loop.c
    M linux-user/aarch64/target_syscall.h
    M linux-user/elfload.c
    M target/arm/arm-powerctl.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c
    M target/arm/translate-a64.c
    M tests/microbit-test.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190201' 
into staging

target-arm queue:
 * New machine mps2-an521 -- this is a model of the AN521 FPGA image for the 
MPS2 devboard
 * Fix various places where we failed to UNDEF invalid A64 instructions
 * Don't UNDEF a valid FCMLA on 32-bit inputs
 * Fix some bugs in the newly-added PAuth implementation
 * microbit: Implement NVMC non-volatile memory controller

# gpg: Signature made Fri 01 Feb 2019 16:06:03 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "address@hidden"
# gpg: Good signature from "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# gpg:                 aka "Peter Maydell <address@hidden>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190201: (47 commits)
  tests/microbit-test: Add tests for nRF51 NVMC
  arm: Instantiate NRF51 special NVM's and NVMC
  hw/nvram/nrf51_nvm: Add nRF51 non-volatile memories
  target/arm: fix decoding of B{,L}RA{A,B}
  target/arm: fix AArch64 virtual address space size
  linux-user: Initialize aarch64 pac keys
  aarch64-linux-user: Enable HWCAP bits for PAuth
  aarch64-linux-user: Update HWCAP bits from linux 5.0-rc1
  target/arm: Always enable pac keys for user-only
  arm: Clarify the logic of set_pc()
  target/arm: Enable API, APK bits in SCR, HCR
  target/arm: Add a timer to predict PMU counter overflow
  target/arm: Send interrupts on PMU counter overflow
  target/arm/translate-a64: Fix mishandling of size in FCMLA decode
  target/arm/translate-a64: Fix FCMLA decoding error
  exec.c: Don't reallocate IOMMUNotifiers that are in use
  target/arm/translate-a64: Don't underdecode SDOT and UDOT
  target/arm/translate-a64: Don't underdecode FP insns
  target/arm/translate-a64: Don't underdecode add/sub extended register
  target/arm/translate-a64: Don't underdecode SIMD ld/st single
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/a1bc3e7dc8f8...e83d74286cad