[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 9a9eda: tcg: Add logical simplifications duri
From: |
GitHub |
Subject: |
[Qemu-commits] [qemu/qemu] 9a9eda: tcg: Add logical simplifications during gvec expan... |
Date: |
Mon, 28 Jan 2019 10:44:11 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 9a9eda78e4e56051485efb65e01748084f99ac3c
https://github.com/qemu/qemu/commit/9a9eda78e4e56051485efb65e01748084f99ac3c
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M tcg/tcg-op-gvec.c
Log Message:
-----------
tcg: Add logical simplifications during gvec expand
We handle many of these during integer expansion, and the
rest of them during integer optimization.
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: f550805d8309500d642f640af8d9928958465478
https://github.com/qemu/qemu/commit/f550805d8309500d642f640af8d9928958465478
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M accel/tcg/tcg-runtime-gvec.c
M accel/tcg/tcg-runtime.h
M tcg/tcg-op-gvec.c
M tcg/tcg-op-gvec.h
M tcg/tcg-op-vec.c
M tcg/tcg-op.h
Log Message:
-----------
tcg: Add gvec expanders for nand, nor, eqv
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 5d6acdd4a485f15b1081acc523b99c1f1a7c42ab
https://github.com/qemu/qemu/commit/5d6acdd4a485f15b1081acc523b99c1f1a7c42ab
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M tcg/tcg-op-gvec.c
M tcg/tcg-op-gvec.h
Log Message:
-----------
tcg: Add write_aofs to GVecGen4
This allows writing 2 output, 3 input operations.
Signed-off-by: Richard Henderson <address@hidden>
Commit: 8afaf0506606f8003ef696df849c5a98637a7a83
https://github.com/qemu/qemu/commit/8afaf0506606f8003ef696df849c5a98637a7a83
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M tcg/README
M tcg/aarch64/tcg-target.h
M tcg/i386/tcg-target.h
M tcg/tcg-op-gvec.c
M tcg/tcg-op-vec.c
M tcg/tcg-op.h
M tcg/tcg-opc.h
M tcg/tcg.c
M tcg/tcg.h
Log Message:
-----------
tcg: Add opcodes for vector saturated arithmetic
Signed-off-by: Richard Henderson <address@hidden>
Commit: dd0a0fcdd8848c2a18970c44a62bd8f394c2b495
https://github.com/qemu/qemu/commit/dd0a0fcdd8848c2a18970c44a62bd8f394c2b495
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M accel/tcg/tcg-runtime-gvec.c
M accel/tcg/tcg-runtime.h
M tcg/README
M tcg/aarch64/tcg-target.h
M tcg/i386/tcg-target.h
M tcg/tcg-op-gvec.c
M tcg/tcg-op-gvec.h
M tcg/tcg-op-vec.c
M tcg/tcg-op.h
M tcg/tcg-opc.h
M tcg/tcg.c
M tcg/tcg.h
Log Message:
-----------
tcg: Add opcodes for vector minmax arithmetic
Signed-off-by: Richard Henderson <address@hidden>
Commit: 44f1441dbe14e7174a707d7e7ecbc2c8e080bfda
https://github.com/qemu/qemu/commit/44f1441dbe14e7174a707d7e7ecbc2c8e080bfda
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M tcg/i386/tcg-target.inc.c
Log Message:
-----------
tcg/i386: Split subroutines out of tcg_expand_vec_op
This routine was becoming too large.
Signed-off-by: Richard Henderson <address@hidden>
Commit: 8ffafbcec275e61f6a1a17ac1d0bd918d5b23db3
https://github.com/qemu/qemu/commit/8ffafbcec275e61f6a1a17ac1d0bd918d5b23db3
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M tcg/i386/tcg-target.h
M tcg/i386/tcg-target.inc.c
Log Message:
-----------
tcg/i386: Implement vector saturating arithmetic
Only MO_8 and MO_16 are implemented, since that's all the
instruction set provides.
Signed-off-by: Richard Henderson <address@hidden>
Commit: bc37faf4cb2baa77c44298c01558970b88d32808
https://github.com/qemu/qemu/commit/bc37faf4cb2baa77c44298c01558970b88d32808
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M tcg/i386/tcg-target.h
M tcg/i386/tcg-target.inc.c
Log Message:
-----------
tcg/i386: Implement vector minmax arithmetic
The avx instruction set does not directly provide MO_64.
We can still implement 64-bit with comparison and vpblendvb.
Signed-off-by: Richard Henderson <address@hidden>
Commit: d32648d445c534cea7e2ad7ed8608208aa8831c1
https://github.com/qemu/qemu/commit/d32648d445c534cea7e2ad7ed8608208aa8831c1
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M tcg/aarch64/tcg-target.h
M tcg/aarch64/tcg-target.inc.c
Log Message:
-----------
tcg/aarch64: Implement vector saturating arithmetic
Signed-off-by: Richard Henderson <address@hidden>
Commit: 93f332a50371936ea02392bdb748c8140ef3f06a
https://github.com/qemu/qemu/commit/93f332a50371936ea02392bdb748c8140ef3f06a
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M tcg/aarch64/tcg-target.h
M tcg/aarch64/tcg-target.inc.c
Log Message:
-----------
tcg/aarch64: Implement vector minmax arithmetic
Signed-off-by: Richard Henderson <address@hidden>
Commit: 3cea94bbc97180dd2de78993982645b11405b3b2
https://github.com/qemu/qemu/commit/3cea94bbc97180dd2de78993982645b11405b3b2
Author: Emilio G. Cota <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M accel/tcg/cputlb.c
Log Message:
-----------
cputlb: do not evict empty entries to the vtlb
Currently we evict an entry to the victim TLB when it doesn't match
the current address. But it could be that there's no match because
the current entry is empty (i.e. all -1's, for instance via tlb_flush).
Do not evict the entry to the vtlb in that case.
This change will help us keep track of the TLB's use rate, which
we'll use to implement a policy for dynamic TLB sizing.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 86e1eff8bc31a88a089d05b16277eafd7a3cf95b
https://github.com/qemu/qemu/commit/86e1eff8bc31a88a089d05b16277eafd7a3cf95b
Author: Emilio G. Cota <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M accel/tcg/cputlb.c
M include/exec/cpu-defs.h
M include/exec/cpu_ldst.h
M tcg/aarch64/tcg-target.h
M tcg/arm/tcg-target.h
M tcg/i386/tcg-target.h
M tcg/mips/tcg-target.h
M tcg/ppc/tcg-target.h
M tcg/riscv/tcg-target.h
M tcg/s390/tcg-target.h
M tcg/sparc/tcg-target.h
M tcg/tci/tcg-target.h
Log Message:
-----------
tcg: introduce dynamic TLB sizing
Disabled in all TCG backends for now.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 54eaf40b8f8bf523c03208f0ebab18ee7ea8c184
https://github.com/qemu/qemu/commit/54eaf40b8f8bf523c03208f0ebab18ee7ea8c184
Author: Emilio G. Cota <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M tcg/i386/tcg-target.h
M tcg/i386/tcg-target.inc.c
Log Message:
-----------
tcg/i386: enable dynamic TLB sizing
As the following experiments show, this series is a net perf gain,
particularly for memory-heavy workloads. Experiments are run on an
Intel(R) Xeon(R) Gold 6142 CPU @ 2.60GHz.
1. System boot + shudown, debian aarch64:
- Before (v3.1.0):
Performance counter stats for './die.sh v3.1.0' (10 runs):
9019.797015 task-clock (msec) # 0.993 CPUs utilized
( +- 0.23% )
29,910,312,379 cycles # 3.316 GHz
( +- 0.14% )
54,699,252,014 instructions # 1.83 insn per cycle
( +- 0.08% )
10,061,951,686 branches # 1115.541 M/sec
( +- 0.08% )
172,966,530 branch-misses # 1.72% of all branches
( +- 0.07% )
9.084039051 seconds time elapsed (
+- 0.23% )
- After:
Performance counter stats for './die.sh tlb-dyn-v5' (10 runs):
8624.084842 task-clock (msec) # 0.993 CPUs utilized
( +- 0.23% )
28,556,123,404 cycles # 3.311 GHz
( +- 0.13% )
51,755,089,512 instructions # 1.81 insn per cycle
( +- 0.05% )
9,526,513,946 branches # 1104.641 M/sec
( +- 0.05% )
166,578,509 branch-misses # 1.75% of all branches
( +- 0.19% )
8.680540350 seconds time elapsed (
+- 0.24% )
That is, a 4.4% perf increase.
2. System boot + shutdown, ubuntu 18.04 x86_64:
- Before (v3.1.0):
56100.574751 task-clock (msec) # 1.016 CPUs utilized
( +- 4.81% )
200,745,466,128 cycles # 3.578 GHz
( +- 5.24% )
431,949,100,608 instructions # 2.15 insn per cycle
( +- 5.65% )
77,502,383,330 branches # 1381.490 M/sec
( +- 6.18% )
844,681,191 branch-misses # 1.09% of all branches
( +- 3.82% )
55.221556378 seconds time elapsed
( +- 5.01% )
- After:
56603.419540 task-clock (msec) # 1.019 CPUs utilized
( +- 10.19% )
202,217,930,479 cycles # 3.573 GHz
( +- 10.69% )
439,336,291,626 instructions # 2.17 insn per cycle
( +- 14.14% )
80,538,357,447 branches # 1422.853 M/sec
( +- 16.09% )
776,321,622 branch-misses # 0.96% of all branches
( +- 3.77% )
55.549661409 seconds time elapsed
( +- 10.44% )
No improvement (within noise range). Note that for this workload,
increasing the time window too much can lead to perf degradation,
since it flushes the TLB *very* frequently.
3. x86_64 SPEC06int:
x86_64-softmmu speedup vs. v3.1.0 for SPEC06int (test set)
Host: Intel(R) Xeon(R) Gold 6142 CPU @ 2.60GHz (Skylake)
5.5 +------------------------------------------------------------------------+
| +-+ |
5 |-+.................+-+...............................tlb-dyn-v5.......+-|
| * * |
4.5 |-+.................*.*................................................+-|
| * * |
4 |-+.................*.*................................................+-|
| * * |
3.5 |-+.................*.*................................................+-|
| * * |
3 |-+......+-+*.......*.*................................................+-|
| * * * * |
2.5 |-+......*..*.......*.*.................................+-+*...........+-|
| * * * * * * |
2 |-+......*..*.......*.*.................................*..*...........+-|
| * * * * * * +-+ |
1.5 |-+......*..*.......*.*.................................*..*.*+-+.*+-+.+-|
| * * *+-+ * * +-+ *+-+ +-+ +-+ * * * * * * |
1 |++++-+*+*++*+*++*++*+*++*+*+++-+*+*+-++*+-++++-++++-+++*++*+*++*+*++*+++|
| * * * * * * * * * * * * * * * * * * * * * * * * * * |
0.5 +------------------------------------------------------------------------+
400.perlb401.bzip403.g429445.g456.hm462.libq464.h471.omn47483.xalancbgeomean
png: https://imgur.com/YRF90f7
That is, a 1.51x average speedup over the baseline, with a max speedup
of 5.17x.
Here's a different look at the SPEC06int results, using KVM as the baseline:
x86_64-softmmu slowdown vs. KVM for SPEC06int (test set)
Host: Intel(R) Xeon(R) Gold 6142 CPU @ 2.60GHz (Skylake)
25 +---------------------------------------------------------------------------+
| +-+ +-+ |
| * * +-+ v3.1.0 |
| * * +-+ tlb-dyn-v5 |
| * * * * +-+ |
20 |-+.................*.*.............................*.+-+......*.*........+-|
| * * * # # * * |
| +-+ * * * # # * * |
| * * * * * # # * * |
15 |-+......*.*........*.*.............................*.#.#......*.+-+......+-|
| * * * * * # # * #|# |
| * * * * +-+ * # # * +-+ |
| * * +-+ * * ++-+ +-+ * # # * # # +-+ |
| * * +-+ * * * ## *| +-+ * # # * # # +-+ |
10 |-+......*.*..*.+-+.*.*........*.##.......++-+.*.+-+*.#.#......*.#.#.*.*..+-|
| * * * +-+ * * * ## +-+ *# # * # #* # # +-+ * # # * * |
| * * * # # * * +-+ * ## * +-+ *# # * # #* # # * * * # # *+-+ |
| * * * # # * * * +-+ * ## * # # *# # * # #* # # * * * # # * ## |
5 |-+......*.+-+*.#.#.*.*..*.#.#.*.##.*.#.#.*#.#.*.#.#*.#.#.*.*..*.#.#.*.##.+-|
| * # #* # # * +-+* # # * ## * # # *# # * # #* # # * * * # # * ## |
| * # #* # # * # #* # # * ## * # # *# # * # #* # # * +-+* # # * ## |
| ++-+ * # #* # # * # #* # # * ## * # # *# # * # #* # # * # #* # # * ## |
|+++*#+#+*+#+#*+#+#+*+#+#*+#+#+*+##+*+#+#+*#+#+*+#+#*+#+#+*+#+#*+#+#+*+##+++|
0 +---------------------------------------------------------------------------+
400.perlbe401.bzi403.gc429445.go456.h462.libqu464.h471.omne4483.xalancbmgeomean
png: https://imgur.com/YzAMNEV
After this series, we bring down the average SPEC06int slowdown vs KVM
from 11.47x to 7.58x.
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: f7bcd966698f31246127a9a201e76bfd47cd72c8
https://github.com/qemu/qemu/commit/f7bcd966698f31246127a9a201e76bfd47cd72c8
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M tcg/aarch64/tcg-target.h
M tcg/aarch64/tcg-target.inc.c
Log Message:
-----------
tcg/aarch64: enable dynamic TLB sizing
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 644f591ab01883138519e8aa6d4ee3b5b606f43c
https://github.com/qemu/qemu/commit/644f591ab01883138519e8aa6d4ee3b5b606f43c
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M tcg/ppc/tcg-target.h
M tcg/ppc/tcg-target.inc.c
Log Message:
-----------
tcg/ppc: enable dynamic TLB sizing
Signed-off-by: Richard Henderson <address@hidden>
Commit: 17ff9f7801235115cb7d83a9de76c699ce805d5b
https://github.com/qemu/qemu/commit/17ff9f7801235115cb7d83a9de76c699ce805d5b
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M tcg/sparc/tcg-target.h
M tcg/sparc/tcg-target.inc.c
Log Message:
-----------
tcg/sparc: enable dynamic TLB sizing
Signed-off-by: Richard Henderson <address@hidden>
Commit: 4f47e338f607eba1cab47588fb81d41c2222ade0
https://github.com/qemu/qemu/commit/4f47e338f607eba1cab47588fb81d41c2222ade0
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M tcg/s390/tcg-target.h
M tcg/s390/tcg-target.inc.c
Log Message:
-----------
tcg/s390: enable dynamic TLB sizing
Signed-off-by: Richard Henderson <address@hidden>
Commit: 41b70f220b8395ea1ceabb6bd4ee53a0eba195ef
https://github.com/qemu/qemu/commit/41b70f220b8395ea1ceabb6bd4ee53a0eba195ef
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M tcg/riscv/tcg-target.h
M tcg/riscv/tcg-target.inc.c
Log Message:
-----------
tcg/riscv: enable dynamic TLB sizing
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: cd7d3cb7a26297c2ca28da68bbc7aacec0c04d25
https://github.com/qemu/qemu/commit/cd7d3cb7a26297c2ca28da68bbc7aacec0c04d25
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M tcg/arm/tcg-target.h
M tcg/arm/tcg-target.inc.c
Log Message:
-----------
tcg/arm: enable dynamic TLB sizing
Signed-off-by: Richard Henderson <address@hidden>
Commit: a31aa4ce00bb8b7ed01d82d08ce2ca94c2e408d2
https://github.com/qemu/qemu/commit/a31aa4ce00bb8b7ed01d82d08ce2ca94c2e408d2
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M tcg/mips/tcg-target.inc.c
Log Message:
-----------
tcg/mips: Fix tcg_out_qemu_ld_slow_path
Patch the branch after it has been emitted rather
than before it exists.
Signed-off-by: Richard Henderson <address@hidden>
Commit: ac33373e0ed49a815f6906d0882898f1a9d89f24
https://github.com/qemu/qemu/commit/ac33373e0ed49a815f6906d0882898f1a9d89f24
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M tcg/mips/tcg-target.h
M tcg/mips/tcg-target.inc.c
Log Message:
-----------
tcg/mips: enable dynamic TLB sizing
Signed-off-by: Richard Henderson <address@hidden>
Commit: 0a9a83d6bf9c42da05e46583e6a2ed11599ea089
https://github.com/qemu/qemu/commit/0a9a83d6bf9c42da05e46583e6a2ed11599ea089
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M tcg/tci/tcg-target.h
Log Message:
-----------
tcg/tci: enable dynamic TLB sizing
This is automatic due to TCI using the other softtlb macros.
Signed-off-by: Richard Henderson <address@hidden>
Commit: e77c89fb086a9bf09dd11f72e4cb2093b426f32b
https://github.com/qemu/qemu/commit/e77c89fb086a9bf09dd11f72e4cb2093b426f32b
Author: Richard Henderson <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M accel/tcg/cputlb.c
M include/exec/cpu-defs.h
M include/exec/cpu_ldst.h
M tcg/aarch64/tcg-target.h
M tcg/arm/tcg-target.h
M tcg/i386/tcg-target.h
M tcg/mips/tcg-target.h
M tcg/ppc/tcg-target.h
M tcg/riscv/tcg-target.h
M tcg/s390/tcg-target.h
M tcg/sparc/tcg-target.h
M tcg/tci/tcg-target.h
Log Message:
-----------
cputlb: Remove static tlb sizing
Now that all tcg backends support TCG_TARGET_IMPLEMENTS_DYN_TLB,
remove the define and the old code.
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Commit: 3a183e330dbd7dbcac3841737ac874979552cca2
https://github.com/qemu/qemu/commit/3a183e330dbd7dbcac3841737ac874979552cca2
Author: Peter Maydell <address@hidden>
Date: 2019-01-28 (Mon, 28 Jan 2019)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/tcg-runtime-gvec.c
M accel/tcg/tcg-runtime.h
M include/exec/cpu-defs.h
M include/exec/cpu_ldst.h
M tcg/README
M tcg/aarch64/tcg-target.h
M tcg/aarch64/tcg-target.inc.c
M tcg/arm/tcg-target.inc.c
M tcg/i386/tcg-target.h
M tcg/i386/tcg-target.inc.c
M tcg/mips/tcg-target.inc.c
M tcg/ppc/tcg-target.inc.c
M tcg/riscv/tcg-target.inc.c
M tcg/s390/tcg-target.inc.c
M tcg/sparc/tcg-target.inc.c
M tcg/tcg-op-gvec.c
M tcg/tcg-op-gvec.h
M tcg/tcg-op-vec.c
M tcg/tcg-op.h
M tcg/tcg-opc.h
M tcg/tcg.c
M tcg/tcg.h
Log Message:
-----------
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190128' into staging
Backend vector enhancements
Dynamic tlb resizing
# gpg: Signature made Mon 28 Jan 2019 15:57:19 GMT
# gpg: using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <address@hidden>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-tcg-20190128: (23 commits)
cputlb: Remove static tlb sizing
tcg/tci: enable dynamic TLB sizing
tcg/mips: enable dynamic TLB sizing
tcg/mips: Fix tcg_out_qemu_ld_slow_path
tcg/arm: enable dynamic TLB sizing
tcg/riscv: enable dynamic TLB sizing
tcg/s390: enable dynamic TLB sizing
tcg/sparc: enable dynamic TLB sizing
tcg/ppc: enable dynamic TLB sizing
tcg/aarch64: enable dynamic TLB sizing
tcg/i386: enable dynamic TLB sizing
tcg: introduce dynamic TLB sizing
cputlb: do not evict empty entries to the vtlb
tcg/aarch64: Implement vector minmax arithmetic
tcg/aarch64: Implement vector saturating arithmetic
tcg/i386: Implement vector minmax arithmetic
tcg/i386: Implement vector saturating arithmetic
tcg/i386: Split subroutines out of tcg_expand_vec_op
tcg: Add opcodes for vector minmax arithmetic
tcg: Add opcodes for vector saturated arithmetic
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/5f39a91dbd9a...3a183e330dbd
**NOTE:** GitHub Services has been marked for deprecation:
https://developer.github.com/changes/2018-04-25-github-services-deprecation/
We will provide an alternative path for the email notifications by
January 31st, 2019.
[Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Qemu-commits] [qemu/qemu] 9a9eda: tcg: Add logical simplifications during gvec expan...,
GitHub <=