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[Qemu-commits] [qemu/qemu] ea9c5e: target/mips: Move comment containing

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] ea9c5e: target/mips: Move comment containing summary of CP...
Date: Mon, 21 Jan 2019 11:19:14 -0800 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: ea9c5e836e205a87038c8153282d0b6d9234cda2
      
https://github.com/qemu/qemu/commit/ea9c5e836e205a87038c8153282d0b6d9234cda2
  Author: Aleksandar Markovic <address@hidden>
  Date:   2019-01-18 (Fri, 18 Jan 2019)

  Changed paths:
    M target/mips/cpu.h

  Log Message:
  -----------
  target/mips: Move comment containing summary of CP0 registers

Move comment containing summary of CP0 registers. Checkpatch
script reported some tabs in the resutling diff, so convert
these tabs to spaces too.

Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: efd27d3f08655fc2bcf79a529566aee2cb2e81f8
      
https://github.com/qemu/qemu/commit/efd27d3f08655fc2bcf79a529566aee2cb2e81f8
  Author: Aleksandar Markovic <address@hidden>
  Date:   2019-01-18 (Fri, 18 Jan 2019)

  Changed paths:
    M target/mips/cpu.h

  Log Message:
  -----------
  target/mips: Add preprocessor constants for 32 major CP0 registers

Add preprocessor constants for 32 major CP0 registers.

Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 46d7642fcc97ac108c8080fbe41bc5d00bb537f2
      
https://github.com/qemu/qemu/commit/46d7642fcc97ac108c8080fbe41bc5d00bb537f2
  Author: Aleksandar Markovic <address@hidden>
  Date:   2019-01-18 (Fri, 18 Jan 2019)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Use preprocessor constants for 32 major CP0 registers

Use preprocessor constants for 32 major CP0 registers.

Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 167db30e981cd72bef15182178037e51afc8e40d
      
https://github.com/qemu/qemu/commit/167db30e981cd72bef15182178037e51afc8e40d
  Author: Yongbok Kim <address@hidden>
  Date:   2019-01-18 (Fri, 18 Jan 2019)

  Changed paths:
    M target/mips/cpu.h
    M target/mips/machine.c

  Log Message:
  -----------
  target/mips: Add fields for SAARI and SAAR CP0 registers

Add fields for SAARI and SAAR CP0 registers.

Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 5fb2dcd17921be71b55fb62d59a12992707d2d3e
      
https://github.com/qemu/qemu/commit/5fb2dcd17921be71b55fb62d59a12992707d2d3e
  Author: Yongbok Kim <address@hidden>
  Date:   2019-01-18 (Fri, 18 Jan 2019)

  Changed paths:
    M target/mips/cpu.h
    M target/mips/helper.h
    M target/mips/internal.h
    M target/mips/op_helper.c
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Provide R/W access to SAARI and SAAR CP0 registers

Provide R/W access to SAARI and SAAR CP0 registers.

Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: e5345d96752a9dec441b022502be34e01bcacca8
      
https://github.com/qemu/qemu/commit/e5345d96752a9dec441b022502be34e01bcacca8
  Author: Yongbok Kim <address@hidden>
  Date:   2019-01-18 (Fri, 18 Jan 2019)

  Changed paths:
    M hw/misc/mips_itu.c
    M include/hw/misc/mips_itu.h

  Log Message:
  -----------
  target/mips: Add field and R/W access to ITU control register ICR0

Add field and R/W access to ITU control register ICR0.

Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 043715d1e0fbb3e3411be3f898c5b77b7f90327a
      
https://github.com/qemu/qemu/commit/043715d1e0fbb3e3411be3f898c5b77b7f90327a
  Author: Yongbok Kim <address@hidden>
  Date:   2019-01-18 (Fri, 18 Jan 2019)

  Changed paths:
    M hw/mips/cps.c
    M hw/misc/mips_itu.c
    M include/hw/misc/mips_itu.h
    M target/mips/cpu.h
    M target/mips/op_helper.c

  Log Message:
  -----------
  target/mips: Update ITU to utilize SAARI and SAAR CP0 registers

Update ITU to utilize SAARI and SAAR CP0 registers.

Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 40cd718052b6c665c41852b95e723f03469f65be
      
https://github.com/qemu/qemu/commit/40cd718052b6c665c41852b95e723f03469f65be
  Author: Yongbok Kim <address@hidden>
  Date:   2019-01-18 (Fri, 18 Jan 2019)

  Changed paths:
    M hw/misc/mips_itu.c

  Log Message:
  -----------
  target/mips: Update ITU to handle bus errors

Update ITU to handle bus errors.

Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 04992c8cd1c43ecdba39dd8c916db092db6ebae0
      
https://github.com/qemu/qemu/commit/04992c8cd1c43ecdba39dd8c916db092db6ebae0
  Author: Aleksandar Markovic <address@hidden>
  Date:   2019-01-18 (Fri, 18 Jan 2019)

  Changed paths:
    M target/mips/cpu.h
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Amend preprocessor constants for CP0 registers

Correct existing CP0-related preprocessor constants (replace
"CPO" with "CP0" (form letter "O" to digit "0", when needed).
Besides, add preprocessor constants for CP0 subregisters.
The names of the subregisters were chosen to be in sync with
the table of corresponding assembler mnemonics found in the
documentation for I6500 and I6400 (release 1.0).

Reviewed-by: Aleksandar Rikalo <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 3ef521ee9fe2d01d4bbcf3e4d5c91ed982bf3f60
      
https://github.com/qemu/qemu/commit/3ef521ee9fe2d01d4bbcf3e4d5c91ed982bf3f60
  Author: Aleksandar Markovic <address@hidden>
  Date:   2019-01-18 (Fri, 18 Jan 2019)

  Changed paths:
    M target/mips/cpu.h
    M target/mips/machine.c

  Log Message:
  -----------
  target/mips: Add CP0 register MemoryMapID

Add CP0 register MemoryMapID. Only data field is added.
The corresponding functionality will be added in future
patches.

Reviewed-by: Aleksandar Rikalo <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 294fc2ea7f8af913523bf004433704377d9ee7a8
      
https://github.com/qemu/qemu/commit/294fc2ea7f8af913523bf004433704377d9ee7a8
  Author: Aleksandar Markovic <address@hidden>
  Date:   2019-01-18 (Fri, 18 Jan 2019)

  Changed paths:
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Rename 'rn' to 'register_name'

Rename 'rn' to 'register_name' in CP0-related handlers.

Reviewed-by: Aleksandar Rikalo <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: a168a796e1c251787fcdf2d9ca1e9e69cb86ffcd
      
https://github.com/qemu/qemu/commit/a168a796e1c251787fcdf2d9ca1e9e69cb86ffcd
  Author: Fredrik Noring <address@hidden>
  Date:   2019-01-18 (Fri, 18 Jan 2019)

  Changed paths:
    M target/mips/cpu.h
    M target/mips/translate.c

  Log Message:
  -----------
  target/mips: Introduce 32 R5900 multimedia registers

The 32 R5900 128-bit registers are split into two 64-bit halves:
the lower halves are the GPRs and the upper halves are accessible
by the R5900-specific multimedia instructions.

Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>


  Commit: 166609e6070fab3424510ac7292ecb585f8b80fb
      
https://github.com/qemu/qemu/commit/166609e6070fab3424510ac7292ecb585f8b80fb
  Author: Peter Maydell <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M hw/mips/cps.c
    M hw/misc/mips_itu.c
    M include/hw/misc/mips_itu.h
    M target/mips/cpu.h
    M target/mips/helper.h
    M target/mips/internal.h
    M target/mips/machine.c
    M target/mips/op_helper.c
    M target/mips/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/amarkovic/tags/mips-queue-january-17-2019-v2' into staging

MIPS queue for January 17, 2019 - v2

# gpg: Signature made Fri 18 Jan 2019 15:55:35 GMT
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <address@hidden>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-january-17-2019-v2:
  target/mips: Introduce 32 R5900 multimedia registers
  target/mips: Rename 'rn' to 'register_name'
  target/mips: Add CP0 register MemoryMapID
  target/mips: Amend preprocessor constants for CP0 registers
  target/mips: Update ITU to handle bus errors
  target/mips: Update ITU to utilize SAARI and SAAR CP0 registers
  target/mips: Add field and R/W access to ITU control register ICR0
  target/mips: Provide R/W access to SAARI and SAAR CP0 registers
  target/mips: Add fields for SAARI and SAAR CP0 registers
  target/mips: Use preprocessor constants for 32 major CP0 registers
  target/mips: Add preprocessor constants for 32 major CP0 registers
  target/mips: Move comment containing summary of CP0 registers

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/5385a5988c8a...166609e6070f
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