[Qemu-commits] [qemu/qemu] 407661: hw/char/stm32f2xx_usart: Do not update data regist...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 4076618095099702e0a29e47aac30b4931a1f54b
      
https://github.com/qemu/qemu/commit/4076618095099702e0a29e47aac30b4931a1f54b
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M hw/char/stm32f2xx_usart.c

  Log Message:
  -----------
  hw/char/stm32f2xx_usart: Do not update data register when device is disabled

When the device is disabled, the internal circuitry keeps the data
register loaded and doesn't update it.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 29bbccc27874caa81106a40ee18d5e311c15451b
      
https://github.com/qemu/qemu/commit/29bbccc27874caa81106a40ee18d5e311c15451b
  Author: Eric Auger <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M hw/arm/virt-acpi-build.c
    M include/hw/acpi/acpi-defs.h

  Log Message:
  -----------
  hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node

Let's report IO-coherent access is supported for translation
table walks, descriptor fetches and queues by setting the COHACC
override flag. Without that, we observe wrong command opcodes.
The DT description also advertises the dma coherency.

Fixes a703b4f6c1ee ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT table")

Signed-off-by: Eric Auger <address@hidden>
Reported-by: Shameerali Kolothum Thodi <address@hidden>
Tested-by: Shameer Kolothum <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2d2a4549cc29850aab891495685a7b31f5254b12
      
https://github.com/qemu/qemu/commit/2d2a4549cc29850aab891495685a7b31f5254b12
  Author: Alexander Graf <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Allow Aarch32 exception return to switch from Mon->Hyp

In U-boot, we switch from S-SVC -> Mon -> Hyp mode when we want to
enter Hyp mode. The change into Hyp mode is done by doing an
exception return from Mon. This doesn't work with current QEMU.

The problem is that in bad_mode_switch() we refuse to allow
the change of mode.

Note that bad_mode_switch() is used to do validation for two situations:

 (1) changes to mode by instructions writing to CPSR.M
     (ie not exception take/return) -- this corresponds to the
     Armv8 Arm ARM pseudocode Arch32.WriteModeByInstr
 (2) changes to mode by exception return

Attempting to enter or leave Hyp mode via case (1) is forbidden in
v8 and UNPREDICTABLE in v7, and QEMU is correct to disallow it
there. However, we're already doing that check at the top of the
bad_mode_switch() function, so if that passes then we should allow
the case (2) exception return mode changes to switch into Hyp mode.

We want to test whether we're trying to return to the nonexistent
"secure Hyp" mode, so we need to look at arm_is_secure_below_el3()
rather than arm_is_secure(), since the latter is always true if
we're in Mon (EL3).

Signed-off-by: Alexander Graf <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: rewrote commit message]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f16c845ade38444db62dc14eb5e267cc0c79876b
      
https://github.com/qemu/qemu/commit/f16c845ade38444db62dc14eb5e267cc0c79876b
  Author: Cédric Le Goater <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M hw/net/ftgmac100.c

  Log Message:
  -----------
  ftgmac100: implement the new MDIO interface on Aspeed SoC

The PHY behind the MAC of an Aspeed SoC can be controlled using two
different MDC/MDIO interfaces. The same registers PHYCR (MAC60) and
PHYDATA (MAC64) are involved but they have a different layout.

BIT31 of the Feature Register (MAC40) controls which MDC/MDIO
interface is active.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 991ad91b6a1f09a6ad62b6e6da78d83b548daec7
      
https://github.com/qemu/qemu/commit/991ad91b6a1f09a6ad62b6e6da78d83b548daec7
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Add state for the ARMv8.3-PAuth extension

Add storage space for the 5 encryption keys.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[PMM: use 0xf rather than -1 in FIELD_DP64() expressions to
 avoid clang warnings about implicit truncation from int to
 bitfield changing the value]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b2af69d0b6e0edcb789ca1fcc1199bbfde6ed986
      
https://github.com/qemu/qemu/commit/b2af69d0b6e0edcb789ca1fcc1199bbfde6ed986
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Add SCTLR bits through ARMv8.5

Post v8.4 bits taken from SysReg_v85_xml-00bet8.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0816ef1bfcd3ac53e7454b62ca436727887f6056
      
https://github.com/qemu/qemu/commit/0816ef1bfcd3ac53e7454b62ca436727887f6056
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Add PAuth active bit to tbflags

There are 5 bits of state that could be added, but to save
space within tbflags, add only a single enable bit.
Helpers will determine the rest of the state at runtime.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7469f6c696d74ad3b22b67c08e1e8f79e2b5d3d6
      
https://github.com/qemu/qemu/commit/7469f6c696d74ad3b22b67c08e1e8f79e2b5d3d6
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/internals.h
    M target/arm/op_helper.c

  Log Message:
  -----------
  target/arm: Introduce raise_exception_ra

This path uses cpu_loop_exit_restore to unwind current processor state.

Suggested-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0d43e1a2d29a05f7b0d5629caaff18733cbdf3bb
      
https://github.com/qemu/qemu/commit/0d43e1a2d29a05f7b0d5629caaff18733cbdf3bb
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/Makefile.objs
    M target/arm/helper-a64.h
    M target/arm/internals.h
    A target/arm/pauth_helper.c

  Log Message:
  -----------
  target/arm: Add PAuth helpers

The cryptographic internals are stubbed out for now,
but the enable and trap bits are checked.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7c94c8343c6a0eea1633a65ed27987b6a71b9089
      
https://github.com/qemu/qemu/commit/7c94c8343c6a0eea1633a65ed27987b6a71b9089
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Decode PAuth within system hint space

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 18de2813c35e359621a24a0a2a77570e83cb73b9
      
https://github.com/qemu/qemu/commit/18de2813c35e359621a24a0a2a77570e83cb73b9
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Rearrange decode in disas_data_proc_1src

Now properly signals unallocated for REV64 with SF=0.
Allows for the opcode2 field to be decoded shortly.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 95ebd99dcd37b8574426c876502bfcc7c299584b
      
https://github.com/qemu/qemu/commit/95ebd99dcd37b8574426c876502bfcc7c299584b
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Decode PAuth within disas_data_proc_1src

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b6342a9f929b5946beb6726eef2ef2c5f4a11f09
      
https://github.com/qemu/qemu/commit/b6342a9f929b5946beb6726eef2ef2c5f4a11f09
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Decode PAuth within disas_data_proc_2src

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ce02fd99e6d53df6f3cf5eca85bcac403b402510
      
https://github.com/qemu/qemu/commit/ce02fd99e6d53df6f3cf5eca85bcac403b402510
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/helper-a64.c
    M target/arm/helper-a64.h
    M target/arm/helper.h
    M target/arm/op_helper.c

  Log Message:
  -----------
  target/arm: Move helper_exception_return to helper-a64.c

This function is only used by AArch64.  Code movement only.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d9f482a0279773c3253092ea149daaf00358c635
      
https://github.com/qemu/qemu/commit/d9f482a0279773c3253092ea149daaf00358c635
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/helper-a64.c
    M target/arm/helper-a64.h
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Add new_pc argument to helper_exception_return

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f7cf3bfc1b65a8c550b8439374c0060f7311ad50
      
https://github.com/qemu/qemu/commit/f7cf3bfc1b65a8c550b8439374c0060f7311ad50
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Rearrange decode in disas_uncond_b_reg

This will enable PAuth decode in a subsequent patch.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 561c0a33080f1058a7671d0223122c98e4c9c1f0
      
https://github.com/qemu/qemu/commit/561c0a33080f1058a7671d0223122c98e4c9c1f0
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Decode PAuth within disas_uncond_b_reg

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bd889f4810839a2b68e339696ccf7c406cd62879
      
https://github.com/qemu/qemu/commit/bd889f4810839a2b68e339696ccf7c406cd62879
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Decode Load/store register (pac)

Not that there are any stores involved, but why argue with ARM's
naming convention.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[fixed trivial comment nit]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 65e4655c609a4a2fd428459d3efb62b704488fd6
      
https://github.com/qemu/qemu/commit/65e4655c609a4a2fd428459d3efb62b704488fd6
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Move cpu_mmu_index out of line

This function is, or will shortly become, too big to inline.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 50494a279dab22a015aba9501a94fcc3cd52140e
      
https://github.com/qemu/qemu/commit/50494a279dab22a015aba9501a94fcc3cd52140e
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Introduce arm_mmu_idx

The pattern

  ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));

is computing the full ARMMMUIdx, stripping off the ARM bits,
and then putting them back.

Avoid the extra two steps with the appropriate helper function.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 64be86ab1b5ef10b660a4230ee7f27c0da499043
      
https://github.com/qemu/qemu/commit/64be86ab1b5ef10b660a4230ee7f27c0da499043
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Introduce arm_stage1_mmu_idx

While we could expose stage_1_mmu_idx, the combination is
probably going to be more useful.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ba97be9f4a4ecaf16a1454dc669e5f3d935d3b63
      
https://github.com/qemu/qemu/commit/ba97be9f4a4ecaf16a1454dc669e5f3d935d3b63
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Create ARMVAParameters and helpers

Split out functions to extract the virtual address parameters.
Let the functions choose T0 or T1 address space half, if present.
Extract (most of) the control bits that vary between EL or Tx.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: fixed minor checkpatch comment nits]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 476a4692f06e381117fb7ad0d04d37c9c2612198
      
https://github.com/qemu/qemu/commit/476a4692f06e381117fb7ad0d04d37c9c2612198
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII

We will shortly want to talk about TBI as it relates to data.
Passing around a pair of variables is less convenient than a
single variable.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bf0be433878935e824479e8ae890493e1fb646ed
      
https://github.com/qemu/qemu/commit/bf0be433878935e824479e8ae890493e1fb646ed
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Export aa64_va_parameters to internals.h

We need to reuse this from helper-a64.c.  Provide a stub
definition for CONFIG_USER_ONLY.  This matches the stub
definitions that we removed for arm_regime_tbi{0,1} before.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e737ed2ad8c14b4b82ed241646ffa370d29d0937
      
https://github.com/qemu/qemu/commit/e737ed2ad8c14b4b82ed241646ffa370d29d0937
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Add aa64_va_parameters_both

We will want to check TBI for I and D simultaneously.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8220af7e4d34c858898fbfe55943aeea8f4e875f
      
https://github.com/qemu/qemu/commit/8220af7e4d34c858898fbfe55943aeea8f4e875f
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Decode TBID from TCR

Use TBID in aa64_va_parameters depending on the data parameter.
This automatically updates all existing users of the function.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5d8634f5a3a8474525edcfd581a659830e9e97c0
      
https://github.com/qemu/qemu/commit/5d8634f5a3a8474525edcfd581a659830e9e97c0
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Reuse aa64_va_parameters for setting tbflags

The arm_regime_tbi{0,1} functions are replacable with the new function
by giving the lowest and highest address.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 04d13549fa10bb9775a90701e4e6fd0a2cbf83cb
      
https://github.com/qemu/qemu/commit/04d13549fa10bb9775a90701e4e6fd0a2cbf83cb
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/pauth_helper.c

  Log Message:
  -----------
  target/arm: Implement pauth_strip

Stripping out the authentication data does not require any crypto,
it merely requires the virtual address parameters.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a7bfa086c973a51fc18116c9d2e22a0e0069edba
      
https://github.com/qemu/qemu/commit/a7bfa086c973a51fc18116c9d2e22a0e0069edba
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/pauth_helper.c

  Log Message:
  -----------
  target/arm: Implement pauth_auth

This is not really functional yet, because the crypto is not yet
implemented.  This, however follows the Auth pseudo function.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 63ff0ca94cb84764d2aee45b37c5502a54811dab
      
https://github.com/qemu/qemu/commit/63ff0ca94cb84764d2aee45b37c5502a54811dab
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/pauth_helper.c

  Log Message:
  -----------
  target/arm: Implement pauth_addpac

This is not really functional yet, because the crypto is not yet
implemented.  This, however follows the AddPAC pseudo function.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 990870b205ddfdba3fd3c1321e6083005ef59d1a
      
https://github.com/qemu/qemu/commit/990870b205ddfdba3fd3c1321e6083005ef59d1a
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/pauth_helper.c

  Log Message:
  -----------
  target/arm: Implement pauth_computepac

This is the main crypto routine, an implementation of QARMA.
This matches, as much as possible, ARM pseudocode.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: fixed minor checkpatch nits]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 967aa94f2b0df08d744b6d0bfa21031175e8a0e6
      
https://github.com/qemu/qemu/commit/967aa94f2b0df08d744b6d0bfa21031175e8a0e6
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add PAuth system registers

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1ce32e47db52e3511132c7104770eae65d412144
      
https://github.com/qemu/qemu/commit/1ce32e47db52e3511132c7104770eae65d412144
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Enable PAuth for -cpu max

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1ae9cfbd470bffb8d9bacd761344e9b5e8adecb6
      
https://github.com/qemu/qemu/commit/1ae9cfbd470bffb8d9bacd761344e9b5e8adecb6
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu64.c

  Log Message:
  -----------
  target/arm: Enable PAuth for user-only

Add 4 attributes that controls the EL1 enable bits, as we may not
always want to turn on pointer authentication with -cpu max.
However, by default they are enabled.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8733d762d5e089a017ac7c5bc71077a8d75d1b46
      
https://github.com/qemu/qemu/commit/8733d762d5e089a017ac7c5bc71077a8d75d1b46
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Tidy TBI handling in gen_a64_set_pc

We can perform this with fewer operations.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8c07559fc7ee132e2145ad09299a08c10ebe7804
      
https://github.com/qemu/qemu/commit/8c07559fc7ee132e2145ad09299a08c10ebe7804
  Author: Aaron Lindsay <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M docs/devel/migration.rst
    M include/migration/vmstate.h
    M migration/vmstate.c

  Log Message:
  -----------
  migration: Add post_save function to VMStateDescription

In some cases it may be helpful to modify state before saving it for
migration, and then modify the state back after it has been saved. The
existing pre_save function provides half of this functionality. This
patch adds a post_save function to provide the second half.

Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Dr. David Alan Gilbert <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5d05b9d462666ed21b7fef61aa45dec9aaa9f0ff
      
https://github.com/qemu/qemu/commit/5d05b9d462666ed21b7fef61aa45dec9aaa9f0ff
  Author: Aaron Lindsay <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Reorganize PMCCNTR accesses

pmccntr_read and pmccntr_write contained duplicate code that was already
being handled by pmccntr_sync. Consolidate the duplicated code into two
functions: pmccntr_op_start and pmccntr_op_finish. Add a companion to
c15_ccnt in CPUARMState so that we can simultaneously save both the
architectural register value and the last underlying cycle count - this
ensures time isn't lost and will also allow us to access the 'old'
architectural register value in order to detect overflows in later
patches.

Signed-off-by: Aaron Lindsay <address@hidden>
Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 980ebe87053792a5bdefaa87777c40914fd4f673
      
https://github.com/qemu/qemu/commit/980ebe87053792a5bdefaa87777c40914fd4f673
  Author: Aaron Lindsay <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/helper.c
    M target/arm/machine.c

  Log Message:
  -----------
  target/arm: Swap PMU values before/after migrations

Because of the PMU's design, many register accesses have side effects
which are inter-related, meaning that the normal method of saving CP
registers can result in inconsistent state. These side-effects are
largely handled in pmu_op_start/finish functions which can be called
before and after the state is saved/restored. By doing this and adding
raw read/write functions for the affected registers, we avoid
migration-related inconsistencies.

Signed-off-by: Aaron Lindsay <address@hidden>
Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 033614c47de78409ad3fb39bb7bd1483b71c6789
      
https://github.com/qemu/qemu/commit/033614c47de78409ad3fb39bb7bd1483b71c6789
  Author: Aaron Lindsay <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Filter cycle counter based on PMCCFILTR_EL0

Rename arm_ccnt_enabled to pmu_counter_enabled, and add logic to only
return 'true' if the specified counter is enabled and neither prohibited
or filtered.

Signed-off-by: Aaron Lindsay <address@hidden>
Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4b8afa1f99c3575f6cfb26770f90e9fd7bc45468
      
https://github.com/qemu/qemu/commit/4b8afa1f99c3575f6cfb26770f90e9fd7bc45468
  Author: Aaron Lindsay <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Allow AArch32 access for PMCCFILTR

Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 327dd5108bb3b66bb5102b659e83a4348a005f5e
      
https://github.com/qemu/qemu/commit/327dd5108bb3b66bb5102b659e83a4348a005f5e
  Author: Aaron Lindsay <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement PMOVSSET

Add an array for PMOVSSET so we only define it for v7ve+ platforms

Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: beceb99c0c1218d0b55cc04ce6ef77579d3416cb
      
https://github.com/qemu/qemu/commit/beceb99c0c1218d0b55cc04ce6ef77579d3416cb
  Author: Aaron Lindsay <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Define FIELDs for ID_DFR0

This is immediately necessary for the PMUv3 implementation to check
ID_DFR0.PerfMon to enable/disable specific features, but defines the
full complement of fields for possible future use elsewhere.

Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: cad8673744d0914587cd7380e70df11e8c4a0f50
      
https://github.com/qemu/qemu/commit/cad8673744d0914587cd7380e70df11e8c4a0f50
  Author: Aaron Lindsay <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]

Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 57a4a11b2b281bb548b419ca81bfafb214e4c77a
      
https://github.com/qemu/qemu/commit/57a4a11b2b281bb548b419ca81bfafb214e4c77a
  Author: Aaron Lindsay <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0

This commit doesn't add any supported events, but provides the framework
for adding them. We store the pm_event structs in a simple array, and
provide the mapping from the event numbers to array indexes in the
supported_event_map array. Because the value of PMCEID[01] depends upon
which events are supported at runtime, generate it dynamically.

Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5ecdd3e47cadae83a62dc92b472f1fe163b56f59
      
https://github.com/qemu/qemu/commit/5ecdd3e47cadae83a62dc92b472f1fe163b56f59
  Author: Aaron Lindsay <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER

Add arrays to hold the registers, the definitions themselves, access
functions, and logic to reset counters when PMCR.P is set. Update
filtering code to support counters other than PMCCNTR. Support migration
with raw read/write functions.

Signed-off-by: Aaron Lindsay <address@hidden>
Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b2e2372511946fae86fbb8709edec7a41c6f3167
      
https://github.com/qemu/qemu/commit/b2e2372511946fae86fbb8709edec7a41c6f3167
  Author: Aaron Lindsay <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: PMU: Add instruction and cycle events

The instruction event is only enabled when icount is used, cycles are
always supported. Always defining get_cycle_count (but altering its
behavior depending on CONFIG_USER_ONLY) allows us to remove some
CONFIG_USER_ONLY #defines throughout the rest of the code.

Signed-off-by: Aaron Lindsay <address@hidden>
Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ac689a2e5155d129acaa39603e2a7a29abd90d89
      
https://github.com/qemu/qemu/commit/ac689a2e5155d129acaa39603e2a7a29abd90d89
  Author: Aaron Lindsay <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: PMU: Set PMCR.N to 4

This both advertises that we support four counters and enables them
because the pmu_num_counters() reads this value from PMCR.

Signed-off-by: Aaron Lindsay <address@hidden>
Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0d4bfd7df809863b1f45fad35229fb9419527d06
      
https://github.com/qemu/qemu/commit/0d4bfd7df809863b1f45fad35229fb9419527d06
  Author: Aaron Lindsay <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement PMSWINC

Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bbca106776ab5decb01a0f101c67524546a1fcd2
      
https://github.com/qemu/qemu/commit/bbca106776ab5decb01a0f101c67524546a1fcd2
  Author: Peter Maydell <address@hidden>
  Date:   2019-01-21 (Mon, 21 Jan 2019)

  Changed paths:
    M docs/devel/migration.rst
    M hw/arm/virt-acpi-build.c
    M hw/char/stm32f2xx_usart.c
    M hw/net/ftgmac100.c
    M include/hw/acpi/acpi-defs.h
    M include/migration/vmstate.h
    M migration/vmstate.c
    M target/arm/Makefile.objs
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper-a64.c
    M target/arm/helper-a64.h
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/internals.h
    M target/arm/machine.c
    M target/arm/op_helper.c
    A target/arm/pauth_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190121' 
into staging

target-arm queue:
 * hw/char/stm32f2xx_usart: Do not update data register when device is disabled
 * hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node
 * target/arm: Allow Aarch32 exception return to switch from Mon->Hyp
 * ftgmac100: implement the new MDIO interface on Aspeed SoC
 * implement the ARMv8.3-PAuth extension
 * improve emulation of the ARM PMU

# gpg: Signature made Mon 21 Jan 2019 10:42:11 GMT
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190121: (48 commits)
  target/arm: Implement PMSWINC
  target/arm: PMU: Set PMCR.N to 4
  target/arm: PMU: Add instruction and cycle events
  target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
  target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0
  target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
  target/arm: Define FIELDs for ID_DFR0
  target/arm: Implement PMOVSSET
  target/arm: Allow AArch32 access for PMCCFILTR
  target/arm: Filter cycle counter based on PMCCFILTR_EL0
  target/arm: Swap PMU values before/after migrations
  target/arm: Reorganize PMCCNTR accesses
  migration: Add post_save function to VMStateDescription
  target/arm: Tidy TBI handling in gen_a64_set_pc
  target/arm: Enable PAuth for user-only
  target/arm: Enable PAuth for -cpu max
  target/arm: Add PAuth system registers
  target/arm: Implement pauth_computepac
  target/arm: Implement pauth_addpac
  target/arm: Implement pauth_auth
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/f12313995c5b...bbca106776ab
      **NOTE:** This service has been marked for deprecation: 
https://developer.github.com/changes/2018-04-25-github-services-deprecation/

      Functionality will be removed from GitHub.com on January 31st, 2019.