[Qemu-commits] [qemu/qemu] aad821: target/arm: Convert ARM_TBFLAG_* to FIELDs

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: aad821ac4faad369fad8941d25e59edf2514246b
      
https://github.com/qemu/qemu/commit/aad821ac4faad369fad8941d25e59edf2514246b
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert ARM_TBFLAG_* to FIELDs

Use "register" TBFLAG_ANY to indicate shared state between
A32 and A64, and "registers" TBFLAG_A32 & TBFLAG_A64 for
fields that are specific to the given cpu state.

Move ARM_TBFLAG_BE_DATA to shared state, instead of its current
placement within "Bit usage when in AArch32 state".

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
[PMM: removed the renaming of BE_DATA flag to BE]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 407e6ce7f1f428cb242d424cd35381a77b5b2071
      
https://github.com/qemu/qemu/commit/407e6ce7f1f428cb242d424cd35381a77b5b2071
  Author: Richard Henderson <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M target/arm/sve.decode

  Log Message:
  -----------
  target/arm: SVE brk[ab] merging does not have s bit

While brk[ab] zeroing has a flags setting option, the merging variant
does not.  Retain the same argument structure, to share expansion but
force the flag zero and do not decode bit 22.

Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 335d52f457e7b3d959b2ddc93f83a36d75484d88
      
https://github.com/qemu/qemu/commit/335d52f457e7b3d959b2ddc93f83a36d75484d88
  Author: Luc Michel <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M MAINTAINERS
    M hw/cpu/Makefile.objs
    A hw/cpu/cluster.c
    A include/hw/cpu/cluster.h

  Log Message:
  -----------
  hw/cpu: introduce CPU clusters

This commit adds the cpu-cluster type. It aims at gathering CPUs from
the same cluster in a machine.

For now it only has a `cluster-id` property.

Documentation in cluster.h written with the help of Peter Maydell.

Signed-off-by: Luc Michel <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8f468636189303358da3b365c53cb03ae5497eca
      
https://github.com/qemu/qemu/commit/8f468636189303358da3b365c53cb03ae5497eca
  Author: Luc Michel <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M gdbstub.c

  Log Message:
  -----------
  gdbstub: introduce GDB processes

Add a structure GDBProcess that represents processes from the GDB
semantic point of view.

CPUs can be split into different processes, by grouping them under
different cpu-cluster objects.  Each occurrence of a cpu-cluster object
implies the existence of the corresponding process in the GDB stub. The
GDB process ID is derived from the corresponding cluster ID as follows:

  GDB PID = cluster ID + 1

This is because PIDs -1 and 0 are reserved in GDB and cannot be used by
processes.

A default process is created to handle CPUs that are not in a cluster.
This process gets the PID of the last process PID + 1.

Signed-off-by: Luc Michel <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
[PMM: fixed checkpatch nit about block comment style]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1a2273369725111a2bbdb602ca7c679d466618b0
      
https://github.com/qemu/qemu/commit/1a2273369725111a2bbdb602ca7c679d466618b0
  Author: Luc Michel <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M gdbstub.c

  Log Message:
  -----------
  gdbstub: add multiprocess support to '?' packets

The gdb_get_cpu_pid() function does the PID lookup for the given CPU. It
checks if the CPU is a direct child of a CPU cluster. If it is, the
returned PID is the cluster ID plus one (cluster IDs start at 0, GDB
PIDs at 1). When the CPU is not a child of such a container, the PID of
the default process is returned.

The gdb_fmt_thread_id() function generates the string to be used to identify
a given thread, in a response packet for the peer. This function
supports generating thread IDs when multiprocess mode is enabled (in the
form `p<pid>.<tid>').

Use them in the reply to a '?' request.

Signed-off-by: Luc Michel <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
[PMM: fixed checkpatch blockquote style nit]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7d8c87da79c23b2caa8f68a0a9cd0b15cedf8b41
      
https://github.com/qemu/qemu/commit/7d8c87da79c23b2caa8f68a0a9cd0b15cedf8b41
  Author: Luc Michel <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M gdbstub.c

  Log Message:
  -----------
  gdbstub: add multiprocess support to 'H' and 'T' packets

Add a couple of helper functions to cope with GDB threads and processes.

The gdb_get_process() function looks for a process given a pid.

The gdb_get_cpu() function returns the CPU corresponding to the (pid,
tid) pair given as parameters.

The read_thread_id() function parses the thread-id sent by the peer.
This function supports the multiprocess extension thread-id syntax.  The
return value specifies if the parsing failed, or if a special case was
encountered (all processes or all threads).

Use them in 'H' and 'T' packets handling to support the multiprocess
extension.

Signed-off-by: Luc Michel <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e40e5204af8388e605df2325d9b562c05919350e
      
https://github.com/qemu/qemu/commit/e40e5204af8388e605df2325d9b562c05919350e
  Author: Luc Michel <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M gdbstub.c

  Log Message:
  -----------
  gdbstub: add multiprocess support to vCont packets

Add the gdb_first_attached_cpu() and gdb_next_attached_cpu() to iterate
over all the CPUs in currently attached processes.

Add the gdb_first_cpu_in_process() and gdb_next_cpu_in_process() to
iterate over CPUs of a given process.

Use them to add multiprocess extension support to vCont packets.

Signed-off-by: Luc Michel <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Message-id: address@hidden
[PMM: corrected checkpatch comment style nit]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8dbbe9ac7f9c838d80fdf06b133daa12ffc3f264
      
https://github.com/qemu/qemu/commit/8dbbe9ac7f9c838d80fdf06b133daa12ffc3f264
  Author: Luc Michel <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M gdbstub.c

  Log Message:
  -----------
  gdbstub: add multiprocess support to 'sC' packets

Change the sC packet handling to support the multiprocess extension.
Instead of returning the first thread, we return the first thread of the
current process.

Signed-off-by: Luc Michel <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
[PMM: corrected checkpatch comment style nit]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7cf48f6752e5ab7e10426264a4cf5d7c70f62284
      
https://github.com/qemu/qemu/commit/7cf48f6752e5ab7e10426264a4cf5d7c70f62284
  Author: Luc Michel <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M gdbstub.c

  Log Message:
  -----------
  gdbstub: add multiprocess support to (f|s)ThreadInfo and ThreadExtraInfo

Change the thread info related packets handling to support multiprocess
extension.

Add the CPUs class name in the extra info to help differentiate
them in multiprocess mode.

Signed-off-by: Luc Michel <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c145eeae1cc7bb826fd60056bbd072e3881dc128
      
https://github.com/qemu/qemu/commit/c145eeae1cc7bb826fd60056bbd072e3881dc128
  Author: Luc Michel <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M gdbstub.c

  Log Message:
  -----------
  gdbstub: add multiprocess support to Xfer:features:read:

Change the Xfer:features:read: packet handling to support the
multiprocess extension. This packet is used to request the XML
description of the CPU. In multiprocess mode, different descriptions can
be sent for different processes.

This function now takes the process to send the description for as a
parameter, and use a buffer in the process structure to store the
generated description.

It takes the first CPU of the process to generate the description.

Signed-off-by: Luc Michel <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 95567c27121e58795949c77fd7503ac03451a62b
      
https://github.com/qemu/qemu/commit/95567c27121e58795949c77fd7503ac03451a62b
  Author: Luc Michel <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M gdbstub.c

  Log Message:
  -----------
  gdbstub: add multiprocess support to gdb_vm_state_change()

Add support for multiprocess extension in gdb_vm_state_change()
function.

Signed-off-by: Luc Michel <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 546f3c676c2824a3718a7d74dfb2f663f9348760
      
https://github.com/qemu/qemu/commit/546f3c676c2824a3718a7d74dfb2f663f9348760
  Author: Luc Michel <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M gdbstub.c

  Log Message:
  -----------
  gdbstub: add multiprocess support to 'D' packets

'D' packets are used by GDB to detach from a process. In multiprocess
mode, the PID to detach from is sent in the request.

Signed-off-by: Luc Michel <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 53fd65541511386564fb53a91b594459e7f06d7e
      
https://github.com/qemu/qemu/commit/53fd65541511386564fb53a91b594459e7f06d7e
  Author: Luc Michel <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M gdbstub.c

  Log Message:
  -----------
  gdbstub: add support for extended mode packet

Add support for the '!' extended mode packet. This is required for the
multiprocess extension.

Signed-off-by: Luc Michel <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3f940dc988b8b958ad940a373cd4c1d1b32e503e
      
https://github.com/qemu/qemu/commit/3f940dc988b8b958ad940a373cd4c1d1b32e503e
  Author: Luc Michel <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M gdbstub.c

  Log Message:
  -----------
  gdbstub: add support for vAttach packets

Add support for the vAttach packets. In multiprocess mode, GDB sends
them to attach to additional processes.

Signed-off-by: Luc Michel <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 970ed9064aa9f997fd9e65d707dd5cafc7360703
      
https://github.com/qemu/qemu/commit/970ed9064aa9f997fd9e65d707dd5cafc7360703
  Author: Luc Michel <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M gdbstub.c

  Log Message:
  -----------
  gdbstub: processes initialization on new peer connection

When a new connection is established, we set the first process to be
attached, and the others detached. The first CPU of the first process
is selected as the current CPU.

Signed-off-by: Luc Michel <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 160d858dd6c62c4b523350d89cfa75f212f49b92
      
https://github.com/qemu/qemu/commit/160d858dd6c62c4b523350d89cfa75f212f49b92
  Author: Luc Michel <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M gdbstub.c

  Log Message:
  -----------
  gdbstub: gdb_set_stop_cpu: ignore request when process is not attached

When gdb_set_stop_cpu() is called with a CPU associated to a process
currently not attached by the GDB client, return without modifying the
stop CPU. Otherwise, GDB gets confused if it receives packets with a
thread-id it does not know about.

Signed-off-by: Luc Michel <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
[PMM: fix checkpatch comment style nit]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 364fce6f82b20537a803c6bfb3cf9bab5590f850
      
https://github.com/qemu/qemu/commit/364fce6f82b20537a803c6bfb3cf9bab5590f850
  Author: Luc Michel <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M gdbstub.c

  Log Message:
  -----------
  gdbstub: add multiprocess extension support

Add multiprocess extension support by enabling multiprocess mode when
the peer requests it, and by replying that we actually support it in the
qSupported reply packet.

Signed-off-by: Luc Michel <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 816fd397a116b3a3850bcc4e3f66e15981a4bae8
      
https://github.com/qemu/qemu/commit/816fd397a116b3a3850bcc4e3f66e15981a4bae8
  Author: Luc Michel <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  arm/xlnx-zynqmp: put APUs and RPUs in separate CPU clusters

Create two separate CPU clusters for APUs and RPUs.

Signed-off-by: Luc Michel <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c38c37ac979c54b09293eb11061aa0e534e0f3bf
      
https://github.com/qemu/qemu/commit/c38c37ac979c54b09293eb11061aa0e534e0f3bf
  Author: Stefan Hajnoczi <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M hw/arm/armv7m.c

  Log Message:
  -----------
  Revert "armv7m: Guard against no -kernel argument"

This reverts commit 01fd41ab3fb69971c24a69ed49cde96086d81278.

The generic loader device (-device loader,file=kernel.bin) can be used
to load a kernel instead of the -kernel option.  Some boards have flash
memory (pflash) that is set via the -pflash or -drive options.

Allow starting QEMU without the -kernel option to accommodate these
scenarios.

Suggested-by: Peter Maydell <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: aee63b07fd1c2316d96dff0a6217288a630ce147
      
https://github.com/qemu/qemu/commit/aee63b07fd1c2316d96dff0a6217288a630ce147
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c

  Log Message:
  -----------
  hw/arm: versal: Plug memory leaks

Plug a couple of "board creation time" memory leaks.

Fixes: 6f16da53ffe4567 ("hw/arm: versal: Add a virtual Xilinx Versal board")
Reported-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b7f301141d68be12f074db4ebfc51508f952ea61
      
https://github.com/qemu/qemu/commit/b7f301141d68be12f074db4ebfc51508f952ea61
  Author: Thomas Huth <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add ARM-related files for hw/[misc|input|timer]/

Some of the files in hw/input/, hw/misc/ and hw/timer/ are only
used by one of the ARM machines, so we can assign these files to
the corresponding boards.

Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0ec7e6779fc830e5b4e6a448d75317fafcf69477
      
https://github.com/qemu/qemu/commit/0ec7e6779fc830e5b4e6a448d75317fafcf69477
  Author: Peter Maydell <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M cpus.c

  Log Message:
  -----------
  cpus.c: Fix race condition in cpu_stop_current()

We use cpu_stop_current() to ensure the current CPU has stopped
from places like qemu_system_reset_request(). Unfortunately its
current implementation has a race. It calls qemu_cpu_stop(),
which sets cpu->stopped to true even though the CPU hasn't
actually stopped yet. The main thread will look at the flags
set by qemu_system_reset_request() and call pause_all_vcpus().
pause_all_vcpus() waits for every cpu to have cpu->stopped true,
so it can continue (and we will start the system reset operation)
before the vcpu thread has got back to its top level loop.

Instead, just set cpu->stop and call cpu_exit(). This will
cause the vcpu to exit back to the top level loop, and there
(as part of the wait_io_event code) it will call qemu_cpu_stop().

This fixes bugs where the reset request appeared to be ignored
or the CPU misbehaved because the reset operation started
to change vcpu state while the vcpu thread was still using it.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Emilio G. Cota <address@hidden>
Tested-by: Jaap Crezee <address@hidden>
Message-id: address@hidden


  Commit: ead07aa4ef753f0facd19a7218402f7d19eff60a
      
https://github.com/qemu/qemu/commit/ead07aa4ef753f0facd19a7218402f7d19eff60a
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M hw/arm/allwinner-a10.c
    M include/hw/arm/allwinner-a10.h

  Log Message:
  -----------
  hw/arm/allwinner-a10: Add the 'A' SRAM and the SRAM controller

>From the "A10 User Manual V1.20" p.29: "3.2. Memory Mapping" and:

 7. System Control
  7.1. Overview

  A10 embeds a high-speed SRAM which has been split into five segments.
  See detailed memory mapping in following table:

  Area          Address        Size (Bytes)
   A1    0x00000000-0x00003FFF 16K
   A2    0x00004000-0x00007FFF 16K
   A3    0x00008000-0x0000B3FF 13K
   A4    0x0000B400-0x0000BFFF  3K

Since for emulation purpose we don't need the segmentations, we simply define
the 'A' area as a single 48KB SRAM.

We don't implement the following others areas:
- 'B': 'Secure RAM' (64K),
- 'C': Debug/ISP SRAM
- 'D': USB SRAM

(qemu) info mtree
address-space: memory
  0000000000000000-ffffffffffffffff (prio 0, i/o): system
    0000000000000000-000000000000bfff (prio 0, ram): sram A
    0000000001c00000-0000000001c00fff (prio -1000, i/o): a10-sram-ctrl
    0000000001c0b000-0000000001c0bfff (prio 0, i/o): aw_emac
    0000000001c18000-0000000001c18fff (prio 0, i/o): ahci
      0000000001c18080-0000000001c180ff (prio 0, i/o): allwinner-ahci
    0000000001c20400-0000000001c207ff (prio 0, i/o): allwinner-a10-pic
    0000000001c20c00-0000000001c20fff (prio 0, i/o): allwinner-A10-timer
    0000000001c28000-0000000001c2801f (prio 0, i/o): serial
    0000000040000000-0000000047ffffff (prio 0, ram): cubieboard.ram

Reported-by: Charlie Smurthwaite <address@hidden>
Tested-by: Charlie Smurthwaite <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9813dc6ac3954d58ba16b3920556f106f97e1c67
      
https://github.com/qemu/qemu/commit/9813dc6ac3954d58ba16b3920556f106f97e1c67
  Author: Steffen Görtz <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M qtest.c
    M tests/libqtest.c
    M tests/libqtest.h

  Log Message:
  -----------
  qtest: Add set_irq_in command to set IRQ/GPIO level

Adds a new qtest command "set_irq_in" which allows
to set qemu gpio lines to a given level.

Based on https://lists.gnu.org/archive/html/qemu-devel/2012-12/msg02363.html
which never got merged.

Signed-off-by: Steffen Görtz <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Originally-by: Matthew Ogilvie <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: Laurent Vivier <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 659b85e4133127b342ed191e9d97dc6ad7626113
      
https://github.com/qemu/qemu/commit/659b85e4133127b342ed191e9d97dc6ad7626113
  Author: Steffen Görtz <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M hw/arm/nrf51_soc.c
    A include/hw/arm/nrf51.h
    M include/hw/char/nrf51_uart.h

  Log Message:
  -----------
  arm: Add header to host common definition for nRF51 SOC peripherals

Adds a header that provides definitions that are used
across nRF51 peripherals

Signed-off-by: Steffen Görtz <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 90c58941f6ce05d03364de253902008299d3f9e8
      
https://github.com/qemu/qemu/commit/90c58941f6ce05d03364de253902008299d3f9e8
  Author: Steffen Görtz <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M hw/misc/Makefile.objs
    A hw/misc/nrf51_rng.c
    A include/hw/misc/nrf51_rng.h

  Log Message:
  -----------
  hw/misc/nrf51_rng: Add NRF51 random number generator peripheral

Add a model of the NRF51 random number generator peripheral.
This is a simple random generator that continuously generates
new random values after startup.

Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf

Signed-off-by: Steffen Görtz <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f30890def51f777db1da350f9c737cc75615bdf0
      
https://github.com/qemu/qemu/commit/f30890def51f777db1da350f9c737cc75615bdf0
  Author: Steffen Görtz <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M hw/arm/nrf51_soc.c
    M include/hw/arm/nrf51_soc.h

  Log Message:
  -----------
  arm: Instantiate NRF51 random number generator

Use RNG in SOC.

Signed-off-by: Steffen Görtz <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 805f61bbb33ba24777a854df5d018858502d6d9c
      
https://github.com/qemu/qemu/commit/805f61bbb33ba24777a854df5d018858502d6d9c
  Author: Steffen Görtz <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M Makefile.objs
    M hw/gpio/Makefile.objs
    A hw/gpio/nrf51_gpio.c
    A hw/gpio/trace-events
    A include/hw/gpio/nrf51_gpio.h

  Log Message:
  -----------
  hw/gpio/nrf51_gpio: Add nRF51 GPIO peripheral

This adds a model of the nRF51 GPIO peripheral.

Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf

The nRF51 series microcontrollers support up to 32 GPIO pins in various 
configurations.
The pins can be used as input pins with pull-ups or pull-down.
Furthermore, three different output driver modes per level are
available (disconnected, standard, high-current).

The GPIO-Peripheral has a mechanism for detecting level changes which is
not featured in this model.

Signed-off-by: Steffen Görtz <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bb42c4cb2aad60a5309228c95eda9381f080e50a
      
https://github.com/qemu/qemu/commit/bb42c4cb2aad60a5309228c95eda9381f080e50a
  Author: Steffen Görtz <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M hw/arm/nrf51_soc.c
    M include/hw/arm/nrf51_soc.h

  Log Message:
  -----------
  arm: Instantiate NRF51 general purpose I/O

Instantiates GPIO peripheral model

Signed-off-by: Steffen Görtz <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 17ff8e18cc1a160737d72a0bf3dac2f6372524ea
      
https://github.com/qemu/qemu/commit/17ff8e18cc1a160737d72a0bf3dac2f6372524ea
  Author: Steffen Görtz <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M tests/Makefile.include
    A tests/microbit-test.c

  Log Message:
  -----------
  tests/microbit-test: Add Tests for nRF51 GPIO

The test suite for the nRF51 GPIO peripheral for now
only tests initial state. Additionally a set of
tests testing an implementation detail of the model
are included.

Signed-off-by: Steffen Görtz <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
[PMM: fixed stray space at start of file]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c5a4829c080866c78b6e04b6e8198aa58e185878
      
https://github.com/qemu/qemu/commit/c5a4829c080866c78b6e04b6e8198aa58e185878
  Author: Steffen Görtz <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M hw/timer/Makefile.objs
    A hw/timer/nrf51_timer.c
    M hw/timer/trace-events
    A include/hw/timer/nrf51_timer.h

  Log Message:
  -----------
  hw/timer/nrf51_timer: Add nRF51 Timer peripheral

This patch adds the model for the nRF51 timer peripheral.
Currently, only the TIMER mode is implemented.

Signed-off-by: Steffen Görtz <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 60facd906bb98e3e5e6788341c97b198e87e7762
      
https://github.com/qemu/qemu/commit/60facd906bb98e3e5e6788341c97b198e87e7762
  Author: Steffen Görtz <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M hw/arm/nrf51_soc.c
    M include/hw/arm/nrf51_soc.h

  Log Message:
  -----------
  arm: Instantiate NRF51 Timers

Instantiates TIMER0 - TIMER2

Signed-off-by: Steffen Görtz <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7ec543e4b9d3113f0f7afa49a474d7098abe29f0
      
https://github.com/qemu/qemu/commit/7ec543e4b9d3113f0f7afa49a474d7098abe29f0
  Author: Steffen Görtz <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M tests/microbit-test.c

  Log Message:
  -----------
  tests/microbit-test: Add Tests for nRF51 Timer

Basic tests for nRF51 Timer Peripheral.

Signed-off-by: Steffen Görtz <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b39dced66ac2612e89c9c822b6cb7b63c0de7f43
      
https://github.com/qemu/qemu/commit/b39dced66ac2612e89c9c822b6cb7b63c0de7f43
  Author: Steffen Görtz <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M hw/arm/nrf51_soc.c
    M include/hw/arm/nrf51_soc.h

  Log Message:
  -----------
  arm: Add Clock peripheral stub to NRF51 SOC

This stubs enables the microbit-micropython firmware to run
on the microbit machine.

Signed-off-by: Steffen Görtz <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 96c552958dbb63453b5f02bea6e704006d50e39a
      
https://github.com/qemu/qemu/commit/96c552958dbb63453b5f02bea6e704006d50e39a
  Author: Peter Maydell <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Emit barriers for A32/T32 load-acquire/store-release insns

Now that MTTCG is here, the comment in the 32-bit Arm decoder that
"Since the emulation does not have barriers, the acquire/release
semantics need no special handling" is no longer true. Emit the
correct barriers for the load-acquire/store-release insns, as
we already do in the A64 decoder.

Signed-off-by: Peter Maydell <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>


  Commit: 619d54a8d854e797bf5627843a5e31015deda202
      
https://github.com/qemu/qemu/commit/619d54a8d854e797bf5627843a5e31015deda202
  Author: Peter Maydell <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M hw/misc/tz-mpc.c

  Log Message:
  -----------
  hw/misc/tz-mpc: Fix value of BLK_MAX register

In the TZ Memory Protection Controller, the BLK_MAX register is supposed
to return the maximum permitted value of the BLK_IDX register. Our
implementation incorrectly returned max+1 (ie the total number of
valid index values, since BLK_IDX is zero-based).

Correct this off-by-one error. Since we consistently initialize
and use s->blk_max throughout the implementation as the 'size'
of the LUT, just adjust the value we return when the guest reads
the BLK_MAX register, rather than trying to change the semantics
of the s->blk_max internal struct field.

Fixes: https://bugs.launchpad.net/qemu/+bug/1806824
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: f831f955d420966471f5f8b316ba50d2523b1ff0
      
https://github.com/qemu/qemu/commit/f831f955d420966471f5f8b316ba50d2523b1ff0
  Author: Nick Hudson <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M hw/arm/boot.c
    M hw/core/loader.c
    M hw/core/uboot_image.h
    M hw/microblaze/boot.c
    M hw/nios2/boot.c
    M hw/ppc/e500.c
    M hw/ppc/ppc440_bamboo.c
    M hw/ppc/sam460ex.c
    M include/hw/loader.h

  Log Message:
  -----------
  Support u-boot noload images for arm as used by, NetBSD/evbarm GENERIC kernel.

noload kernels are loaded with the u-boot image header and as a result
the header size needs adding to the entry point.  Fake up a hdr so the
kernel image is loaded at the right address and the entry point is
adjusted appropriately.

The default location for the uboot file is 32MiB above bottom of DRAM.
This matches the recommendation in Documentation/arm/Booting.

Clarify the load_uimage API to state the passing of a load address when an
image doesn't specify one, or when loading a ramdisk is expected.

Adjust callers of load_uimage, etc.

Signed-off-by: Nick Hudson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c102d9471f8f02d9fbea72ec4505d7089173f470
      
https://github.com/qemu/qemu/commit/c102d9471f8f02d9fbea72ec4505d7089173f470
  Author: Peter Maydell <address@hidden>
  Date:   2019-01-07 (Mon, 07 Jan 2019)

  Changed paths:
    M MAINTAINERS
    M Makefile.objs
    M cpus.c
    M gdbstub.c
    M hw/arm/allwinner-a10.c
    M hw/arm/armv7m.c
    M hw/arm/boot.c
    M hw/arm/nrf51_soc.c
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-zynqmp.c
    M hw/core/loader.c
    M hw/core/uboot_image.h
    M hw/cpu/Makefile.objs
    A hw/cpu/cluster.c
    M hw/gpio/Makefile.objs
    A hw/gpio/nrf51_gpio.c
    A hw/gpio/trace-events
    M hw/microblaze/boot.c
    M hw/misc/Makefile.objs
    A hw/misc/nrf51_rng.c
    M hw/misc/tz-mpc.c
    M hw/nios2/boot.c
    M hw/ppc/e500.c
    M hw/ppc/ppc440_bamboo.c
    M hw/ppc/sam460ex.c
    M hw/timer/Makefile.objs
    A hw/timer/nrf51_timer.c
    M hw/timer/trace-events
    M include/hw/arm/allwinner-a10.h
    A include/hw/arm/nrf51.h
    M include/hw/arm/nrf51_soc.h
    M include/hw/arm/xlnx-zynqmp.h
    M include/hw/char/nrf51_uart.h
    A include/hw/cpu/cluster.h
    A include/hw/gpio/nrf51_gpio.h
    M include/hw/loader.h
    A include/hw/misc/nrf51_rng.h
    A include/hw/timer/nrf51_timer.h
    M qtest.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/sve.decode
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M tests/Makefile.include
    M tests/libqtest.c
    M tests/libqtest.h
    A tests/microbit-test.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20190107' 
into staging

target-arm queue:
 * Support u-boot 'noload' images for Arm (as used by NetBSD/evbarm GENERIC 
kernel)
 * hw/misc/tz-mpc: Fix value of BLK_MAX register
 * target/arm: Emit barriers for A32/T32 load-acquire/store-release insns
 * nRF51 SoC: add timer, GPIO, RNG peripherals
 * hw/arm/allwinner-a10: Add the 'A' SRAM and the SRAM controller
 * cpus.c: Fix race condition in cpu_stop_current()
 * hw/arm: versal: Plug memory leaks
 * Allow M profile boards to run even if -kernel not specified
 * gdbstub: Add multiprocess extension support for use when the
   board has multiple CPUs of different types (like the Xilinx Zynq boards)
 * target/arm: Don't decode S bit in SVE brk[ab] merging insns
 * target/arm: Convert ARM_TBFLAG_* to FIELDs

# gpg: Signature made Mon 07 Jan 2019 16:29:52 GMT
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20190107: (37 commits)
  Support u-boot noload images for arm as used by, NetBSD/evbarm GENERIC kernel.
  hw/misc/tz-mpc: Fix value of BLK_MAX register
  target/arm: Emit barriers for A32/T32 load-acquire/store-release insns
  arm: Add Clock peripheral stub to NRF51 SOC
  tests/microbit-test: Add Tests for nRF51 Timer
  arm: Instantiate NRF51 Timers
  hw/timer/nrf51_timer: Add nRF51 Timer peripheral
  tests/microbit-test: Add Tests for nRF51 GPIO
  arm: Instantiate NRF51 general purpose I/O
  hw/gpio/nrf51_gpio: Add nRF51 GPIO peripheral
  arm: Instantiate NRF51 random number generator
  hw/misc/nrf51_rng: Add NRF51 random number generator peripheral
  arm: Add header to host common definition for nRF51 SOC peripherals
  qtest: Add set_irq_in command to set IRQ/GPIO level
  hw/arm/allwinner-a10: Add the 'A' SRAM and the SRAM controller
  cpus.c: Fix race condition in cpu_stop_current()
  MAINTAINERS: Add ARM-related files for hw/[misc|input|timer]/
  hw/arm: versal: Plug memory leaks
  Revert "armv7m: Guard against no -kernel argument"
  arm/xlnx-zynqmp: put APUs and RPUs in separate CPU clusters
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/31ed41889e6e...c102d9471f8f
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