[Qemu-commits] [qemu/qemu] f6c98f: target/arm: Remove can't-happen if() from handle_v...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: f6c98f91f56031141a47f86225fdc30f0f9f84fb
      
https://github.com/qemu/qemu/commit/f6c98f91f56031141a47f86225fdc30f0f9f84fb
  Author: Peter Maydell <address@hidden>
  Date:   2018-11-06 (Tue, 06 Nov 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Remove can't-happen if() from handle_vec_simd_shli()

In handle_vec_simd_shli() we have a check:
     if (size > 3 && !is_q) {
   unallocated_encoding(s);
   return;
     }
However this can never be true, because we calculate
    int size = 32 - clz32(immh) - 1;
where immh is a 4 bit field which we know cannot be all-zeroes.
So the clz32() return must be in {28,29,30,31} and the resulting
size is in {0,1,2,3}, and "size > 3" is never true.

This unnecessary code confuses Coverity's analysis:
in CID 1396476 it thinks we might later index off the
end of an array because the condition implies that we
might have a size > 3.

Remove the code, and instead assert that the size is in [0..3],
since the decode that enforces that is somewhat distant from
this function.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: 40af11eb7f80aac6c45d75e4fa6fa71ff930c651
      
https://github.com/qemu/qemu/commit/40af11eb7f80aac6c45d75e4fa6fa71ff930c651
  Author: Peter Maydell <address@hidden>
  Date:   2018-11-06 (Tue, 06 Nov 2018)

  Changed paths:
    M hw/lm32/milkymist.c

  Log Message:
  -----------
  milkymist: Check for failure trying to load BIOS image

Check the return value from load_image_targphys(), which tells us
whether our attempt to load the BIOS image into RAM failed.
(Spotted by Coverity, CID 1190305.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Acked-by: Michael Walle <address@hidden>
Message-id: address@hidden


  Commit: 76a82ced1184f26c1e2426938241442d80b1c13e
      
https://github.com/qemu/qemu/commit/76a82ced1184f26c1e2426938241442d80b1c13e
  Author: Peter Maydell <address@hidden>
  Date:   2018-11-06 (Tue, 06 Nov 2018)

  Changed paths:
    M hw/arm/exynos4210.c

  Log Message:
  -----------
  hw/arm/exynos4210: Zero memory allocated for Exynos4210State

In exynos4210_init() we allocate memory for an Exynos4210State
struct. Generally devices can assume that the memory allocated
for their state struct is zero-initialized; we broke that
assumption here by using g_new(). Use g_new0() instead.
(In particular, some code assumes that the various irq arrays
in the Exynos4210Irq sub-struct are zero-initialized.)

In the longer term, this code should be QOMified, and then
the struct memory will be allocated elsewhere and by functions
which always zero-initalize it; but for 3.1 this is a
simple fix.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: 0f7b791b35f24cb1333f779705a3f6472e6935de
      
https://github.com/qemu/qemu/commit/0f7b791b35f24cb1333f779705a3f6472e6935de
  Author: Peter Maydell <address@hidden>
  Date:   2018-11-06 (Tue, 06 Nov 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Set S and PTW in 64-bit PAR format

In do_ats_write() we construct a PAR value based on the result
of the translation.  A comment says "S2WLK and FSTAGE are always
zero, because we don't implement virtualization".
Since we do in fact now implement virtualization, add the missing
code that sets these bits based on the reported ARMMMUFaultInfo.

(These bits are named PTW and S in ARMv8, so we follow that
convention in the new comments in this patch.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: 23463e0e4aeb2f0a9c60549a2c163f4adc0b8512
      
https://github.com/qemu/qemu/commit/23463e0e4aeb2f0a9c60549a2c163f4adc0b8512
  Author: Peter Maydell <address@hidden>
  Date:   2018-11-06 (Tue, 06 Nov 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Fix ATS1Hx instructions

ATS1HR and ATS1HW (which allow AArch32 EL2 to do address translations
on the EL2 translation regime) were implemented in commit 14db7fe09a2c8.
However, we got them wrong: these should do stage 1 address translations
as defined for NS-EL2, which is ARMMMUIdx_S1E2. We were incorrectly
making them perform stage 2 translations.

A few years later in commit 1313e2d7e2cd we forgot entirely that
we'd implemented ATS1Hx, and added a comment that ATS1Hx were
"not supported yet". Remove the comment; there is no extra code
needed to handle these operations in do_ats_write(), because
arm_s1_regime_using_lpae_format() returns true for ARMMMUIdx_S1E2,
which forces 64-bit PAR format.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Reviewed-by: Edgar E. Iglesias <address@hidden>


  Commit: 9aca866699d1173131f780cd62846d623cba28ff
      
https://github.com/qemu/qemu/commit/9aca866699d1173131f780cd62846d623cba28ff
  Author: Peter Maydell <address@hidden>
  Date:   2018-11-06 (Tue, 06 Nov 2018)

  Changed paths:
    M hw/arm/exynos4210.c
    M hw/lm32/milkymist.c
    M target/arm/helper.c
    M target/arm/translate-a64.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20181106' 
into staging

target-arm queue:
 * Remove can't-happen if() from handle_vec_simd_shli()
 * hw/arm/exynos4210: Zero memory allocated for Exynos4210State
 * Set S and PTW in 64-bit PAR format
 * Fix ATS1Hx instructions
 * milkymist: Check for failure trying to load BIOS image

# gpg: Signature made Tue 06 Nov 2018 11:37:30 GMT
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20181106:
  target/arm: Fix ATS1Hx instructions
  target/arm: Set S and PTW in 64-bit PAR format
  hw/arm/exynos4210: Zero memory allocated for Exynos4210State
  milkymist: Check for failure trying to load BIOS image
  target/arm: Remove can't-happen if() from handle_vec_simd_shli()

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/b66db50f6720...9aca866699d1
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