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[Qemu-commits] [qemu/qemu] 438c78: tests: Move tests/acpi-test-data/ to
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[Qemu-commits] [qemu/qemu] 438c78: tests: Move tests/acpi-test-data/ to tests/data/ac... |
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Tue, 06 Nov 2018 04:39:18 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 438c78dab75e3b9d1bc8da1d5401da77c84e27b7
https://github.com/qemu/qemu/commit/438c78dab75e3b9d1bc8da1d5401da77c84e27b7
Author: Peter Maydell <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M configure
R tests/acpi-test-data/pc/APIC
R tests/acpi-test-data/pc/APIC.cphp
R tests/acpi-test-data/pc/APIC.dimmpxm
R tests/acpi-test-data/pc/DSDT
R tests/acpi-test-data/pc/DSDT.bridge
R tests/acpi-test-data/pc/DSDT.cphp
R tests/acpi-test-data/pc/DSDT.dimmpxm
R tests/acpi-test-data/pc/DSDT.ipmikcs
R tests/acpi-test-data/pc/DSDT.memhp
R tests/acpi-test-data/pc/DSDT.numamem
R tests/acpi-test-data/pc/FACP
R tests/acpi-test-data/pc/FACS
R tests/acpi-test-data/pc/HPET
R tests/acpi-test-data/pc/NFIT.dimmpxm
R tests/acpi-test-data/pc/SLIT.cphp
R tests/acpi-test-data/pc/SLIT.memhp
R tests/acpi-test-data/pc/SRAT.cphp
R tests/acpi-test-data/pc/SRAT.dimmpxm
R tests/acpi-test-data/pc/SRAT.memhp
R tests/acpi-test-data/pc/SRAT.numamem
R tests/acpi-test-data/pc/SSDT.dimmpxm
R tests/acpi-test-data/q35/APIC
R tests/acpi-test-data/q35/APIC.cphp
R tests/acpi-test-data/q35/APIC.dimmpxm
R tests/acpi-test-data/q35/DSDT
R tests/acpi-test-data/q35/DSDT.bridge
R tests/acpi-test-data/q35/DSDT.cphp
R tests/acpi-test-data/q35/DSDT.dimmpxm
R tests/acpi-test-data/q35/DSDT.ipmibt
R tests/acpi-test-data/q35/DSDT.memhp
R tests/acpi-test-data/q35/DSDT.numamem
R tests/acpi-test-data/q35/FACP
R tests/acpi-test-data/q35/FACS
R tests/acpi-test-data/q35/HPET
R tests/acpi-test-data/q35/MCFG
R tests/acpi-test-data/q35/NFIT.dimmpxm
R tests/acpi-test-data/q35/SLIT.cphp
R tests/acpi-test-data/q35/SLIT.memhp
R tests/acpi-test-data/q35/SRAT.cphp
R tests/acpi-test-data/q35/SRAT.dimmpxm
R tests/acpi-test-data/q35/SRAT.memhp
R tests/acpi-test-data/q35/SRAT.numamem
R tests/acpi-test-data/q35/SSDT.dimmpxm
R tests/acpi-test-data/rebuild-expected-aml.sh
M tests/bios-tables-test.c
A tests/data/acpi/pc/APIC
A tests/data/acpi/pc/APIC.cphp
A tests/data/acpi/pc/APIC.dimmpxm
A tests/data/acpi/pc/DSDT
A tests/data/acpi/pc/DSDT.bridge
A tests/data/acpi/pc/DSDT.cphp
A tests/data/acpi/pc/DSDT.dimmpxm
A tests/data/acpi/pc/DSDT.ipmikcs
A tests/data/acpi/pc/DSDT.memhp
A tests/data/acpi/pc/DSDT.numamem
A tests/data/acpi/pc/FACP
A tests/data/acpi/pc/FACS
A tests/data/acpi/pc/HPET
A tests/data/acpi/pc/NFIT.dimmpxm
A tests/data/acpi/pc/SLIT.cphp
A tests/data/acpi/pc/SLIT.memhp
A tests/data/acpi/pc/SRAT.cphp
A tests/data/acpi/pc/SRAT.dimmpxm
A tests/data/acpi/pc/SRAT.memhp
A tests/data/acpi/pc/SRAT.numamem
A tests/data/acpi/pc/SSDT.dimmpxm
A tests/data/acpi/q35/APIC
A tests/data/acpi/q35/APIC.cphp
A tests/data/acpi/q35/APIC.dimmpxm
A tests/data/acpi/q35/DSDT
A tests/data/acpi/q35/DSDT.bridge
A tests/data/acpi/q35/DSDT.cphp
A tests/data/acpi/q35/DSDT.dimmpxm
A tests/data/acpi/q35/DSDT.ipmibt
A tests/data/acpi/q35/DSDT.memhp
A tests/data/acpi/q35/DSDT.numamem
A tests/data/acpi/q35/FACP
A tests/data/acpi/q35/FACS
A tests/data/acpi/q35/HPET
A tests/data/acpi/q35/MCFG
A tests/data/acpi/q35/NFIT.dimmpxm
A tests/data/acpi/q35/SLIT.cphp
A tests/data/acpi/q35/SLIT.memhp
A tests/data/acpi/q35/SRAT.cphp
A tests/data/acpi/q35/SRAT.dimmpxm
A tests/data/acpi/q35/SRAT.memhp
A tests/data/acpi/q35/SRAT.numamem
A tests/data/acpi/q35/SSDT.dimmpxm
A tests/data/acpi/rebuild-expected-aml.sh
Log Message:
-----------
tests: Move tests/acpi-test-data/ to tests/data/acpi/
Currently tests/acpi-test-data contains data files used by the
bios-tables-test, and configure individually symlinks those
data files into the build directory using a wildcard.
Using a wildcard like this is a bad idea, because if a new
data file is added, nothing causes configure to be rerun,
and so no symlink is added for the new file. This can cause
tests to spuriously fail when they can't find their data.
Instead, it's better to symlink an entire directory of
data files. We already have such a directory: tests/data.
Move the data files from tests/acpi-test-data/ to
tests/data/acpi/, and remove the unnecessary symlinking.
We can remove entirely the note in rebuild-expected-aml.sh
about copying any new data files, because now they will
be in the source directory, not the build directory, and
no copying is required.
(We can't just change the existing tests/acpi-test-data/
to being a symlinked directory, because if we did that and
a developer switched git branches from one after that change
to one before it then configure would end up trashing all
the test files by making them symlinks to themselves.
Changing their path avoids this annoyance.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 4b2ff65a1f33b6130bfd92a8aaf6289909af9d35
https://github.com/qemu/qemu/commit/4b2ff65a1f33b6130bfd92a8aaf6289909af9d35
Author: Peter Maydell <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M MAINTAINERS
M configure
A tests/data/hex-loader/test.hex
R tests/hex-loader-check-data/test.hex
M tests/hexloader-test.c
Log Message:
-----------
tests: Move tests/hex-loader-check-data/ to tests/data/hex-loader/
Currently tests/hex-loader-check-data contains data files used
by the hexloader-test, and configure individually symlinks those
data files into the build directory using a wildcard.
Using a wildcard like this is a bad idea, because if a new
data file is added, nothing causes configure to be rerun,
and so no symlink is added for the new file. This can cause
tests to spuriously fail when they can't find their data.
Instead, it's better to symlink an entire directory of
data files. We already have such a directory: tests/data.
Move the data files from tests/hex-loader-check-data/ to
tests/data/hex-loader/, and remove the unnecessary symlinking.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: e29e5c6ee0b2770912dfea6a05926352ff30171d
https://github.com/qemu/qemu/commit/e29e5c6ee0b2770912dfea6a05926352ff30171d
Author: Peter Maydell <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M configure
Log Message:
-----------
configure: Rename FILES variable to LINKS
The FILES variable is used to accumulate a list of things to symlink
from the source tree into the build tree. These don't have to be
individual files; symlinking an entire directory of data files is
also fine. Rename it to something less confusing before we add a few
directories to it.
Improve the comment to clarify what DIRS and LINKS do and why
it's not a good idea to add things to LINKS with wildcarding.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 39950353959932320763c9ef27fb4ff0b774fe0c
https://github.com/qemu/qemu/commit/39950353959932320763c9ef27fb4ff0b774fe0c
Author: Peter Maydell <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M configure
Log Message:
-----------
configure: Use LINKS loop for all build tree symlinks
A few places in configure were doing ad-hoc calls to
the symlink function to set up symlinks from the build tree
back to the source tree. We have a loop that does this
already for all files and directories listed in the LINKS
environment variable; use that instead.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 9bb192a4fca3e50194b6ac2e0eaaee20d996bba1
https://github.com/qemu/qemu/commit/9bb192a4fca3e50194b6ac2e0eaaee20d996bba1
Author: Yaowei Bai <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/block/virtio-blk.c
Log Message:
-----------
virtio-blk: fix comment for virtio_blk_rw_complete
Here should be submit_requests, there is no submit_merged_requests
function.
Signed-off-by: Yaowei Bai <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 06aba4ca52fd2c8718b8ba486f22f0aa7c99ed55
https://github.com/qemu/qemu/commit/06aba4ca52fd2c8718b8ba486f22f0aa7c99ed55
Author: Peter Xu <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel_iommu: introduce vtd_reset_caches()
Provide the function and use it in vtd_init(). Used to reset both
context entry cache and iotlb cache for the whole IOMMU unit.
Signed-off-by: Peter Xu <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Reviewed-by: Jason Wang <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 2cc9ddccebcaa48b3debfc279a83761fcbb7616c
https://github.com/qemu/qemu/commit/2cc9ddccebcaa48b3debfc279a83761fcbb7616c
Author: Peter Xu <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel_iommu: better handling of dmar state switch
QEMU is not handling the global DMAR switch well, especially when from
"on" to "off".
Let's first take the example of system reset.
Assuming that a guest has IOMMU enabled. When it reboots, we will drop
all the existing DMAR mappings to handle the system reset, however we'll
still keep the existing memory layouts which has the IOMMU memory region
enabled. So after the reboot and before the kernel reloads again, there
will be no mapping at all for the host device. That's problematic since
any software (for example, SeaBIOS) that runs earlier than the kernel
after the reboot will assume the IOMMU is disabled, so any DMA from the
software will fail.
For example, a guest that boots on an assigned NVMe device might fail to
find the boot device after a system reboot/reset and we'll be able to
observe SeaBIOS errors if we capture the debugging log:
WARNING - Timeout at nvme_wait:144!
Meanwhile, we should see DMAR errors on the host of that NVMe device.
It's the DMA fault that caused a NVMe driver timeout.
The correct fix should be that we do proper switching of device DMA
address spaces when system resets, which will setup correct memory
regions and notify the backend of the devices. This might not affect
much on non-assigned devices since QEMU VT-d emulation will assume a
default passthrough mapping if DMAR is not enabled in the GCMD
register (please refer to vtd_iommu_translate). However that's required
for an assigned devices, since that'll rebuild the correct GPA to HPA
mapping that is needed for any DMA operation during guest bootstrap.
Besides the system reset, we have some other places that might change
the global DMAR status and we'd better do the same thing there. For
example, when we change the state of GCMD register, or the DMAR root
pointer. Do the same refresh for all these places. For these two
places we'll also need to explicitly invalidate the context entry cache
and iotlb cache.
Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1625173
CC: QEMU Stable <address@hidden>
Reported-by: Cong Li <address@hidden>
Signed-off-by: Peter Xu <address@hidden>
--
v2:
- do the same for GCMD write, or root pointer update [Alex]
- test is carried out by me this time, by observing the
vtd_switch_address_space tracepoint after system reboot
v3:
- rewrite commit message as suggested by Alex
Signed-off-by: Peter Xu <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Reviewed-by: Jason Wang <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 95ecd3df7815b4bc4f9a0f47e1c64d81434715aa
https://github.com/qemu/qemu/commit/95ecd3df7815b4bc4f9a0f47e1c64d81434715aa
Author: Peter Xu <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel_iommu: move ce fetching out when sync shadow
There are two callers for vtd_sync_shadow_page_table_range(): one
provided a valid context entry and one not. Move that fetching
operation into the caller vtd_sync_shadow_page_table() where we need to
fetch the context entry.
Meanwhile, remove the error_report_once() directly since we're already
tracing all the error cases in the previous call. Instead, return error
number back to caller. This will not change anything functional since
callers are dropping it after all.
We do this move majorly because we want to do something more later in
vtd_sync_shadow_page_table().
Signed-off-by: Peter Xu <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Reviewed-by: Maxime Coquelin <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: c28b535d083d0a263d38d9ceeada83cdae8c64f0
https://github.com/qemu/qemu/commit/c28b535d083d0a263d38d9ceeada83cdae8c64f0
Author: Peter Xu <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel_iommu: handle invalid ce for shadow sync
We should handle VTD_FR_CONTEXT_ENTRY_P properly when synchronizing
shadow page tables. Having invalid context entry there is perfectly
valid when we move a device out of an existing domain. When that
happens, instead of posting an error we invalidate the whole region.
Without this patch, QEMU will crash if we do these steps:
(1) start QEMU with VT-d IOMMU and two 10G NICs (ixgbe)
(2) bind the NICs with vfio-pci in the guest
(3) start testpmd with the NICs applied
(4) stop testpmd
(5) rebind the NIC back to ixgbe kernel driver
The patch should fix it.
Reported-by: Pei Zhang <address@hidden>
Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1627272
Signed-off-by: Peter Xu <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Reviewed-by: Maxime Coquelin <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 110b9463d5c820120c8311db79f55a64c9d81ebe
https://github.com/qemu/qemu/commit/110b9463d5c820120c8311db79f55a64c9d81ebe
Author: Yongji Xie <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/block/vhost-user-blk.c
Log Message:
-----------
vhost-user-blk: start vhost when guest kicks
Some old guests (before commit 7a11370e5: "virtio_blk: enable VQs early")
kick virtqueue before setting VIRTIO_CONFIG_S_DRIVER_OK. This violates
the virtio spec. But virtio 1.0 transitional devices support this behaviour.
So we should start vhost when guest kicks in this case.
Signed-off-by: Yongji Xie <address@hidden>
Signed-off-by: Chai Wen <address@hidden>
Signed-off-by: Ni Xun <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 50662ce16da37479533e7ae9f515d4e9d49b9d14
https://github.com/qemu/qemu/commit/50662ce16da37479533e7ae9f515d4e9d49b9d14
Author: Singh, Brijesh <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/x86-iommu.c
Log Message:
-----------
x86_iommu: move the kernel-irqchip check in common code
Interrupt remapping needs kernel-irqchip={off|split} on both Intel and AMD
platforms. Move the check in common place.
Signed-off-by: Brijesh Singh <address@hidden>
Reviewed-by: Peter Xu <address@hidden>
Cc: Peter Xu <address@hidden>
Cc: "Michael S. Tsirkin" <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Richard Henderson <address@hidden>
Cc: Eduardo Habkost <address@hidden>
Cc: Marcel Apfelbaum <address@hidden>
Cc: Tom Lendacky <address@hidden>
Cc: Suravee Suthikulpanit <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 35c2450191634bd0ac0ae3c6e9da3f590124e8e2
https://github.com/qemu/qemu/commit/35c2450191634bd0ac0ae3c6e9da3f590124e8e2
Author: Singh, Brijesh <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/x86-iommu.c
M include/hw/i386/intel_iommu.h
M include/hw/i386/x86-iommu.h
Log Message:
-----------
x86_iommu: move vtd_generate_msi_message in common file
The vtd_generate_msi_message() in intel-iommu is used to construct a MSI
Message from IRQ. A similar function will be needed when we add interrupt
remapping support in amd-iommu. Moving the function in common file to
avoid the code duplication. Rename it to x86_iommu_irq_to_msi_message().
There is no logic changes in the code flow.
Signed-off-by: Brijesh Singh <address@hidden>
Suggested-by: Peter Xu <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Cc: Peter Xu <address@hidden>
Cc: "Michael S. Tsirkin" <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Richard Henderson <address@hidden>
Cc: Eduardo Habkost <address@hidden>
Cc: Marcel Apfelbaum <address@hidden>
Cc: Tom Lendacky <address@hidden>
Cc: Suravee Suthikulpanit <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 470506b5821c62d6b00d0dd82eea999b61c3719e
https://github.com/qemu/qemu/commit/470506b5821c62d6b00d0dd82eea999b61c3719e
Author: Singh, Brijesh <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/i386/amd_iommu.c
Log Message:
-----------
x86_iommu/amd: remove V=1 check from amdvi_validate_dte()
Currently, the amdvi_validate_dte() assumes that a valid DTE will
always have V=1. This is not true. The V=1 means that bit[127:1] are
valid. A valid DTE can have IV=1 and V=0 (i.e address translation
disabled and interrupt remapping enabled)
Remove the V=1 check from amdvi_validate_dte(), make the caller
responsible to check for V or IV bits.
This also fixes a bug in existing code that when error is
detected during the translation we'll fail the translation
instead of assuming a passthrough mode.
Signed-off-by: Brijesh Singh <address@hidden>
Reviewed-by: Peter Xu <address@hidden>
Cc: Peter Xu <address@hidden>
Cc: "Michael S. Tsirkin" <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Richard Henderson <address@hidden>
Cc: Eduardo Habkost <address@hidden>
Cc: Marcel Apfelbaum <address@hidden>
Cc: Tom Lendacky <address@hidden>
Cc: Suravee Suthikulpanit <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 53244386b0674dc91ae2987c77a95e82476bb6f7
https://github.com/qemu/qemu/commit/53244386b0674dc91ae2987c77a95e82476bb6f7
Author: Singh, Brijesh <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/i386/amd_iommu.c
Log Message:
-----------
x86_iommu/amd: make the address space naming consistent with intel-iommu
To be consistent with intel-iommu:
- rename the address space to use '_' instead of '-'
- update the memory region relationships
Signed-off-by: Brijesh Singh <address@hidden>
Reviewed-by: Peter Xu <address@hidden>
Cc: Peter Xu <address@hidden>
Cc: "Michael S. Tsirkin" <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Richard Henderson <address@hidden>
Cc: Eduardo Habkost <address@hidden>
Cc: Marcel Apfelbaum <address@hidden>
Cc: Tom Lendacky <address@hidden>
Cc: Suravee Suthikulpanit <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 577c470f4326eae22e4e412946b167075f4440d2
https://github.com/qemu/qemu/commit/577c470f4326eae22e4e412946b167075f4440d2
Author: Singh, Brijesh <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/i386/amd_iommu.c
M hw/i386/amd_iommu.h
M hw/i386/trace-events
Log Message:
-----------
x86_iommu/amd: Prepare for interrupt remap support
Register the interrupt remapping callback and read/write ops for the
amd-iommu-ir memory region.
amd-iommu-ir is set to higher priority to ensure that this region won't
be masked out by other memory regions.
Signed-off-by: Brijesh Singh <address@hidden>
Cc: Peter Xu <address@hidden>
Cc: "Michael S. Tsirkin" <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Richard Henderson <address@hidden>
Cc: Eduardo Habkost <address@hidden>
Cc: Marcel Apfelbaum <address@hidden>
Cc: Tom Lendacky <address@hidden>
Cc: Suravee Suthikulpanit <address@hidden>
Reviewed-by: Peter Xu <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: b44159fe00784f67f766ba1bf6eec14f3c709806
https://github.com/qemu/qemu/commit/b44159fe00784f67f766ba1bf6eec14f3c709806
Author: Singh, Brijesh <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/i386/amd_iommu.c
M hw/i386/amd_iommu.h
M hw/i386/trace-events
Log Message:
-----------
x86_iommu/amd: Add interrupt remap support when VAPIC is not enabled
Emulate the interrupt remapping support when guest virtual APIC is
not enabled.
For more info Refer: AMD IOMMU spec Rev 3.0 - section 2.2.5.1
When VAPIC is not enabled, it uses interrupt remapping as defined in
Table 20 and Figure 15 from IOMMU spec.
Signed-off-by: Brijesh Singh <address@hidden>
Cc: Peter Xu <address@hidden>
Cc: "Michael S. Tsirkin" <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Richard Henderson <address@hidden>
Cc: Eduardo Habkost <address@hidden>
Cc: Marcel Apfelbaum <address@hidden>
Cc: Tom Lendacky <address@hidden>
Cc: Suravee Suthikulpanit <address@hidden>
Reviewed-by: Peter Xu <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: c028818d573ab3d86ed916a70359fedb2d24a8ad
https://github.com/qemu/qemu/commit/c028818d573ab3d86ed916a70359fedb2d24a8ad
Author: Singh, Brijesh <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/i386/acpi-build.c
Log Message:
-----------
i386: acpi: add IVHD device entry for IOAPIC
When interrupt remapping is enabled, add a special IVHD device
(type IOAPIC).
Signed-off-by: Brijesh Singh <address@hidden>
Acked-by: Peter Xu <address@hidden>
Cc: Peter Xu <address@hidden>
Cc: "Michael S. Tsirkin" <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Richard Henderson <address@hidden>
Cc: Eduardo Habkost <address@hidden>
Cc: Marcel Apfelbaum <address@hidden>
Cc: Tom Lendacky <address@hidden>
Cc: Suravee Suthikulpanit <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 135f866e609c2ddbd0f352e8e0fee8dfb5d56c3e
https://github.com/qemu/qemu/commit/135f866e609c2ddbd0f352e8e0fee8dfb5d56c3e
Author: Singh, Brijesh <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/i386/amd_iommu.c
M hw/i386/amd_iommu.h
M hw/i386/trace-events
Log Message:
-----------
x86_iommu/amd: Add interrupt remap support when VAPIC is enabled
Emulate the interrupt remapping support when guest virtual APIC is
enabled.
For more information refer: IOMMU spec rev 3.0 (section 2.2.5.2)
When VAPIC is enabled, it uses interrupt remapping as defined in
Table 22 and Figure 17 from IOMMU spec.
Signed-off-by: Brijesh Singh <address@hidden>
Reviewed-by: Peter Xu <address@hidden>
Cc: Peter Xu <address@hidden>
Cc: "Michael S. Tsirkin" <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Richard Henderson <address@hidden>
Cc: Eduardo Habkost <address@hidden>
Cc: Marcel Apfelbaum <address@hidden>
Cc: Tom Lendacky <address@hidden>
Cc: Suravee Suthikulpanit <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 12499b23315bac605516986f4de4fc55ddfaca78
https://github.com/qemu/qemu/commit/12499b23315bac605516986f4de4fc55ddfaca78
Author: Singh, Brijesh <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/i386/acpi-build.c
M hw/i386/amd_iommu.h
Log Message:
-----------
x86_iommu/amd: Enable Guest virtual APIC support
Now that amd-iommu support interrupt remapping, enable the GASup in IVRS
table and GASup in extended feature register to indicate that IOMMU
support guest virtual APIC mode. GASup provides option to guest OS to
make use of 128-bit IRTE.
Note that the GAMSup is set to zero to indicate that amd-iommu does not
support guest virtual APIC mode (aka AVIC) which would be used for the
nested VMs.
See Table 21 from IOMMU spec for interrupt virtualization controls
Signed-off-by: Brijesh Singh <address@hidden>
Reviewed-by: Peter Xu <address@hidden>
Cc: Peter Xu <address@hidden>
Cc: "Michael S. Tsirkin" <address@hidden>
Cc: Paolo Bonzini <address@hidden>
Cc: Richard Henderson <address@hidden>
Cc: Eduardo Habkost <address@hidden>
Cc: Marcel Apfelbaum <address@hidden>
Cc: Tom Lendacky <address@hidden>
Cc: Suravee Suthikulpanit <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 7115dcf4f19e1d590aec7afe315095af9491dad6
https://github.com/qemu/qemu/commit/7115dcf4f19e1d590aec7afe315095af9491dad6
Author: Laszlo Ersek <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: list "tests/acpi-test-data" files in ACPI/SMBIOS section
The "tests/acpi-test-data" files are currently not covered by any section
in MAINTAINERS, and "scripts/checkpatch.pl" complains when new data files
are added.
Cc: "Michael S. Tsirkin" <address@hidden>
Cc: Alex Williamson <address@hidden>
Cc: Gerd Hoffmann <address@hidden>
Cc: Igor Mammedov <address@hidden>
Cc: Marcel Apfelbaum <address@hidden>
Signed-off-by: Laszlo Ersek <address@hidden>
Reviewed-by: Marcel Apfelbaum <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 417463341e3e35c9be80f54b0d6ae8cfdb4b0d84
https://github.com/qemu/qemu/commit/417463341e3e35c9be80f54b0d6ae8cfdb4b0d84
Author: Gerd Hoffmann <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M docs/specs/pci-testdev.txt
M hw/misc/pci-testdev.c
Log Message:
-----------
pci-testdev: add optional memory bar
Add memory bar to pci-testdev. Size is configurable using the membar
property. Setting the size to zero (default) turns it off. Can be used
to check whether guests handle large pci bars correctly.
Reviewed-by: Marc-André Lureau <address@hidden>
Reviewed-by: Laszlo Ersek <address@hidden>
Tested-by: Laszlo Ersek <address@hidden>
Signed-off-by: Gerd Hoffmann <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: ccef5b1fcf1ca33976583c88489a55d6acd13b78
https://github.com/qemu/qemu/commit/ccef5b1fcf1ca33976583c88489a55d6acd13b78
Author: Laszlo Ersek <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/pci-host/piix.c
M hw/pci-host/q35.c
Log Message:
-----------
hw/pci-host/x86: extract get_pci_hole64_start_value() helpers
Expose the calculated "hole64 start" GPAs as plain uint64_t values,
extracting the internals of the current property getters.
This patch doesn't change behavior.
Cc: "Michael S. Tsirkin" <address@hidden>
Cc: Alex Williamson <address@hidden>
Cc: Gerd Hoffmann <address@hidden>
Cc: Igor Mammedov <address@hidden>
Cc: Marcel Apfelbaum <address@hidden>
Signed-off-by: Laszlo Ersek <address@hidden>
Reviewed-by: Marcel Apfelbaum <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: ed6bb4b581050fe27aba80d6937138adf883d41e
https://github.com/qemu/qemu/commit/ed6bb4b581050fe27aba80d6937138adf883d41e
Author: Laszlo Ersek <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/pci-host/piix.c
M hw/pci-host/q35.c
Log Message:
-----------
hw/pci-host/x86: extend the 64-bit PCI hole relative to the fw-assigned base
In commit 9fa99d2519cb ("hw/pci-host: Fix x86 Host Bridges 64bit PCI
hole", 2017-11-16), we meant to expose such a 64-bit PCI MMIO aperture in
the ACPI DSDT that would be at least as large as the new "pci-hole64-size"
property (2GB on i440fx, 32GB on q35). The goal was to offer "enough"
64-bit MMIO aperture to the guest OS for hotplug purposes.
In that commit, we added or modified five functions:
- pc_pci_hole64_start(): shared between i440fx and q35. Provides a default
64-bit base, which starts beyond the cold-plugged 64-bit RAM, and skips
the DIMM hotplug area too (if any).
- i440fx_pcihost_get_pci_hole64_start(), q35_host_get_pci_hole64_start():
board-specific 64-bit base property getters called abstractly by the
ACPI generator. Both of these fall back to pc_pci_hole64_start() if the
firmware didn't program any 64-bit hole (i.e. if the firmware didn't
assign a 64-bit GPA to any MMIO BAR on any device). Otherwise, they
honor the firmware's BAR assignments (i.e., they treat the lowest 64-bit
GPA programmed by the firmware as the base address for the aperture).
- i440fx_pcihost_get_pci_hole64_end(), q35_host_get_pci_hole64_end():
these intended to extend the aperture to our size recommendation,
calculated relative to the base of the aperture.
Despite the original intent, i440fx_pcihost_get_pci_hole64_end() and
q35_host_get_pci_hole64_end() currently only extend the aperture relative
to the default base (pc_pci_hole64_start()), ignoring any programming done
by the firmware. This means that our size recommendation may not be met.
Fix it by honoring the firmware's address assignments.
The strange extension sizes were spotted by Alex, in the log of a guest
kernel running on top of OVMF (which prefers to assign 64-bit GPAs to
64-bit BARs).
This change only affects DSDT generation, therefore no new compat property
is being introduced.
Using an i440fx OVMF guest with 5GB RAM, an example _CRS change is:
> @@ -881,9 +881,9 @@
> QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
> Cacheable, ReadWrite,
> 0x0000000000000000, // Granularity
> 0x0000000800000000, // Range Minimum
> - 0x000000080001C0FF, // Range Maximum
> + 0x000000087FFFFFFF, // Range Maximum
> 0x0000000000000000, // Translation Offset
> - 0x000000000001C100, // Length
> + 0x0000000080000000, // Length
> ,, , AddressRangeMemory, TypeStatic)
> })
> Device (GPE0)
(On i440fx, the low RAM split is at 3GB, in this case. Therefore, with 5GB
guest RAM and no DIMM hotplug range, pc_pci_hole64_start() returns 4 +
(5-3) = 6 GB. Adding the 2GB extension to that yields 8GB, which is below
the firmware-programmed base of 32GB, before the patch. Therefore, before
the patch, the extension is ineffective. After the patch, we add the 2GB
extension to the firmware-programmed base, namely 32GB.)
Using a q35 OVMF guest with 5GB RAM, an example _CRS change is:
> @@ -3162,9 +3162,9 @@
> QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
> Cacheable, ReadWrite,
> 0x0000000000000000, // Granularity
> 0x0000000800000000, // Range Minimum
> - 0x00000009BFFFFFFF, // Range Maximum
> + 0x0000000FFFFFFFFF, // Range Maximum
> 0x0000000000000000, // Translation Offset
> - 0x00000001C0000000, // Length
> + 0x0000000800000000, // Length
> ,, , AddressRangeMemory, TypeStatic)
> })
> Device (GPE0)
(On Q35, the low RAM split is at 2GB. Therefore, with 5GB guest RAM and no
DIMM hotplug range, pc_pci_hole64_start() returns 4 + (5-2) = 7 GB. Adding
the 32GB extension to that yields 39GB (0x0000_0009_BFFF_FFFF + 1), before
the patch. After the patch, we add the 32GB extension to the
firmware-programmed base, namely 32GB.)
The ACPI test data for the bios-tables-test case that we added earlier in
this series are corrected too, as follows:
> @@ -3339,9 +3339,9 @@
> QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
> Cacheable, ReadWrite,
> 0x0000000000000000, // Granularity
> 0x0000000200000000, // Range Minimum
> - 0x00000009BFFFFFFF, // Range Maximum
> + 0x00000009FFFFFFFF, // Range Maximum
> 0x0000000000000000, // Translation Offset
> - 0x00000007C0000000, // Length
> + 0x0000000800000000, // Length
> ,, , AddressRangeMemory, TypeStatic)
> })
> Device (GPE0)
Cc: "Michael S. Tsirkin" <address@hidden>
Cc: Alex Williamson <address@hidden>
Cc: Gerd Hoffmann <address@hidden>
Cc: Igor Mammedov <address@hidden>
Cc: Marcel Apfelbaum <address@hidden>
Fixes: 9fa99d2519cbf71f871e46871df12cb446dc1c3e
Signed-off-by: Laszlo Ersek <address@hidden>
Reviewed-by: Marcel Apfelbaum <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: f5f4002ddc0c0159735fc1a2dc44c97493fdff35
https://github.com/qemu/qemu/commit/f5f4002ddc0c0159735fc1a2dc44c97493fdff35
Author: Michael S. Tsirkin <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
A tests/data/acpi/q35/DSDT.mmio64
A tests/data/acpi/q35/SRAT.mmio64
Log Message:
-----------
bios-tables-test: prepare expected files for mmio64
test will be added by follow-up patch.
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 0259e96687fa9b01d87113693e076dfa83a649f0
https://github.com/qemu/qemu/commit/0259e96687fa9b01d87113693e076dfa83a649f0
Author: Laszlo Ersek <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M tests/bios-tables-test.c
Log Message:
-----------
tests/bios-tables-test: add 64-bit PCI MMIO aperture round-up test on Q35
In commit 9fa99d2519cb ("hw/pci-host: Fix x86 Host Bridges 64bit PCI
hole", 2017-11-16), we meant to expose such a 64-bit PCI MMIO aperture in
the ACPI DSDT that would be at least as large as the new "pci-hole64-size"
property (2GB on i440fx, 32GB on q35). The goal was to offer "enough"
64-bit MMIO aperture to the guest OS for hotplug purposes.
Previous patch fixed the issue that the aperture is extended relative to
a possibly incorrect base. This may result in an aperture size that is
smaller than the intent of commit 9fa99d2519cb.
This patch adds a test to make sure it won't happen again.
In the test case being added:
- use 128 MB initial RAM size,
- ask for one DIMM hotplug slot,
- ask for 2 GB maximum RAM size,
- use a pci-testdev with a 64-bit BAR of 2 GB size.
Consequences:
(1) In pc_memory_init() [hw/i386/pc.c], the DIMM hotplug area size is
initially set to 2048-128 = 1920 MB. (Maximum RAM size minus initial
RAM size.)
(2) The DIMM area base is set to 4096 MB (because the initial RAM is only
128 MB -- there is no initial "high RAM").
(3) Due to commit 085f8e88ba73 ("pc: count in 1Gb hugepage alignment when
sizing hotplug-memory container", 2014-11-24), we add 1 GB for the one
DIMM hotplug slot that was specified. This sets the DIMM area size to
1920+1024 = 2944 MB.
(4) The reserved-memory-end address (exclusive) is set to 4096 + 2944 =
7040 MB (DIMM area base plus DIMM area size).
(5) The reserved-memory-end address is rounded up to GB alignment,
yielding 7 GB (7168 MB).
(6) Given the 2 GB BAR size of pci-testdev, SeaBIOS allocates said 64-bit
BAR in 64-bit address space.
(7) Because reserved-memory-end is at 7 GB, it is unaligned for the 2 GB
BAR. Therefore SeaBIOS allocates the BAR at 8 GB. QEMU then
(correctly) assigns the root bridge aperture base this BAR address, to
be exposed in \_SB.PCI0._CRS.
(8) The intent of commit 9fa99d2519cb dictates that QEMU extend the
aperture size to 32 GB, implying a 40 GB end address. However, QEMU
performs the extension relative to reserved-memory-end (7 GB), not
relative to the bridge aperture base that was correctly deduced from
SeaBIOS's BAR programming (8 GB). Therefore we see 39 GB as the
aperture end address in \_SB.PCI0._CRS:
> QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable,
> ReadWrite,
> 0x0000000000000000, // Granularity
> 0x0000000200000000, // Range Minimum
> 0x00000009BFFFFFFF, // Range Maximum
> 0x0000000000000000, // Translation Offset
> 0x00000007C0000000, // Length
> ,, , AddressRangeMemory, TypeStatic)
Cc: "Michael S. Tsirkin" <address@hidden>
Cc: Alex Williamson <address@hidden>
Cc: Gerd Hoffmann <address@hidden>
Cc: Igor Mammedov <address@hidden>
Cc: Marcel Apfelbaum <address@hidden>
Signed-off-by: Laszlo Ersek <address@hidden>
Reviewed-by: Marcel Apfelbaum <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: c6329a2d0976661a466e02e29f50ce7b708cb8eb
https://github.com/qemu/qemu/commit/c6329a2d0976661a466e02e29f50ce7b708cb8eb
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/pci-bridge/xio3130_downstream.c
R hw/pci-bridge/xio3130_downstream.h
M hw/pci-bridge/xio3130_upstream.c
R hw/pci-bridge/xio3130_upstream.h
Log Message:
-----------
hw/pci-bridge/xio3130: Remove unused functions
Introduced in 48ebf2f90f8 and faf1e708d5b, these functions
were never used. Remove them.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: cd1f0ca29d3be55398d6def7ad9db9ad7bfb4e9d
https://github.com/qemu/qemu/commit/cd1f0ca29d3be55398d6def7ad9db9ad7bfb4e9d
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/pci-bridge/ioh3420.c
R hw/pci-bridge/ioh3420.h
Log Message:
-----------
hw/pci-bridge/ioh3420: Remove unuseful header
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 2728a57a061af92b476f926b7fb66cb3ac60ab50
https://github.com/qemu/qemu/commit/2728a57a061af92b476f926b7fb66cb3ac60ab50
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M include/hw/pci/pci_bus.h
Log Message:
-----------
hw/pci: Add missing include
Noted while refactoring:
CC mips-softmmu/hw/mips/gt64xxx_pci.o
In file included from include/hw/pci-host/gt64xxx.h:2,
from hw/mips/gt64xxx_pci.c:30:
include/hw/pci/pci_bus.h:23:5: error: unknown type name ‘PCIIOMMUFunc’
PCIIOMMUFunc iommu_fn;
^~~~~~~~~~~~
include/hw/pci/pci_bus.h:27:5: error: unknown type name ‘pci_set_irq_fn’
pci_set_irq_fn set_irq;
^~~~~~~~~~~~~~
include/hw/pci/pci_bus.h:28:5: error: unknown type name ‘pci_map_irq_fn’
pci_map_irq_fn map_irq;
^~~~~~~~~~~~~~
include/hw/pci/pci_bus.h:29:5: error: unknown type name ‘pci_route_irq_fn’
pci_route_irq_fn route_intx_to_irq;
^~~~~~~~~~~~~~~~
include/hw/pci/pci_bus.h:31:24: error: ‘PCI_SLOT_MAX’ undeclared here (not
in a function)
PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX];
^~~~~~~~~~~~
include/hw/pci/pci_bus.h:31:39: error: ‘PCI_FUNC_MAX’ undeclared here (not
in a function)
PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX];
^~~~~~~~~~~~
make[1]: *** [rules.mak:69: hw/mips/gt64xxx_pci.o] Error 1
make: *** [Makefile:482: subdir-mips-softmmu] Error 2
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: d05eec73e209b0ddca98fdb048de3a18b28223f4
https://github.com/qemu/qemu/commit/d05eec73e209b0ddca98fdb048de3a18b28223f4
Author: Mao Zhongyi <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/pci/pci_bridge.c
Log Message:
-----------
pci_bridge: fix typo in comment
Signed-off-by: Mao Zhongyi <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 0118c01cabdf6e37a7fb79aa267d18e787c2bd7b
https://github.com/qemu/qemu/commit/0118c01cabdf6e37a7fb79aa267d18e787c2bd7b
Author: Li Qiang <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/pci-host/piix.c
Log Message:
-----------
i440fx: use ARRAY_SIZE for pam_regions
Cc: address@hidden
Signed-off-by: Li Qiang <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: ee31e901ef3ad3bfa340fab7ec18f0a7eee6bab1
https://github.com/qemu/qemu/commit/ee31e901ef3ad3bfa340fab7ec18f0a7eee6bab1
Author: Li Qiang <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/pci-host/piix.c
Log Message:
-----------
piix: use TYPE_FOO constants than string constats
Make them more QOMConventional.
Cc:address@hidden
Signed-off-by: Li Qiang <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: 9b178f0e80cb007e1a96ac01f10d39e8955ddeb0
https://github.com/qemu/qemu/commit/9b178f0e80cb007e1a96ac01f10d39e8955ddeb0
Author: Li Qiang <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/pci-host/piix.c
Log Message:
-----------
piix_pci: fix i440fx data sheet link
It seems that the intel link is unavailable, change it to point to the
qemu site.
Signed-off-by: Li Qiang <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Marcel Apfelbaum <address@hidden>
Acked-by: Michael S. Tsirkin <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Commit: e6cc11d64fc998c11a4dfcde8fda3fc33a74d844
https://github.com/qemu/qemu/commit/e6cc11d64fc998c11a4dfcde8fda3fc33a74d844
Author: yuchenlin <address@hidden>
Date: 2018-11-05 (Mon, 05 Nov 2018)
Changed paths:
M hw/scsi/vhost-scsi.c
Log Message:
-----------
vhost-scsi: prevent using uninitialized vqs
There are 3 virtqueues (ctrl, event and cmd) for virtio scsi device,
but seabios will only set the physical address for the 3rd one (cmd).
Then in vhost_virtqueue_start(), virtio_queue_get_desc_addr()
will be 0 for ctrl and event vq.
In this case, ctrl and event vq are not initialized.
vhost_verify_ring_mappings may use uninitialized vhost_virtqueue
such that vhost_verify_ring_part_mapping returns ENOMEM.
When encountered this problem, we got the following logs:
qemu-system-x86_64: Unable to map available ring for ring 0
qemu-system-x86_64: Verify ring failure on region 0
Signed-off-by: Forrest Liu <address@hidden>
Signed-off-by: yuchenlin <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
Commit: b66db50f672015df53e0c1a317f6b0bb21d7d414
https://github.com/qemu/qemu/commit/b66db50f672015df53e0c1a317f6b0bb21d7d414
Author: Peter Maydell <address@hidden>
Date: 2018-11-06 (Tue, 06 Nov 2018)
Changed paths:
M MAINTAINERS
M configure
M docs/specs/pci-testdev.txt
M hw/block/vhost-user-blk.c
M hw/block/virtio-blk.c
M hw/i386/acpi-build.c
M hw/i386/amd_iommu.c
M hw/i386/amd_iommu.h
M hw/i386/intel_iommu.c
M hw/i386/trace-events
M hw/i386/x86-iommu.c
M hw/misc/pci-testdev.c
M hw/pci-bridge/ioh3420.c
R hw/pci-bridge/ioh3420.h
M hw/pci-bridge/xio3130_downstream.c
R hw/pci-bridge/xio3130_downstream.h
M hw/pci-bridge/xio3130_upstream.c
R hw/pci-bridge/xio3130_upstream.h
M hw/pci-host/piix.c
M hw/pci-host/q35.c
M hw/pci/pci_bridge.c
M hw/scsi/vhost-scsi.c
M include/hw/i386/intel_iommu.h
M include/hw/i386/x86-iommu.h
M include/hw/pci/pci_bus.h
R tests/acpi-test-data/pc/APIC
R tests/acpi-test-data/pc/APIC.cphp
R tests/acpi-test-data/pc/APIC.dimmpxm
R tests/acpi-test-data/pc/DSDT
R tests/acpi-test-data/pc/DSDT.bridge
R tests/acpi-test-data/pc/DSDT.cphp
R tests/acpi-test-data/pc/DSDT.dimmpxm
R tests/acpi-test-data/pc/DSDT.ipmikcs
R tests/acpi-test-data/pc/DSDT.memhp
R tests/acpi-test-data/pc/DSDT.numamem
R tests/acpi-test-data/pc/FACP
R tests/acpi-test-data/pc/FACS
R tests/acpi-test-data/pc/HPET
R tests/acpi-test-data/pc/NFIT.dimmpxm
R tests/acpi-test-data/pc/SLIT.cphp
R tests/acpi-test-data/pc/SLIT.memhp
R tests/acpi-test-data/pc/SRAT.cphp
R tests/acpi-test-data/pc/SRAT.dimmpxm
R tests/acpi-test-data/pc/SRAT.memhp
R tests/acpi-test-data/pc/SRAT.numamem
R tests/acpi-test-data/pc/SSDT.dimmpxm
R tests/acpi-test-data/q35/APIC
R tests/acpi-test-data/q35/APIC.cphp
R tests/acpi-test-data/q35/APIC.dimmpxm
R tests/acpi-test-data/q35/DSDT
R tests/acpi-test-data/q35/DSDT.bridge
R tests/acpi-test-data/q35/DSDT.cphp
R tests/acpi-test-data/q35/DSDT.dimmpxm
R tests/acpi-test-data/q35/DSDT.ipmibt
R tests/acpi-test-data/q35/DSDT.memhp
R tests/acpi-test-data/q35/DSDT.numamem
R tests/acpi-test-data/q35/FACP
R tests/acpi-test-data/q35/FACS
R tests/acpi-test-data/q35/HPET
R tests/acpi-test-data/q35/MCFG
R tests/acpi-test-data/q35/NFIT.dimmpxm
R tests/acpi-test-data/q35/SLIT.cphp
R tests/acpi-test-data/q35/SLIT.memhp
R tests/acpi-test-data/q35/SRAT.cphp
R tests/acpi-test-data/q35/SRAT.dimmpxm
R tests/acpi-test-data/q35/SRAT.memhp
R tests/acpi-test-data/q35/SRAT.numamem
R tests/acpi-test-data/q35/SSDT.dimmpxm
R tests/acpi-test-data/rebuild-expected-aml.sh
M tests/bios-tables-test.c
A tests/data/acpi/pc/APIC
A tests/data/acpi/pc/APIC.cphp
A tests/data/acpi/pc/APIC.dimmpxm
A tests/data/acpi/pc/DSDT
A tests/data/acpi/pc/DSDT.bridge
A tests/data/acpi/pc/DSDT.cphp
A tests/data/acpi/pc/DSDT.dimmpxm
A tests/data/acpi/pc/DSDT.ipmikcs
A tests/data/acpi/pc/DSDT.memhp
A tests/data/acpi/pc/DSDT.numamem
A tests/data/acpi/pc/FACP
A tests/data/acpi/pc/FACS
A tests/data/acpi/pc/HPET
A tests/data/acpi/pc/NFIT.dimmpxm
A tests/data/acpi/pc/SLIT.cphp
A tests/data/acpi/pc/SLIT.memhp
A tests/data/acpi/pc/SRAT.cphp
A tests/data/acpi/pc/SRAT.dimmpxm
A tests/data/acpi/pc/SRAT.memhp
A tests/data/acpi/pc/SRAT.numamem
A tests/data/acpi/pc/SSDT.dimmpxm
A tests/data/acpi/q35/APIC
A tests/data/acpi/q35/APIC.cphp
A tests/data/acpi/q35/APIC.dimmpxm
A tests/data/acpi/q35/DSDT
A tests/data/acpi/q35/DSDT.bridge
A tests/data/acpi/q35/DSDT.cphp
A tests/data/acpi/q35/DSDT.dimmpxm
A tests/data/acpi/q35/DSDT.ipmibt
A tests/data/acpi/q35/DSDT.memhp
A tests/data/acpi/q35/DSDT.mmio64
A tests/data/acpi/q35/DSDT.numamem
A tests/data/acpi/q35/FACP
A tests/data/acpi/q35/FACS
A tests/data/acpi/q35/HPET
A tests/data/acpi/q35/MCFG
A tests/data/acpi/q35/NFIT.dimmpxm
A tests/data/acpi/q35/SLIT.cphp
A tests/data/acpi/q35/SLIT.memhp
A tests/data/acpi/q35/SRAT.cphp
A tests/data/acpi/q35/SRAT.dimmpxm
A tests/data/acpi/q35/SRAT.memhp
A tests/data/acpi/q35/SRAT.mmio64
A tests/data/acpi/q35/SRAT.numamem
A tests/data/acpi/q35/SSDT.dimmpxm
A tests/data/acpi/rebuild-expected-aml.sh
A tests/data/hex-loader/test.hex
R tests/hex-loader-check-data/test.hex
M tests/hexloader-test.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
pci, pc, virtio: fixes, features
AMD IOMMU VAPIC support + fixes all over the place.
Signed-off-by: Michael S. Tsirkin <address@hidden>
# gpg: Signature made Mon 05 Nov 2018 18:24:10 GMT
# gpg: using RSA key 281F0DB8D28D5469
# gpg: Good signature from "Michael S. Tsirkin <address@hidden>"
# gpg: aka "Michael S. Tsirkin <address@hidden>"
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* remotes/mst/tags/for_upstream: (33 commits)
vhost-scsi: prevent using uninitialized vqs
piix_pci: fix i440fx data sheet link
piix: use TYPE_FOO constants than string constats
i440fx: use ARRAY_SIZE for pam_regions
pci_bridge: fix typo in comment
hw/pci: Add missing include
hw/pci-bridge/ioh3420: Remove unuseful header
hw/pci-bridge/xio3130: Remove unused functions
tests/bios-tables-test: add 64-bit PCI MMIO aperture round-up test on Q35
bios-tables-test: prepare expected files for mmio64
hw/pci-host/x86: extend the 64-bit PCI hole relative to the fw-assigned base
hw/pci-host/x86: extract get_pci_hole64_start_value() helpers
pci-testdev: add optional memory bar
MAINTAINERS: list "tests/acpi-test-data" files in ACPI/SMBIOS section
x86_iommu/amd: Enable Guest virtual APIC support
x86_iommu/amd: Add interrupt remap support when VAPIC is enabled
i386: acpi: add IVHD device entry for IOAPIC
x86_iommu/amd: Add interrupt remap support when VAPIC is not enabled
x86_iommu/amd: Prepare for interrupt remap support
x86_iommu/amd: make the address space naming consistent with intel-iommu
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/fc3d1bad1edf...b66db50f6720
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https://developer.github.com/changes/2018-04-25-github-services-deprecation/
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