[Qemu-commits] [qemu/qemu] 4a9b31: target/riscv/pmp.c: pmpcfg_csr_read returns bogus ...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 4a9b31b82bcd2cafe85137334f1c07afe56cc224
      
https://github.com/qemu/qemu/commit/4a9b31b82bcd2cafe85137334f1c07afe56cc224
  Author: Dayeol Lee <address@hidden>
  Date:   2018-10-30 (Tue, 30 Oct 2018)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64

pmp_read_cfg() returns 8-bit value, which is combined together to form a single 
pmpcfg CSR.
The default promotion rules will result in an integer here ("i*8" is integer, 
which
flows through) resulting in a 32-bit signed value on most hosts.
That's bogus on RV64I, with the high bits of the CSR being wrong.

Signed-off-by: Dayeol Lee <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: a17a61f306c12690d541515798b2d227049aa35b
      
https://github.com/qemu/qemu/commit/a17a61f306c12690d541515798b2d227049aa35b
  Author: Palmer Dabbelt <address@hidden>
  Date:   2018-10-30 (Tue, 30 Oct 2018)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  Add Alistair as a RISC-V Maintainer

Alistair has been contributing to the RISC-V QEMU port for a while now
so I'd like him to be officially listed as a maintainer.  I've checked
with the other RISC-V maintainers and there are no objections, and I've
also checked with Alistair so he knows I'm volunteering him.

Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: a094b3544f2855c0489f5df3c938b14b9a5899e5
      
https://github.com/qemu/qemu/commit/a094b3544f2855c0489f5df3c938b14b9a5899e5
  Author: Palmer Dabbelt <address@hidden>
  Date:   2018-10-30 (Tue, 30 Oct 2018)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  Add address@hidden as the RISC-V list

We now have a RISC-V specific QEMU development list.

Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>


  Commit: 69e2d03843412b9c076515b3aa9a71db161b6a1a
      
https://github.com/qemu/qemu/commit/69e2d03843412b9c076515b3aa9a71db161b6a1a
  Author: Peter Maydell <address@hidden>
  Date:   2018-11-02 (Fri, 02 Nov 2018)

  Changed paths:
    M MAINTAINERS
    M target/riscv/pmp.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/riscv/tags/riscv-for-master-3.1-sf1' 
into staging

RISC-V Patches for the 3.1 Soft Freeze, Part 2

This tag contains a few simple patches that I'd like to target for the
QEMU soft freeze.  There's only one code change: a fix to our PMP
implementation that avoids an internal truncation while computing a
partial PMP read.

I also have two updates to the MAINTAINERS file: one to add Alistair as
a RISC-V maintainer, and one to add our newly created mailing list.

# gpg: Signature made Tue 30 Oct 2018 18:17:17 GMT
# gpg:                using RSA key EF4CA1502CCBAB41
# gpg: Good signature from "Palmer Dabbelt <address@hidden>"
# gpg:                 aka "Palmer Dabbelt <address@hidden>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/riscv/tags/riscv-for-master-3.1-sf1:
  Add address@hidden as the RISC-V list
  Add Alistair as a RISC-V Maintainer
  target/riscv/pmp.c: pmpcfg_csr_read returns bogus value on RV64

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/fbdd2b2b03cb...69e2d0384341
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