[Qemu-commits] [qemu/qemu] de2e68: i386: correct cpu_x86_cpuid(0xd)

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: de2e68c902f7b6e438b0fa3cfedd74a06a20704f
      
https://github.com/qemu/qemu/commit/de2e68c902f7b6e438b0fa3cfedd74a06a20704f
  Author: Sebastian Andrzej Siewior <address@hidden>
  Date:   2018-10-30 (Tue, 30 Oct 2018)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: correct cpu_x86_cpuid(0xd)

Intel SDM says for CPUID function 0DH, sub-function 0:

| • ECX enumerates the size (in bytes) required by the XSAVE instruction for an
|   XSAVE area containing all the user state components supported by this
|   processor.
| • EBX enumerates the size (in bytes) required by the XSAVE instruction for an
|   XSAVE area containing all the user state components corresponding to bits
|   currently set in XCR0.

Signed-off-by: Sebastian Andrzej Siewior <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 38bf9e3b6185e6e4e4d50f7ff968676bf92a5bd7
      
https://github.com/qemu/qemu/commit/38bf9e3b6185e6e4e4d50f7ff968676bf92a5bd7
  Author: Peter Maydell <address@hidden>
  Date:   2018-10-30 (Tue, 30 Oct 2018)

  Changed paths:
    M target/i386/translate.c

  Log Message:
  -----------
  target/i386: Remove #ifdeffed-out icebp debugging hack

Remove a debugging hack which could be used to cause the
undocumented 'icebp' instruction to enable QEMU internal
debug logging. This code has always been #ifdeffed out
since it was introduced in commit aba9d61e34b9 in 2005;
judging by the rest of that commit (which is entirely
unrelated) it may have even been committed by accident.

(Note that WANT_ICEBP is not defined by default anyway.)

Signed-off-by: Peter Maydell <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: f57bceb6ab5163ddd6c41ff4344ab8cf28a9c63d
      
https://github.com/qemu/qemu/commit/f57bceb6ab5163ddd6c41ff4344ab8cf28a9c63d
  Author: Robert Hoo <address@hidden>
  Date:   2018-10-30 (Tue, 30 Oct 2018)

  Changed paths:
    M include/sysemu/kvm.h
    M target/i386/kvm.c

  Log Message:
  -----------
  kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS system 
ioctl

Add kvm_get_supported_feature_msrs() to get supported MSR feature index list.
Add kvm_arch_get_supported_msr_feature() to get each MSR features value.

Signed-off-by: Robert Hoo <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 07585923485952bf4cb7da563c9f91fecc85d09c
      
https://github.com/qemu/qemu/commit/07585923485952bf4cb7da563c9f91fecc85d09c
  Author: Robert Hoo <address@hidden>
  Date:   2018-10-30 (Tue, 30 Oct 2018)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  x86: Data structure changes to support MSR based features

Add FeatureWordType indicator in struct FeatureWordInfo.
Change feature_word_info[] accordingly.
Change existing functions that refer to feature_word_info[] accordingly.

Signed-off-by: Robert Hoo <address@hidden>
Message-Id: <address@hidden>
[ehabkost: fixed hvf_enabled() case]
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: d86f963694df27f11b3681ffd225c9362de1b634
      
https://github.com/qemu/qemu/commit/d86f963694df27f11b3681ffd225c9362de1b634
  Author: Robert Hoo <address@hidden>
  Date:   2018-10-30 (Tue, 30 Oct 2018)

  Changed paths:
    M target/i386/cpu.c
    M target/i386/cpu.h
    M target/i386/kvm.c

  Log Message:
  -----------
  x86: define a new MSR based feature word -- FEATURE_WORDS_ARCH_CAPABILITIES

Note RSBA is specially treated -- no matter host support it or not, qemu
pretends it is supported.

Signed-off-by: Robert Hoo <address@hidden>
Message-Id: <address@hidden>
[ehabkost: removed automatic enabling of RSBA]
Reviewed-by: Eduardo Habkost <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: c7a88b52f62b30c04158eeb07f73e3f72221b6a8
      
https://github.com/qemu/qemu/commit/c7a88b52f62b30c04158eeb07f73e3f72221b6a8
  Author: Tao Xu <address@hidden>
  Date:   2018-10-30 (Tue, 30 Oct 2018)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: Add new model of Cascadelake-Server

New CPU models mostly inherit features from ancestor Skylake-Server,
while addin new features: AVX512_VNNI, Intel PT.
SSBD support for speculative execution
side channel mitigations.

Note:

On Cascadelake, some capabilities (RDCL_NO, IBRS_ALL, RSBA,
SKIP_L1DFL_VMENTRY and SSB_NO) are enumerated by MSR.
These features rely on MSR based feature support patch.
Will be added later after that patch's in.
http://lists.nongnu.org/archive/html/qemu-devel/2018-09/msg00074.html

Signed-off-by: Tao Xu <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 09b9ee643f90ef95e30e594df2a3c83ccaf75b1f
      
https://github.com/qemu/qemu/commit/09b9ee643f90ef95e30e594df2a3c83ccaf75b1f
  Author: Tao Xu <address@hidden>
  Date:   2018-10-30 (Tue, 30 Oct 2018)

  Changed paths:
    M include/hw/i386/pc.h
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: Add PKU on Skylake-Server CPU model

As the release document ref below link (page 13):
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf

PKU is supported in Skylake Server (Only Server) and later, and
on Intel(R) Xeon(R) Processor Scalable Family. So PKU is supposed
to be in Skylake-Server CPU model. And PKU's CPUID has been
exposed to QEMU. But PKU can't be find in Skylake-Server CPU
model in the code. So this patch will fix this issue in
Skylake-Server CPU model.

Signed-off-by: Tao Xu <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 00878c95165de8ffc015a43e14249d789de1b8ff
      
https://github.com/qemu/qemu/commit/00878c95165de8ffc015a43e14249d789de1b8ff
  Author: Peter Maydell <address@hidden>
  Date:   2018-11-01 (Thu, 01 Nov 2018)

  Changed paths:
    M include/hw/i386/pc.h
    M include/sysemu/kvm.h
    M target/i386/cpu.c
    M target/i386/cpu.h
    M target/i386/kvm.c
    M target/i386/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' 
into staging

x86 queue, 2018-10-30

* MSR-based feature support for
  MSR_IA32_ARCH_CAPABILITIES bits (Robert Hoo)
* Cascadelake-Server CPU model (Tao Xu)
* Add PKU on Skylake-Server CPU model (Tao Xu)
* Correct cpu_x86_cpuid(0xd) (Sebastian Andrzej Siewior)
* Remove dead code (Peter Maydell)

# gpg: Signature made Wed 31 Oct 2018 14:05:25 GMT
# gpg:                using RSA key 2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <address@hidden>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-next-pull-request:
  i386: Add PKU on Skylake-Server CPU model
  i386: Add new model of Cascadelake-Server
  x86: define a new MSR based feature word -- FEATURE_WORDS_ARCH_CAPABILITIES
  x86: Data structure changes to support MSR based features
  kvm: Add support to KVM_GET_MSR_FEATURE_INDEX_LIST and KVM_GET_MSRS system 
ioctl
  target/i386: Remove #ifdeffed-out icebp debugging hack
  i386: correct cpu_x86_cpuid(0xd)

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/60126df95f14...00878c95165d
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