[Qemu-commits] [qemu/qemu] 61e9e3: ssi-sd: Make devices picking up backe

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[Qemu-commits] [qemu/qemu] 61e9e3: ssi-sd: Make devices picking up backe

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 61e9e3: ssi-sd: Make devices picking up backends unavailab...
Date:	Wed, 24 Oct 2018 08:00:19 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 61e9e3cb45c378c1e705d67ff66e5936249539c8
      
https://github.com/qemu/qemu/commit/61e9e3cb45c378c1e705d67ff66e5936249539c8
  Author: Markus Armbruster <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M hw/sd/ssi-sd.c

  Log Message:
  -----------
  ssi-sd: Make devices picking up backends unavailable with -device

Device models aren't supposed to go on fishing expeditions for
backends.  They should expose suitable properties for the user to set.
For onboard devices, board code sets them.

Device ssi-sd picks up its block backend in its init() method with
drive_get_next() instead.  This mistake is already marked FIXME since
commit af9e40a.

Unset user_creatable to remove the mistake from our external
interface.  Since the SSI bus doesn't support hotplug, only -device
can be affected.  Only certain ARM machines have ssi-sd and provide an
SSI bus for it; this patch breaks -device ssi-sd for these machines.
No actual use of -device ssi-sd is known.

Signed-off-by: Markus Armbruster <address@hidden>
Acked-by: Philippe Mathieu-Daudé <address@hidden>
Acked-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 202ccb6bab5fe26bca2c82bff23302f7acfd1940
      
https://github.com/qemu/qemu/commit/202ccb6bab5fe26bca2c82bff23302f7acfd1940
  Author: Dongjiu Geng <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/kvm.c
    M target/arm/kvm32.c
    M target/arm/kvm64.c
    M target/arm/kvm_arm.h
    M target/arm/machine.c

  Log Message:
  -----------
  target/arm: Add support for VCPU event states

This patch extends the qemu-kvm state sync logic with support for
KVM_GET/SET_VCPU_EVENTS, giving access to yet missing SError exception.
And also it can support the exception state migration.

The SError exception states include SError pending state and ESR value,
the kvm_put/get_vcpu_events() will be called when set or get system
registers. When do migration, if source machine has SError pending,
QEMU will do this migration regardless whether the target machine supports
to specify guest ESR value, because if target machine does not support that,
it can also inject the SError with zero ESR value.

Signed-off-by: Dongjiu Geng <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 47576b94af5c406fc6521fb336fb5c12beeac3f8
      
https://github.com/qemu/qemu/commit/47576b94af5c406fc6521fb336fb5c12beeac3f8
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Move some system registers into a substructure

Create struct ARMISARegisters, to be accessed during translation.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5256df880d1312a58472af3fb0a3c51e708f2161
      
https://github.com/qemu/qemu/commit/5256df880d1312a58472af3fb0a3c51e708f2161
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: V8M should not imply V7VE

Instantiating mps2-an505 (cortex-m33) will fail make check when
V7VE asserts that ID_ISAR0.Divide includes ARM division.  It is
also wrong to include ARM_FEATURE_LPAE.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 962fcbf2efe57231a9f5df0ae0f40c05e35628ba
      
https://github.com/qemu/qemu/commit/962fcbf2efe57231a9f5df0ae0f40c05e35628ba
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M linux-user/elfload.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Convert v8 extensions from feature bits to isar tests

Most of the v8 extensions are self-contained within the ISAR
registers and are not implied by other feature bits, which
makes them the easiest to convert.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7e0cf8b47f0e67cebbc3dfa73f304e56ad1a090f
      
https://github.com/qemu/qemu/commit/7e0cf8b47f0e67cebbc3dfa73f304e56ad1a090f
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M linux-user/elfload.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert division from feature bits to isar0 tests

Both arm and thumb2 division are controlled by the same ISAR field,
which takes care of the arm implies thumb case.  Having M imply
thumb2 division was wrong for cortex-m0, which is v6m and does not
have thumb2 at all, much less thumb2 division.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 09cbd50198d5dcac8bea2e47fa5dd641ec505fae
      
https://github.com/qemu/qemu/commit/09cbd50198d5dcac8bea2e47fa5dd641ec505fae
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert jazelle from feature bit to isar1 test

Having V6 alone imply jazelle was wrong for cortex-m0.
Change to an assertion for V6 & !M.

This was harmless, because the only place we tested ARM_FEATURE_JAZELLE
was for 'bxj' in disas_arm(), which is unreachable for M-profile cores.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: cd208a1c3923bc097ec55c5b207d79294ab0e719
      
https://github.com/qemu/qemu/commit/cd208a1c3923bc097ec55c5b207d79294ab0e719
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M linux-user/aarch64/signal.c
    M linux-user/elfload.c
    M linux-user/syscall.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c
    M target/arm/machine.c
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert sve from feature bit to aa64pfr0 test

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5763190fa8705863b4b725aa1657661a97113eb4
      
https://github.com/qemu/qemu/commit/5763190fa8705863b4b725aa1657661a97113eb4
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M linux-user/elfload.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 81e3728407bf4a12f83e14fd410d5f0a7d29b5b4
      
https://github.com/qemu/qemu/commit/81e3728407bf4a12f83e14fd410d5f0a7d29b5b4
  Author: Peter Maydell <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Improve debug logging of AArch32 exception return

For AArch32, exception return happens through certain kinds
of CPSR write. We don't currently have any CPU_LOG_INT logging
of these events (unlike AArch64, where we log in the ERET
instruction). Add some suitable logging.

This will log exception returns like this:
Exception return from AArch32 hyp to usr PC 0x80100374

paralleling the existing logging in the exception_return
helper for AArch64 exception returns:
Exception return from AArch64 EL2 to AArch64 EL0 PC 0x8003045c
Exception return from AArch64 EL2 to AArch32 EL0 PC 0x8003045c

(Note that an AArch32 exception return can only be
AArch32->AArch32, never to AArch64.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: affdb64d847bfa7c4fafe9d85fd5f3d905314fc4
      
https://github.com/qemu/qemu/commit/affdb64d847bfa7c4fafe9d85fd5f3d905314fc4
  Author: Peter Maydell <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Make switch_mode() file-local

The switch_mode() function is defined in target/arm/helper.c and used
only in that file and nowhere else, so we can make it file-local
rather than global.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: b4ab8ce98b8c482c8986785800f238d32a1578a9
      
https://github.com/qemu/qemu/commit/b4ab8ce98b8c482c8986785800f238d32a1578a9
  Author: Peter Maydell <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement HCR.FB

The HCR.FB virtualization configuration register bit requests that
TLB maintenance, branch predictor invalidate-all and icache
invalidate-all operations performed in NS EL1 should be upgraded
from "local CPU only to "broadcast within Inner Shareable domain".
For QEMU we NOP the branch predictor and icache operations, so
we only need to upgrade the TLB invalidates:
 AArch32 TLBIALL, TLBIMVA, TLBIASID, DTLBIALL, DTLBIMVA, DTLBIASID,
   ITLBIALL, ITLBIMVA, ITLBIASID, TLBIMVAA, TLBIMVAL, TLBIMVAAL
 AArch64 TLBI VMALLE1, TLBI VAE1, TLBI ASIDE1, TLBI VAAE1,
   TLBI VALE1, TLBI VAALE1

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 9d1bab337caf2324a233e5937f415fad4ce1641b
      
https://github.com/qemu/qemu/commit/9d1bab337caf2324a233e5937f415fad4ce1641b
  Author: Peter Maydell <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement HCR.DC

The HCR.DC virtualization configuration register bit has the
following effects:
 * SCTLR.M behaves as if it is 0 for all purposes except
   direct reads of the bit
 * HCR.VM behaves as if it is 1 for all purposes except
   direct reads of the bit
 * the memory type produced by the first stage of the EL1&EL0
   translation regime is Normal Non-Shareable,
   Inner Write-Back Read-Allocate Write-Allocate,
   Outer Write-Back Read-Allocate Write-Allocate.

Implement this behaviour.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 636540e9c40bd0931ef3022cb953bb7dbecd74ed
      
https://github.com/qemu/qemu/commit/636540e9c40bd0931ef3022cb953bb7dbecd74ed
  Author: Peter Maydell <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set

The A/I/F bits in ISR_EL1 should track the virtual interrupt
status, not the physical interrupt status, if the associated
HCR_EL2.AMO/IMO/FMO bit is set. Implement this, rather than
always showing the physical interrupt status.

We don't currently implement anything to do with external
aborts, so this applies only to the I and F bits (though it
ought to be possible for the outer guest to present a virtual
external abort to the inner guest, even if QEMU doesn't
emulate physical external aborts, so there is missing
functionality in this area).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 8a0fc3a29fc2315325400c738f807d0d4ae0ab7f
      
https://github.com/qemu/qemu/commit/8a0fc3a29fc2315325400c738f807d0d4ae0ab7f
  Author: Peter Maydell <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement HCR.VI and VF

The HCR_EL2 VI and VF bits are supposed to track whether there is
a pending virtual IRQ or virtual FIQ. For QEMU we store the
pending VIRQ/VFIQ status in cs->interrupt_request, so this means:
 * if the register is read we must get these bit values from
   cs->interrupt_request
 * if the register is written then we must write the bit
   values back into cs->interrupt_request

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: eadb2febf05452bd8062c4c7823d7d789142500c
      
https://github.com/qemu/qemu/commit/eadb2febf05452bd8062c4c7823d7d789142500c
  Author: Peter Maydell <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Implement HCR.PTW

If the HCR_EL2 PTW virtualizaiton configuration register bit
is set, then this means that a stage 2 Permission fault must
be generated if a stage 1 translation table access is made
to an address that is mapped as Device memory in stage 2.
Implement this.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 64b91e3f890a8c221b65c6820a5ee39107ee40f5
      
https://github.com/qemu/qemu/commit/64b91e3f890a8c221b65c6820a5ee39107ee40f5
  Author: Peter Maydell <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/kvm64.c
    M target/arm/op_helper.c

  Log Message:
  -----------
  target/arm: New utility function to extract EC from syndrome

Create and use a utility function to extract the EC field
from a syndrome, rather than open-coding the shift.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 2ed08180db096ea5e44573529b85e09b1ed10b08
      
https://github.com/qemu/qemu/commit/2ed08180db096ea5e44573529b85e09b1ed10b08
  Author: Peter Maydell <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Get IL bit correct for v7 syndrome values

For the v7 version of the Arm architecture, the IL bit in
syndrome register values where the field is not valid was
defined to be UNK/SBZP. In v8 this is RES1, which is what
QEMU currently implements. Handle the desired v7 behaviour
by squashing the IL bit for the affected cases:
 * EC == EC_UNCATEGORIZED
 * prefetch aborts
 * data aborts where ISV is 0

(The fourth case listed in the v8 Arm ARM DDI 0487C.a in
section G7.2.70, "illegal state exception", can't happen
on a v7 CPU.)

This deals with a corner case noted in a comment.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 4be42f4013fa1a9df47b48aae5148767bed8e80c
      
https://github.com/qemu/qemu/commit/4be42f4013fa1a9df47b48aae5148767bed8e80c
  Author: Peter Maydell <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode

For traps of FP/SIMD instructions to AArch32 Hyp mode, the syndrome
provided in HSR has more information than is reported to AArch64.
Specifically, there are extra fields TA and coproc which indicate
whether the trapped instruction was FP or SIMD. Add this extra
information to the syndromes we construct, and mask it out when
taking the exception to AArch64.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: ea358872a6a2e136a6a2bc08649a079acb99b6a2
      
https://github.com/qemu/qemu/commit/ea358872a6a2e136a6a2bc08649a079acb99b6a2
  Author: Stewart Hildebrand <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  hw/arm/boot: Increase compliance with kernel arm64 boot protocol

"The Image must be placed text_offset bytes from a 2MB aligned base
address anywhere in usable system RAM and called there."

For the virt board, we write our startup bootloader at the very
bottom of RAM, so that bit can't be used for the image. To avoid
overlap in case the image requests to be loaded at an offset
smaller than our bootloader, we increment the load offset to the
next 2MB.

This fixes a boot failure for Xen AArch64.

Signed-off-by: Stewart Hildebrand <address@hidden>
Tested-by: Andre Przywara <address@hidden>
Message-id: address@hidden
[PMM: Rephrased a comment a bit]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a7d8143aed2268f147cc1abfebc848ed6282a313
      
https://github.com/qemu/qemu/commit/a7d8143aed2268f147cc1abfebc848ed6282a313
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Hoist address increment for vector memory ops

This can reduce the number of opcodes required for certain
complex forms of load-multiple (e.g. ld4.16b).

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7108e255c2d95b44c9dfee8075d0d6fb391281a8
      
https://github.com/qemu/qemu/commit/7108e255c2d95b44c9dfee8075d0d6fb391281a8
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Don't call tcg_clear_temp_count

This is done generically in translator_loop.

Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 10e0b33c676b4e8ac80d5929980f4fa6be617c5a
      
https://github.com/qemu/qemu/commit/10e0b33c676b4e8ac80d5929980f4fa6be617c5a
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 87f9a7f0c8d5122c36743885158782c2348a6d21
      
https://github.com/qemu/qemu/commit/87f9a7f0c8d5122c36743885158782c2348a6d21
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Promote consecutive memory ops for aa64

For a sequence of loads or stores from a single register,
little-endian operations can be promoted to an 8-byte op.
This can reduce the number of operations by a factor of 8.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 308e5636152594daa4c5597b1188d44d7266db04
      
https://github.com/qemu/qemu/commit/308e5636152594daa4c5597b1188d44d7266db04
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Mark some arrays const

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
[PMM: drop change to now-deleted cpu_mode_names array]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 32f91fb71f4c32113ec8c2af5f74f14abe6c7162
      
https://github.com/qemu/qemu/commit/32f91fb71f4c32113ec8c2af5f74f14abe6c7162
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Use gvec for NEON VDUP

Also introduces neon_element_offset to find the env offset
of a specific element within a neon register.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 246fa4aca95e213fba10c8222dbc6bd0a9a2a8d4
      
https://github.com/qemu/qemu/commit/246fa4aca95e213fba10c8222dbc6bd0a9a2a8d4
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate)

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: eabcd6faa90461e0b7463f4ebe75b8d050487c9c
      
https://github.com/qemu/qemu/commit/eabcd6faa90461e0b7463f4ebe75b8d050487c9c
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Use gvec for NEON_3R_LOGIC insns

Move expanders for VBSL, VBIT, and VBIF from translate-a64.c.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e4717ae02dd0c2e544a07302c1ed473775209aba
      
https://github.com/qemu/qemu/commit/e4717ae02dd0c2e544a07302c1ed473775209aba
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Use gvec for NEON_3R_VADD_VSUB insns

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4bf940bebad273e4b3534ae3f83f2c9d1191d3a2
      
https://github.com/qemu/qemu/commit/4bf940bebad273e4b3534ae3f83f2c9d1191d3a2
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 82083184b6ad1b9e84f14669c4015672595ffd24
      
https://github.com/qemu/qemu/commit/82083184b6ad1b9e84f14669c4015672595ffd24
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Use gvec for NEON_3R_VMUL

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1dc8425e551be1371d657e94367f37130cd7aede
      
https://github.com/qemu/qemu/commit/1dc8425e551be1371d657e94367f37130cd7aede
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Use gvec for VSHR, VSHL

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 41f6c113c9ebf475554b2546c3e4c175db02c569
      
https://github.com/qemu/qemu/commit/41f6c113c9ebf475554b2546c3e4c175db02c569
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Use gvec for VSRA

Move ssra_op and usra_op expanders from translate-a64.c.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f3cd8218d1d3e534877ce3f3cb61c6757d10f9df
      
https://github.com/qemu/qemu/commit/f3cd8218d1d3e534877ce3f3cb61c6757d10f9df
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Use gvec for VSRI, VSLI

Move shi_op and sli_op expanders from translate-a64.c.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4a7832b095b9ce97a815749a13516f5cfb3c5dd4
      
https://github.com/qemu/qemu/commit/4a7832b095b9ce97a815749a13516f5cfb3c5dd4
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Use gvec for NEON_3R_VML

Move mla_op and mls_op expanders from translate-a64.c.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ea580fa312674c1ba82a8b137caf42b0609ce3e3
      
https://github.com/qemu/qemu/commit/ea580fa312674c1ba82a8b137caf42b0609ce3e3
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE

Move cmtst_op expanders from translate-a64.c.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7377c2c97e20e64ed9b481eb2d9b9084bfd5b7e9
      
https://github.com/qemu/qemu/commit/7377c2c97e20e64ed9b481eb2d9b9084bfd5b7e9
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Use gvec for NEON VLD all lanes

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[PMM: added parens in ?: expression]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ac55d00709e78cd39dfa298dcaac7aecb58762e8
      
https://github.com/qemu/qemu/commit/ac55d00709e78cd39dfa298dcaac7aecb58762e8
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Reorg NEON VLD/VST all elements

Instead of shifts and masks, use direct loads and stores from the neon
register file.  Mirror the iteration structure of the ARM pseudocode
more closely.  Correct the parameters of the VLD2 A2 insn.

Note that this includes a bugfix for handling of the insn
"VLD2 (multiple 2-element structures)" -- we were using an
incorrect stride value.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e23f12b3a252352b575908ca7b94587acd004641
      
https://github.com/qemu/qemu/commit/e23f12b3a252352b575908ca7b94587acd004641
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Promote consecutive memory ops for aa32

For a sequence of loads or stores from a single register,
little-endian operations can be promoted to an 8-byte op.
This can reduce the number of operations by a factor of 8.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2d6ac920837f558be214ad2ddd28cad7f3b15e5c
      
https://github.com/qemu/qemu/commit/2d6ac920837f558be214ad2ddd28cad7f3b15e5c
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Reorg NEON VLD/VST single element to one lane

Instead of shifts and masks, use direct loads and stores from
the neon register file.

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 726a2a951bf12fe0e0c0034b3ba23e8a3e2f331c
      
https://github.com/qemu/qemu/commit/726a2a951bf12fe0e0c0034b3ba23e8a3e2f331c
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M hw/net/cadence_gem.c

  Log Message:
  -----------
  net: cadence_gem: Announce availability of priority queues

Announce the availability of the various priority queues.
This fixes an issue where guest kernels would miss to
configure secondary queues due to inproper feature bits.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e2c0c4eef5a4901b817f8fc73941575c927699ff
      
https://github.com/qemu/qemu/commit/e2c0c4eef5a4901b817f8fc73941575c927699ff
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M hw/net/cadence_gem.c

  Log Message:
  -----------
  net: cadence_gem: Announce 64bit addressing support

Announce 64bit addressing support.

Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f478847f1ee0df9397f561025ab2f687fd923571
      
https://github.com/qemu/qemu/commit/f478847f1ee0df9397f561025ab2f687fd923571
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Remove writefn from TTBR0_EL3

The EL3 version of this register does not include an ASID,
and so the tlb_flush performed by vmsa_ttbr_write is not needed.

Reviewed-by: Aaron Lindsay <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 93f379b0c43617b1361f742f261479eaed4959cb
      
https://github.com/qemu/qemu/commit/93f379b0c43617b1361f742f261479eaed4959cb
  Author: Richard Henderson <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Only flush tlb if ASID changes

Since QEMU does not implement ASIDs, changes to the ASID must flush the
tlb.  However, if the ASID does not change there is no reason to flush.

In testing a boot of the Ubuntu installer to the first menu, this reduces
the number of flushes by 30%, or nearly 600k instances.

Reviewed-by: Aaron Lindsay <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e60b38f445d0ca0c305440b07a23e8f0da73373a
      
https://github.com/qemu/qemu/commit/e60b38f445d0ca0c305440b07a23e8f0da73373a
  Author: Peter Maydell <address@hidden>
  Date:   2018-10-24 (Wed, 24 Oct 2018)

  Changed paths:
    M hw/arm/boot.c
    M hw/intc/armv7m_nvic.c
    M hw/net/cadence_gem.c
    M hw/sd/ssi-sd.c
    M linux-user/aarch64/signal.c
    M linux-user/elfload.c
    M linux-user/syscall.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/kvm.c
    M target/arm/kvm32.c
    M target/arm/kvm64.c
    M target/arm/kvm_arm.h
    M target/arm/machine.c
    M target/arm/op_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20181024' 
into staging

target-arm queue:
 * ssi-sd: Make devices picking up backends unavailable with -device
 * Add support for VCPU event states
 * Move towards making ID registers the source of truth for
   whether a guest CPU implements a feature, rather than having
   parallel ID registers and feature bit flags
 * Implement various HCR hypervisor trap/config bits
 * Get IL bit correct for v7 syndrome values
 * Report correct syndrome for FP/SIMD traps to Hyp mode
 * hw/arm/boot: Increase compliance with kernel arm64 boot protocol
 * Refactor A32 Neon to use generic vector infrastructure
 * Fix a bug in A32 VLD2 "(multiple 2-element structures)" insn
 * net: cadence_gem: Report features correctly in ID register
 * Avoid some unnecessary TLB flushes on TTBR register writes

# gpg: Signature made Wed 24 Oct 2018 10:46:01 BST
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20181024: (44 commits)
  target/arm: Only flush tlb if ASID changes
  target/arm: Remove writefn from TTBR0_EL3
  net: cadence_gem: Announce 64bit addressing support
  net: cadence_gem: Announce availability of priority queues
  target/arm: Reorg NEON VLD/VST single element to one lane
  target/arm: Promote consecutive memory ops for aa32
  target/arm: Reorg NEON VLD/VST all elements
  target/arm: Use gvec for NEON VLD all lanes
  target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE
  target/arm: Use gvec for NEON_3R_VML
  target/arm: Use gvec for VSRI, VSLI
  target/arm: Use gvec for VSRA
  target/arm: Use gvec for VSHR, VSHL
  target/arm: Use gvec for NEON_3R_VMUL
  target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG
  target/arm: Use gvec for NEON_3R_VADD_VSUB insns
  target/arm: Use gvec for NEON_3R_LOGIC insns
  target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate)
  target/arm: Use gvec for NEON VDUP
  target/arm: Mark some arrays const
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/13399aad4fa8...e60b38f445d0
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