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[Qemu-commits] [qemu/qemu] c8a447: target/arm: fix code comments error
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[Qemu-commits] [qemu/qemu] c8a447: target/arm: fix code comments error |
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Date: |
Mon, 08 Oct 2018 07:40:13 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: c8a44709861869feff478dac6062f04b7411b04f
https://github.com/qemu/qemu/commit/c8a44709861869feff478dac6062f04b7411b04f
Author: Dongjiu Geng <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/kvm.c
M target/arm/kvm_arm.h
Log Message:
-----------
target/arm: fix code comments error
The parameter of kvm_arm_init_cpreg_list() is ARMCPU instead of
CPUState, so correct the note to make it match the code.
Signed-off-by: Dongjiu Geng <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 846690dee8ca6a4143d20b39e894fd1f24627561
https://github.com/qemu/qemu/commit/846690dee8ca6a4143d20b39e894fd1f24627561
Author: Peter Maydell <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
virt: Suppress external aborts on virt-2.10 and earlier
In commit c79c0a314c43b78 we enabled emulation of external aborts
when the guest attempts to access a physical address with no
mapped device. In commit 4672cbd7bed88dc6 we suppress this for
most legacy boards to prevent breakage of previously working
guests, but we didn't suppress it in the 'virt' board, with
the rationale "we know that guests won't try to prod devices
that we don't describe in the device tree or ACPI tables". This
is mostly true, but we've had a report of a Linux guest image
that this did break. The problem seems to be that the guest
is (incorrectly) configured with a DEBUG_UART_PHYS value that
tells it there is a uart at 0x10009000 (which is true for
vexpress but not for virt), so in early bootup the kernel
probes this bogus address.
This is a misconfigured guest, so we don't need to worry
about it too much, but we can arrange that guests that ran
on QEMU v2.10 (before c79c0a314c43b78) will still run on
the "virt-2.10" board model, by suppressing external aborts
only for that version and earlier. This seems a reasonable
compromise: "virt-2.10" is supposed to behave the same way
that "virt" did in the 2.10 release, and making it do that
provides a usable workaround for guests with bugs like this.
Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Commit: 7b73a1ca05b33d42278ce29cea4652e22d408165
https://github.com/qemu/qemu/commit/7b73a1ca05b33d42278ce29cea4652e22d408165
Author: Peter Maydell <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Correct condition for v8M callee stack push
In v7m_exception_taken() we were incorrectly using a
"LR bit EXCRET.ES is 1" check when it should be 0
(compare the pseudocode ExceptionTaken() function).
This meant we didn't stack the callee-saved registers
when tailchaining from a NonSecure to a Secure exception.
Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: e5ae4d0c063fbcca4cbbd26bcefbf1760cfac2aa
https://github.com/qemu/qemu/commit/e5ae4d0c063fbcca4cbbd26bcefbf1760cfac2aa
Author: Peter Maydell <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Don't read r4 from v8M exception stackframe twice
A cut-and-paste error meant we were reading r4 from the v8M
callee-saves exception stack frame twice. This is harmless
since it just meant we did two memory accesses to the same
location, but it's unnecessary. Delete it.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 9516d7725ec1deaa6ef5ccc5a26d005650d6c524
https://github.com/qemu/qemu/commit/9516d7725ec1deaa6ef5ccc5a26d005650d6c524
Author: Richard Henderson <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Define ID_AA64ZFR0_EL1
Given that the only field defined for this new register may only
be 0, we don't actually need to change anything except the name.
Reviewed-by: Peter Maydell <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 60eed0869d68b91eff71cc0a0facb01983726a5d
https://github.com/qemu/qemu/commit/60eed0869d68b91eff71cc0a0facb01983726a5d
Author: Richard Henderson <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Adjust sve_exception_el
Check for EL3 before testing CPTR_EL3.EZ. Return 0 when the exception
should be routed via AdvSIMDFPAccessTrap. Mirror the structure of
CheckSVEEnabled more closely.
Fixes: 5be5e8eda78
Reviewed-by: Peter Maydell <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 2de7ace292cf7846b0cda0e940272d2cb0e06859
https://github.com/qemu/qemu/commit/2de7ace292cf7846b0cda0e940272d2cb0e06859
Author: Richard Henderson <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Pass in current_el to fp and sve_exception_el
We are going to want to determine whether sve is enabled
for EL other than current.
Tested-by: Laurent Desnogues <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 0ab5953b00b3165877d00cf75de628c51670b550
https://github.com/qemu/qemu/commit/0ab5953b00b3165877d00cf75de628c51670b550
Author: Richard Henderson <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
M target/arm/op_helper.c
Log Message:
-----------
target/arm: Handle SVE vector length changes in system mode
SVE vector length can change when changing EL, or when writing
to one of the ZCR_ELn registers.
For correctness, our implementation requires that predicate bits
that are inaccessible are never set. Which means noticing length
changes and zeroing the appropriate register bits.
Tested-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: ced3155141755ba244c988c72c4bde32cc819670
https://github.com/qemu/qemu/commit/ced3155141755ba244c988c72c4bde32cc819670
Author: Richard Henderson <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Adjust aarch64_cpu_dump_state for system mode SVE
Use the existing helpers to determine if (1) the fpu is enabled,
(2) sve state is enabled, and (3) the current sve vector length.
Tested-by: Laurent Desnogues <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 2a99ab2b3545133961de034df27e24f4c22e3707
https://github.com/qemu/qemu/commit/2a99ab2b3545133961de034df27e24f4c22e3707
Author: Richard Henderson <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Clear unused predicate bits for LD1RQ
The 16-byte load only uses 16 predicate bits. But while
reusing the other load infrastructure, we find other bits
that are set and trigger an assert. To avoid this and
retain the assert, zero-extend the predicate that we pass
to the LD1 helper.
Tested-by: Laurent Desnogues <address@hidden>
Reported-by: Laurent Desnogues <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 9123aeb6fcb14e0955ebe4e2a613802cfa0503ea
https://github.com/qemu/qemu/commit/9123aeb6fcb14e0955ebe4e2a613802cfa0503ea
Author: Richard Henderson <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Rewrite helper_sve_ld1*_r using pages
Uses tlb_vaddr_to_host for correct operation with softmmu.
Optimize for accesses within a single page or pair of pages.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: f27d4dc2af0de9b7b45c955882b8420905c6efe8
https://github.com/qemu/qemu/commit/f27d4dc2af0de9b7b45c955882b8420905c6efe8
Author: Richard Henderson <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Rewrite helper_sve_ld[234]*_r
Use the same *_tlb primitives as we use for ld1.
For linux-user, this hoists the set of helper_retaddr. For softmmu,
hoists the computation of the current mmu_idx outside the loop,
fixes the endianness problem, and moves the main loop out of a
macro and into an inlined function.
Reviewed-by: Peter Maydell <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 9fd46c8362e0a45d04ccceae7051d06dd65c1d57
https://github.com/qemu/qemu/commit/9fd46c8362e0a45d04ccceae7051d06dd65c1d57
Author: Richard Henderson <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/sve_helper.c
Log Message:
-----------
target/arm: Rewrite helper_sve_st[1234]*_r
This fixes the endianness problem for softmmu, and moves the
main loop out of a macro and into an inlined function.
Reviewed-by: Peter Maydell <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7d0a57a2e1cea188b9023261a404d7a211117230
https://github.com/qemu/qemu/commit/7d0a57a2e1cea188b9023261a404d7a211117230
Author: Richard Henderson <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Split contiguous loads for endianness
We can choose the endianness at translation time, rather than
re-computing it at execution time.
Tested-by: Laurent Desnogues <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 28d57f2dc59c287e1c40239509b0a325fd00e32f
https://github.com/qemu/qemu/commit/28d57f2dc59c287e1c40239509b0a325fd00e32f
Author: Richard Henderson <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Split contiguous stores for endianness
We can choose the endianness at translation time, rather than
re-computing it at execution time.
Tested-by: Laurent Desnogues <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: d4f75f25b43041e7a46d12352b3c70ae457d8cea
https://github.com/qemu/qemu/commit/d4f75f25b43041e7a46d12352b3c70ae457d8cea
Author: Richard Henderson <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Rewrite vector gather loads
This fixes the endianness problem for softmmu, and moves
the main loop out of a macro and into an inlined function.
Reviewed-by: Peter Maydell <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 78cf1b886aa1b95c97fc5114641515c2892bb240
https://github.com/qemu/qemu/commit/78cf1b886aa1b95c97fc5114641515c2892bb240
Author: Richard Henderson <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Rewrite vector gather stores
This fixes the endianness problem for softmmu, and moves
the main loop out of a macro and into an inlined function.
Reviewed-by: Peter Maydell <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 116347ce20bb7b5cac17bf2b0e6f607530b50862
https://github.com/qemu/qemu/commit/116347ce20bb7b5cac17bf2b0e6f607530b50862
Author: Richard Henderson <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Rewrite vector gather first-fault loads
This implements the feature for softmmu, and moves the
main loop out of a macro and into a function.
Reviewed-by: Peter Maydell <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 500d04843ba953dc4560e44f04001efec38c14a6
https://github.com/qemu/qemu/commit/500d04843ba953dc4560e44f04001efec38c14a6
Author: Richard Henderson <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/internals.h
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Pass TCGMemOpIdx to sve memory helpers
There is quite a lot of code required to compute cpu_mem_index,
or even put together the full TCGMemOpIdx. This can easily be
done at translation time.
Reviewed-by: Peter Maydell <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 4730fb85035e99c909db7d14ef76cd17f28f4423
https://github.com/qemu/qemu/commit/4730fb85035e99c909db7d14ef76cd17f28f4423
Author: Peter Maydell <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Define new TBFLAG for v8M stack checking
The Arm v8M architecture includes hardware stack limit checking.
When certain instructions update the stack pointer, if the new
value of SP is below the limit set in the associated limit register
then an exception is taken. Add a TB flag that tracks whether
the limit-checking code needs to be emitted.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Commit: 86f026de22d8854eecc004af44895de74225794f
https://github.com/qemu/qemu/commit/86f026de22d8854eecc004af44895de74225794f
Author: Peter Maydell <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Define new EXCP type for v8M stack overflows
Define EXCP_STKOF, and arrange for it to cause us to take
a UsageFault with CFSR.STKOF set.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 5529bf188d996391ff52a0e1801daf9c6a6bfcb0
https://github.com/qemu/qemu/commit/5529bf188d996391ff52a0e1801daf9c6a6bfcb0
Author: Peter Maydell <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Move v7m_using_psp() to internals.h
We're going to want v7m_using_psp() in op_helper.c in the
next patch, so move it from helper.c to internals.h.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 5520318939fea5d659bf808157cd726cb967b761
https://github.com/qemu/qemu/commit/5520318939fea5d659bf808157cd726cb967b761
Author: Peter Maydell <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/helper.h
M target/arm/internals.h
M target/arm/op_helper.c
M target/arm/translate.c
Log Message:
-----------
target/arm: Add v8M stack checks on ADD/SUB/MOV of SP
Add code to insert calls to a helper function to do the stack
limit checking when we handle these forms of instruction
that write to SP:
* ADD (SP plus immediate)
* ADD (SP plus register)
* SUB (SP minus immediate)
* SUB (SP minus register)
* MOV (register)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: a2d12f0f34e9c5ef8a193556fde983aa186fa73a
https://github.com/qemu/qemu/commit/a2d12f0f34e9c5ef8a193556fde983aa186fa73a
Author: Peter Maydell <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Add some comments in Thumb decode
Add some comments to the Thumb decoder indicating what bits
of the instruction have been decoded at various points in
the code.
This is not an exhaustive set of comments; we're gradually
adding comments as we work with particular bits of the code.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: c32da7aa6205a5ff62ae8d5062f7cad0eae4c1fd
https://github.com/qemu/qemu/commit/c32da7aa6205a5ff62ae8d5062f7cad0eae4c1fd
Author: Peter Maydell <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Add v8M stack checks on exception entry
Add checks for breaches of the v8M stack limit when the
stack pointer is decremented to push the exception frame
for exception entry.
Note that the exception-entry case is unique in that the
stack pointer is updated to be the limit value if the limit
is hit (per rule R_ZLZG).
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 597610eb39f8a2d5c8146007c1ac37c623c23645
https://github.com/qemu/qemu/commit/597610eb39f8a2d5c8146007c1ac37c623c23645
Author: Peter Maydell <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
M target/arm/op_helper.c
Log Message:
-----------
target/arm: Add v8M stack limit checks on NS function calls
Check the v8M stack limits when pushing the frame for a
non-secure function call via BLXNS.
In order to be able to generate the exception we need to
promote raise_exception() from being local to op_helper.c
so we can call it from helper.c.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 910d7692e5b60f2c2d08cc3d6d36076e85b6a69d
https://github.com/qemu/qemu/commit/910d7692e5b60f2c2d08cc3d6d36076e85b6a69d
Author: Peter Maydell <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Add v8M stack checks for LDRD/STRD (imm)
Add the v8M stack checks for:
* LDRD (immediate)
* STRD (immediate)
Loads and stores are more complicated than ADD/SUB/MOV, because we
must ensure that memory accesses below the stack limit are not
performed, so we can't simply do the check when we actually update
SP.
For these instructions, if the stack limit check triggers
we must not:
* perform any memory access below the SP limit
* update PC, SP or the load/store base register
but it is IMPDEF whether we:
* perform any accesses above or equal to the SP limit
* update destination registers for loads
For QEMU we choose to always check the limit before doing any other
part of the load or store, so we won't update any registers or
perform any memory accesses.
It is UNKNOWN whether the limit check triggers for a load or store
where the initial SP value is below the limit and one of the stores
would be below the limit, but the writeback moves SP to above the
limit. For QEMU we choose to trigger the check in this situation.
Note that limit checks happen only for loads and stores which update
SP via writeback; they do not happen for loads and stores which
simply use SP as a base register.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 7c0ed88e7d6bee3e55c3d8935c46226cb544191a
https://github.com/qemu/qemu/commit/7c0ed88e7d6bee3e55c3d8935c46226cb544191a
Author: Peter Maydell <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Add v8M stack checks for Thumb2 LDM/STM
Add the v8M stack checks for:
* LDM (T2 encoding)
* STM (T2 encoding)
This includes the 32-bit encodings of the instructions listed
in v8M ARM ARM rule R_YVWT as
* LDM, LDMIA, LDMFD
* LDMDB, LDMEA
* POP (multiple registers)
* PUSH (muliple registers)
* STM, STMIA, STMEA
* STMDB, STMFD
We perform the stack limit before doing any other part
of the load or store.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 0bc003bad9752afc61624cb680226c922f34f82c
https://github.com/qemu/qemu/commit/0bc003bad9752afc61624cb680226c922f34f82c
Author: Peter Maydell <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Add v8M stack checks for T32 load/store single
Add v8M stack checks for the instructions in the T32
"load/store single" encoding class: these are the
"immediate pre-indexed" and "immediate, post-indexed"
LDR and STR instructions.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: aa369e5c08bbe2748d2be96f13f4ef469a4d3080
https://github.com/qemu/qemu/commit/aa369e5c08bbe2748d2be96f13f4ef469a4d3080
Author: Peter Maydell <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Add v8M stack checks for Thumb push/pop
Add v8M stack checks for the 16-bit Thumb push/pop
encodings: STMDB, STMFD, LDM, LDMIA, LDMFD.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 8a954faf5412d5073d585d85a1da63a09bb5d84e
https://github.com/qemu/qemu/commit/8a954faf5412d5073d585d85a1da63a09bb5d84e
Author: Peter Maydell <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Add v8M stack checks for VLDM/VSTM
Add the v8M stack checks for the VLDM/VSTM
(aka VPUSH/VPOP) instructions. This code is currently
unreachable because we haven't yet implemented M profile
floating point support, but since the change is simple,
we add it now because otherwise we're likely to forget to
do it later.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 167765f0739e4a108e8c2e2ff2f37917df5658f9
https://github.com/qemu/qemu/commit/167765f0739e4a108e8c2e2ff2f37917df5658f9
Author: Peter Maydell <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Add v8M stack checks for MSR to SP_NS
Updating the NS stack pointer via MSR to SP_NS should include
a check whether the new SP value is below the stack limit.
No other kinds of update to the various stack pointer and
limit registers via MSR should perform a check.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 74e2e59b8d0a68be0956310fc349179c89fd7be0
https://github.com/qemu/qemu/commit/74e2e59b8d0a68be0956310fc349179c89fd7be0
Author: Peter Maydell <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M hw/display/bcm2835_fb.c
Log Message:
-----------
hw/display/bcm2835_fb: Silence Coverity warning about multiply overflow
Coverity complains (CID 1395628) that the multiply in the calculation
of the framebuffer base is performed as 32x32 but then used in a
context that takes a 64-bit hwaddr. This can't actually ever
overflow the 32-bit result, because of the constraints placed on
the s->config values in bcm2835_fb_validate_config(). But we
can placate Coverity anyway, by explicitly casting one of the
inputs to a hwaddr, so the whole expression is calculated with
64-bit arithmetic.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Message-id: address@hidden
Commit: 7c69b7c849641a39ba3defa40d384a2ba24cd7a2
https://github.com/qemu/qemu/commit/7c69b7c849641a39ba3defa40d384a2ba24cd7a2
Author: Peter Maydell <address@hidden>
Date: 2018-10-08 (Mon, 08 Oct 2018)
Changed paths:
M hw/arm/virt.c
M hw/display/bcm2835_fb.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper-sve.h
M target/arm/helper.c
M target/arm/helper.h
M target/arm/internals.h
M target/arm/kvm.c
M target/arm/kvm_arm.h
M target/arm/op_helper.c
M target/arm/sve_helper.c
M target/arm/translate-a64.c
M target/arm/translate-sve.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20181008'
into staging
target-arm queue:
* target/arm: fix error in a code comment
* virt: Suppress external aborts on virt-2.10 and earlier
* target/arm: Correct condition for v8M callee stack push
* target/arm: Don't read r4 from v8M exception stackframe twice
* target/arm: Support SVE in system emulation mode
* target/arm: Implement v8M hardware stack limit checking
* hw/display/bcm2835_fb: Silence Coverity warning about multiply overflow
# gpg: Signature made Mon 08 Oct 2018 14:58:53 BST
# gpg: using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20181008: (33 commits)
hw/display/bcm2835_fb: Silence Coverity warning about multiply overflow
target/arm: Add v8M stack checks for MSR to SP_NS
target/arm: Add v8M stack checks for VLDM/VSTM
target/arm: Add v8M stack checks for Thumb push/pop
target/arm: Add v8M stack checks for T32 load/store single
target/arm: Add v8M stack checks for Thumb2 LDM/STM
target/arm: Add v8M stack checks for LDRD/STRD (imm)
target/arm: Add v8M stack limit checks on NS function calls
target/arm: Add v8M stack checks on exception entry
target/arm: Add some comments in Thumb decode
target/arm: Add v8M stack checks on ADD/SUB/MOV of SP
target/arm: Move v7m_using_psp() to internals.h
target/arm: Define new EXCP type for v8M stack overflows
target/arm: Define new TBFLAG for v8M stack checking
target/arm: Pass TCGMemOpIdx to sve memory helpers
target/arm: Rewrite vector gather first-fault loads
target/arm: Rewrite vector gather stores
target/arm: Rewrite vector gather loads
target/arm: Split contiguous stores for endianness
target/arm: Split contiguous loads for endianness
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/079911cb6e26...7c69b7c84964
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