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[Qemu-commits] [qemu/qemu] 3b8afb: hw/s390x/ipl: Fix alignment problems
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[Qemu-commits] [qemu/qemu] 3b8afb: hw/s390x/ipl: Fix alignment problems of S390IPLSta... |
Date: |
Fri, 05 Oct 2018 09:53:46 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 3b8afb41bc8eef42c3e2d3ed78ca5fe94ebe76e8
https://github.com/qemu/qemu/commit/3b8afb41bc8eef42c3e2d3ed78ca5fe94ebe76e8
Author: Thomas Huth <address@hidden>
Date: 2018-10-04 (Thu, 04 Oct 2018)
Changed paths:
M hw/s390x/ipl.h
Log Message:
-----------
hw/s390x/ipl: Fix alignment problems of S390IPLState members
The IplParameterBlock and QemuIplParameters structures are declared with
QEMU_PACKED, so the compiler assumes that the structures do not need to
be aligned in memory. Since the are listed after a "bool" within the
S390IPLState, the IplParameterBlock and QemuIplParameters are also indeed
mis-aligned in memory. This causes problems on Sparc during migration, since
we use VMSTATE_UINT16 in vmstate_iplb to access the devno member for example,
and the corresponding migration functions (like qemu_get_be16s) then try to
access a 16-bit value from a misaligned memory address.
The easiest solution to fix this problem is to move the packed structures
to the beginning of the S390IPLState, right after the DeviceState of course
which has to stay first for QOM reasons. But since DeviceState is a non-packed
struct, we can be sure that it will be padded to the correct alignment at the
end. If not, the QEMU_BUILD_BUG_MSG in this patch will tell us.
Signed-off-by: Thomas Huth <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 729315ebca0811c11e937d00231f8e05de5b446d
https://github.com/qemu/qemu/commit/729315ebca0811c11e937d00231f8e05de5b446d
Author: Thomas Huth <address@hidden>
Date: 2018-10-04 (Thu, 04 Oct 2018)
Changed paths:
M hw/s390x/css.c
M include/hw/s390x/css.h
Log Message:
-----------
hw/s390x/css: Remove QEMU_PACKED from struct SenseId
The uint16_t member cu_type of struct SenseId is not naturally aligned,
and since the struct is marked with QEMU_PACKED, this can lead to
unaligned memory accesses - which does not work on architectures like
Sparc. Thus remove the QEMU_PACKED here and rather copy the struct
byte by byte when we do copy_sense_id_to_guest().
Signed-off-by: Thomas Huth <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: cb89b349074310ff9eb7ebe18a8ae24d7d9ea3fb
https://github.com/qemu/qemu/commit/cb89b349074310ff9eb7ebe18a8ae24d7d9ea3fb
Author: Thomas Huth <address@hidden>
Date: 2018-10-04 (Thu, 04 Oct 2018)
Changed paths:
M include/hw/s390x/css.h
M include/hw/s390x/ioinst.h
Log Message:
-----------
hw/s390x/ioinst: Fix alignment problem in struct SubchDev
struct SubchDev embeds several other structures which are marked with
QEMU_PACKED. This causes the compiler to not care for proper alignment
of these structures. When we later pass around pointers to the unaligned
struct members during migration, this causes problems on host architectures
like Sparc that can not do unaligned memory access.
Most of the structs in ioinst.h are naturally aligned, so we can fix
most of the problem by removing the QEMU_PACKED statements (and use
QEMU_BUILD_BUG_MSG() statements instead to make sure that there is no
padding). However, for the struct SCHIB, we have to keep the QEMU_PACKED
since the compiler adds some padding here otherwise. Move this struct
to the beginning of struct SubchDev instead to fix the alignment problem
here, too.
Signed-off-by: Thomas Huth <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 28221f9c999a9b34f58d94599da9c229df9a4fed
https://github.com/qemu/qemu/commit/28221f9c999a9b34f58d94599da9c229df9a4fed
Author: Janosch Frank <address@hidden>
Date: 2018-10-04 (Thu, 04 Oct 2018)
Changed paths:
M hw/s390x/s390-virtio-ccw.c
M include/hw/s390x/s390-virtio-ccw.h
M target/s390x/kvm.c
Log Message:
-----------
s390x: Fence huge pages prior to 3.1
As the kernel has no way of disallowing the start of a huge page
backed VM, we can migrate a running huge backed VM to a host that has
no huge page KVM support.
Let's glue huge page support support to the 3.1 machine, so we do not
migrate to a destination host that doesn't have QEMU huge page support
and can stop migration if KVM doesn't indicate support.
Signed-off-by: Janosch Frank <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: ae4b5a5472ede9c92b83fa908c2ec63e80b64ced
https://github.com/qemu/qemu/commit/ae4b5a5472ede9c92b83fa908c2ec63e80b64ced
Author: Pavel Zbitskiy <address@hidden>
Date: 2018-10-04 (Thu, 04 Oct 2018)
Changed paths:
M target/s390x/translate.c
Log Message:
-----------
target/s390x: exception on non-aligned LPSW(E)
Both LPSW and LPSWE should raise a specification exception when their
operand is not doubleword aligned.
Signed-off-by: Pavel Zbitskiy <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 52341ed61d3a7b84602f6ee6b4234027ed5e6172
https://github.com/qemu/qemu/commit/52341ed61d3a7b84602f6ee6b4234027ed5e6172
Author: David Hildenbrand <address@hidden>
Date: 2018-10-04 (Thu, 04 Oct 2018)
Changed paths:
M target/s390x/excp_helper.c
M target/s390x/interrupt.c
M target/s390x/kvm.c
M target/s390x/tcg-stub.c
M target/s390x/tcg_s390x.h
Log Message:
-----------
s390x: move tcg_s390_program_interrupt() into TCG code and mark it noreturn
Move it into TCG-only code and provide a stub. Turn it into noreturn.
As Richard noted, we currently don't log the psw.addr before restoring
the state, fix that by moving (duplicating) the qemu_log_mask in the
tcg/kvm handlers.
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: bbf6ea3bd961970785a583117ac1c0b84a8ee736
https://github.com/qemu/qemu/commit/bbf6ea3bd961970785a583117ac1c0b84a8ee736
Author: David Hildenbrand <address@hidden>
Date: 2018-10-04 (Thu, 04 Oct 2018)
Changed paths:
M target/s390x/cpu.h
M target/s390x/excp_helper.c
M target/s390x/fpu_helper.c
M target/s390x/helper.h
M target/s390x/tcg-stub.c
M target/s390x/tcg_s390x.h
M target/s390x/translate.c
Log Message:
-----------
s390x/tcg: factor out and fix DATA exception injection
The DXC is to be stored in the low core, and only in the FPC in case AFP
is enabled in CR0. Stub is not required in current code, but this way
we never run into problems.
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 13054739b5838c7ef9d2e6e88a68bbf914d63bfa
https://github.com/qemu/qemu/commit/13054739b5838c7ef9d2e6e88a68bbf914d63bfa
Author: David Hildenbrand <address@hidden>
Date: 2018-10-04 (Thu, 04 Oct 2018)
Changed paths:
M target/s390x/cpu.h
Log Message:
-----------
s390x/tcg: store in the TB flags if AFP is enabled
We exit the TB when changing the control registers, so just like PSW
bits, this should always be consistent for a TB.
Using the PSW bit semantic makes things a lot easier compared to
manually defining the spare, shifted bits.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 82d179336dd696d04495963ca007fa961496d924
https://github.com/qemu/qemu/commit/82d179336dd696d04495963ca007fa961496d924
Author: David Hildenbrand <address@hidden>
Date: 2018-10-04 (Thu, 04 Oct 2018)
Changed paths:
M target/s390x/insn-data.def
M target/s390x/translate.c
Log Message:
-----------
s390x/tcg: support flags for instructions
Storing flags for instructions allows us to efficiently verify certain
properties at a central point. Examples might later be handling if
AFP is disabled in CR0, we are not in problem state, or if vector
instructions are disabled in CR0.
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: ca5f31a0f27d265f2220ad43913f70280e8753a2
https://github.com/qemu/qemu/commit/ca5f31a0f27d265f2220ad43913f70280e8753a2
Author: David Hildenbrand <address@hidden>
Date: 2018-10-04 (Thu, 04 Oct 2018)
Changed paths:
M target/s390x/insn-data.def
M target/s390x/translate.c
Log Message:
-----------
s390x/tcg: add instruction flags for floating point instructions
These flags allow us to later on detect if a DATA program interrupt
is to be injected, and which DXC (1,2,3) is to be used.
Interestingly, some support FP instructions are considered as HFP
instructions (I assume simply because they were available very early).
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Acked-by: Thomas Huth <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: db0504154ef1feedd135f25f8ca6e9abb5d00bbb
https://github.com/qemu/qemu/commit/db0504154ef1feedd135f25f8ca6e9abb5d00bbb
Author: David Hildenbrand <address@hidden>
Date: 2018-10-04 (Thu, 04 Oct 2018)
Changed paths:
M target/s390x/translate.c
Log Message:
-----------
s390x/tcg: check for AFP-register, BFP and DFP data exceptions
With the annotated functions, we can now easily check this at a central
place.
DXC 1 is to be injected if an AFP register is used (for a HFP AND FPS
instruction) when AFP is disabled.
DXC 2 is to be injected if a BFP instruction is used when AFP is
disabled.
DXC 3 is to be injected if a DFP instruction is used when AFP is
disabled.
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: b51cc1d826f3e86f790117d21d2bf1a3fb03b5a4
https://github.com/qemu/qemu/commit/b51cc1d826f3e86f790117d21d2bf1a3fb03b5a4
Author: David Hildenbrand <address@hidden>
Date: 2018-10-04 (Thu, 04 Oct 2018)
Changed paths:
M target/s390x/insn-data.def
M target/s390x/translate.c
Log Message:
-----------
s390x/tcg: handle privileged instructions via flags
Let's check this also at a central place.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Acked-by: Thomas Huth <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: eba7170b55ba77a391b2b1b9cd49ffbac6561b0d
https://github.com/qemu/qemu/commit/eba7170b55ba77a391b2b1b9cd49ffbac6561b0d
Author: David Hildenbrand <address@hidden>
Date: 2018-10-04 (Thu, 04 Oct 2018)
Changed paths:
M target/s390x/translate.c
Log Message:
-----------
s390x/tcg: fix FP register pair checks
Valid register pairs are 0/2, 1/3, 4/6, 5/7, 8/10, 9/11, 12/14, 13/15.
R1/R2 always selects the lower number, so the current checks are not
correct as e.g. 2/4 could be selected as a pair.
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: 74fbae31cfff10066f241a8909caecd1195df614
https://github.com/qemu/qemu/commit/74fbae31cfff10066f241a8909caecd1195df614
Author: David Hildenbrand <address@hidden>
Date: 2018-10-04 (Thu, 04 Oct 2018)
Changed paths:
M target/s390x/translate.c
Log Message:
-----------
s390x/tcg: refactor specification checking
We can fit this nicely into less LOC, without harming readability.
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: b576d582ea2b03f4eada186fff59308d22b40a6a
https://github.com/qemu/qemu/commit/b576d582ea2b03f4eada186fff59308d22b40a6a
Author: Thomas Huth <address@hidden>
Date: 2018-10-04 (Thu, 04 Oct 2018)
Changed paths:
M hw/s390x/s390-pci-bus.c
Log Message:
-----------
hw/s390x/s390-pci-bus: Convert sysbus init function to realize function
The SysBusDeviceClass->init() interface is considered as a legacy interface
and there are currently some efforts going on to get rid of it. Thus let's
convert the init function in the s390x code to realize() instead.
Signed-off-by: Thomas Huth <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>
Commit: ae7a4c0a4604bcfed40170db6cca576c44d872a2
https://github.com/qemu/qemu/commit/ae7a4c0a4604bcfed40170db6cca576c44d872a2
Author: Peter Maydell <address@hidden>
Date: 2018-10-05 (Fri, 05 Oct 2018)
Changed paths:
M hw/s390x/css.c
M hw/s390x/ipl.h
M hw/s390x/s390-pci-bus.c
M hw/s390x/s390-virtio-ccw.c
M include/hw/s390x/css.h
M include/hw/s390x/ioinst.h
M include/hw/s390x/s390-virtio-ccw.h
M target/s390x/cpu.h
M target/s390x/excp_helper.c
M target/s390x/fpu_helper.c
M target/s390x/helper.h
M target/s390x/insn-data.def
M target/s390x/interrupt.c
M target/s390x/kvm.c
M target/s390x/tcg-stub.c
M target/s390x/tcg_s390x.h
M target/s390x/translate.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20181004' into staging
Various s390x updates:
- fix several struct definitions so that sparc hosts do not trip over
unaligned accesses
- fence enabling huge pages for pre-3.1 machines
- sysbus init -> realize conversion
- fixes and improvements in tcg (instruction flags and AFP registers)
# gpg: Signature made Thu 04 Oct 2018 16:22:20 BST
# gpg: using RSA key DECF6B93C6F02FAF
# gpg: Good signature from "Cornelia Huck <address@hidden>"
# gpg: aka "Cornelia Huck <address@hidden>"
# gpg: aka "Cornelia Huck <address@hidden>"
# gpg: aka "Cornelia Huck <address@hidden>"
# gpg: aka "Cornelia Huck <address@hidden>"
# Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF
* remotes/cohuck/tags/s390x-20181004:
hw/s390x/s390-pci-bus: Convert sysbus init function to realize function
s390x/tcg: refactor specification checking
s390x/tcg: fix FP register pair checks
s390x/tcg: handle privileged instructions via flags
s390x/tcg: check for AFP-register, BFP and DFP data exceptions
s390x/tcg: add instruction flags for floating point instructions
s390x/tcg: support flags for instructions
s390x/tcg: store in the TB flags if AFP is enabled
s390x/tcg: factor out and fix DATA exception injection
s390x: move tcg_s390_program_interrupt() into TCG code and mark it noreturn
target/s390x: exception on non-aligned LPSW(E)
s390x: Fence huge pages prior to 3.1
hw/s390x/ioinst: Fix alignment problem in struct SubchDev
hw/s390x/css: Remove QEMU_PACKED from struct SenseId
hw/s390x/ipl: Fix alignment problems of S390IPLState members
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/d21ee59ae5b6...ae7a4c0a4604
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