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[Qemu-commits] [qemu/qemu] 094609: target/xtensa: extract test for an il


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 094609: target/xtensa: extract test for an illegal instruc...
Date: Tue, 02 Oct 2018 01:42:40 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 0946097051713031db1ff884c67081f291210ee2
      
https://github.com/qemu/qemu/commit/0946097051713031db1ff884c67081f291210ee2
  Author: Max Filippov <address@hidden>
  Date:   2018-10-01 (Mon, 01 Oct 2018)

  Changed paths:
    M target/xtensa/cpu.h
    M target/xtensa/helper.c
    M target/xtensa/helper.h
    M target/xtensa/op_helper.c
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: extract test for an illegal instruction

- TB flags: add XTENSA_TBFLAG_CWOE that corresponds to the architectural
  CWOE state;
- entry: move CWOE check from the helper to the test_ill_entry;
- retw: move CWOE check from the helper to the test_ill_retw;
- separate instruction disassembly loop and translation loop; save
  disassembly results in local array;

Signed-off-by: Max Filippov <address@hidden>


  Commit: 21a2dad5c40d9f1b3f82e73c9fcc35166ef4d57c
      
https://github.com/qemu/qemu/commit/21a2dad5c40d9f1b3f82e73c9fcc35166ef4d57c
  Author: Max Filippov <address@hidden>
  Date:   2018-10-01 (Mon, 01 Oct 2018)

  Changed paths:
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: extract test for privileged instruction

- mark privileged instructions;
- put single privileged instruction check after disassembly loop;
- translate_[di]cache: drop parameter 0, shift parameters one down;

Signed-off-by: Max Filippov <address@hidden>


  Commit: 4c6ec5f3cd88cb27a4e40a480b34e433a725dc05
      
https://github.com/qemu/qemu/commit/4c6ec5f3cd88cb27a4e40a480b34e433a725dc05
  Author: Max Filippov <address@hidden>
  Date:   2018-10-01 (Mon, 01 Oct 2018)

  Changed paths:
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: extract test for syscall instruction

- mark syscall instruction;
- put syscall exception check right after privileged exception check;

Signed-off-by: Max Filippov <address@hidden>


  Commit: 15477819427f5d2f0eddd4daba4159dee5f3b2ec
      
https://github.com/qemu/qemu/commit/15477819427f5d2f0eddd4daba4159dee5f3b2ec
  Author: Max Filippov <address@hidden>
  Date:   2018-10-01 (Mon, 01 Oct 2018)

  Changed paths:
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: extract test for debug exception

- mark break and break.n instructions;
- collect debug cause bits from parameter 0 of instructions marked for
  debug exception;
- put debug exception check right after syscall check;

Signed-off-by: Max Filippov <address@hidden>


  Commit: 6416d16f7544c53ccb6ce7d74e8f01f502b558d3
      
https://github.com/qemu/qemu/commit/6416d16f7544c53ccb6ce7d74e8f01f502b558d3
  Author: Max Filippov <address@hidden>
  Date:   2018-10-01 (Mon, 01 Oct 2018)

  Changed paths:
    M target/xtensa/cpu.h
    M target/xtensa/op_helper.c
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: extract test for window overflow exception

- add ps.callinc to the TB flags, that allows testing all instructions
  for window overflow statically;
- drop gen_window_check* functions; replace them with get_window_check
  that accepts bitmask of used registers;
- add XtensaOpcodeOps::test_overflow that returns bitmask of implicitly
  used registers; use it for entry and call{,x}{4,8,12};
- drop window overflow test from the entry helper;
- drop parameter 0 from translate_[di]cache and use translate_nop for
  d/i cache opcodes that don't need memory accessibility check;
- add bitmask XtensaOpcodeOps::windowed_register_op that marks opcode
  arguments that refer to windowed registers;
- translate windowed_register_op mask to a mask of actually used
  registers in the disassembly loop;
- add check for window overflow right after the check for debug
  exception;

Signed-off-by: Max Filippov <address@hidden>


  Commit: f473019a97d7c890ddb816367dc9f89fdfefa22e
      
https://github.com/qemu/qemu/commit/f473019a97d7c890ddb816367dc9f89fdfefa22e
  Author: Max Filippov <address@hidden>
  Date:   2018-10-01 (Mon, 01 Oct 2018)

  Changed paths:
    M target/xtensa/helper.h
    M target/xtensa/op_helper.c
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: extract test for window underflow exception

- mark retw and retw.n instructions;
- extract window inderflow test from retw helper;
- put underflow exception check generation right after the overflow
  check;

Signed-off-by: Max Filippov <address@hidden>


  Commit: 90d6494d130afa6de932fb1fa2eed8296d702836
      
https://github.com/qemu/qemu/commit/90d6494d130afa6de932fb1fa2eed8296d702836
  Author: Max Filippov <address@hidden>
  Date:   2018-10-01 (Mon, 01 Oct 2018)

  Changed paths:
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: extract test for alloca exception

- mark movsp instruction;
- put test for alloca exception right after the test for window
  underflow;

Signed-off-by: Max Filippov <address@hidden>


  Commit: 582fef0f47876da8968ac8d867922e040a02ebae
      
https://github.com/qemu/qemu/commit/582fef0f47876da8968ac8d867922e040a02ebae
  Author: Max Filippov <address@hidden>
  Date:   2018-10-01 (Mon, 01 Oct 2018)

  Changed paths:
    M target/xtensa/cpu.h
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: extract test for cpdisabled exception

- add XtensaOpcodeOps::coprocessor with bitmask of coprocessors used by
  the instruction;
- replace coprocessor id parameter of gen_check_cpenable with the
  bitmask of used coprocessors;
- collect coprocessor IDs used by an instruction in the disassembly
  loop;
- put test for coprocessor disabled exception after the alloca test;

Signed-off-by: Max Filippov <address@hidden>


  Commit: 4a038955dadd063b17c1d67bc2811707cfa56719
      
https://github.com/qemu/qemu/commit/4a038955dadd063b17c1d67bc2811707cfa56719
  Author: Max Filippov <address@hidden>
  Date:   2018-10-01 (Mon, 01 Oct 2018)

  Changed paths:
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: extract test for division by zero

- mark quos/quou/rems/remu instructions;
- drop parameter 0 from the translate_quou and split translate_remu from
  it;
- put test for division by zero exception right after the coprocessor
  exception test;

Signed-off-by: Max Filippov <address@hidden>


  Commit: 226444a8444b7b3269442505026c78766a6870db
      
https://github.com/qemu/qemu/commit/226444a8444b7b3269442505026c78766a6870db
  Author: Max Filippov <address@hidden>
  Date:   2018-10-01 (Mon, 01 Oct 2018)

  Changed paths:
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: extract unconditional TB termination

- mark all instructions that exit TB and require dynamic search for the
  next TB;
- put TB termination right after the instruction translation loop;

Signed-off-by: Max Filippov <address@hidden>


  Commit: 9dccbd1c69fd928a8eafbb171374029967143673
      
https://github.com/qemu/qemu/commit/9dccbd1c69fd928a8eafbb171374029967143673
  Author: Max Filippov <address@hidden>
  Date:   2018-10-01 (Mon, 01 Oct 2018)

  Changed paths:
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: change SR number checks to assertions

Opcode decoding with libisa takes care about range of valid group SRs,
like CCOMPARE, IBREAKA, DBREAKA or DBREAKC. Turn range checks in wsr
implementations into assertions.

Signed-off-by: Max Filippov <address@hidden>


  Commit: 06ec08a0be86c249163284dbb5e9f4828155fa83
      
https://github.com/qemu/qemu/commit/06ec08a0be86c249163284dbb5e9f4828155fa83
  Author: Max Filippov <address@hidden>
  Date:   2018-10-01 (Mon, 01 Oct 2018)

  Changed paths:
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: always end TB on CCOUNT access/CCOMPARE write

Currently we only end TB in icount mode, because access to CCOUNT or
write to CCOMPARE are IO operations. Simplify the behaviour a bit and
end TB unconditionally.

Signed-off-by: Max Filippov <address@hidden>


  Commit: bf525107749a9ea78e6ecdc3d98f34e82c8d8881
      
https://github.com/qemu/qemu/commit/bf525107749a9ea78e6ecdc3d98f34e82c8d8881
  Author: Max Filippov <address@hidden>
  Date:   2018-10-01 (Mon, 01 Oct 2018)

  Changed paths:
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: extract unconditional TB termination via slot 0

- mark instructions that require TB termination via slot 0;
- put TB termination right after the instruction translation loop, if
  termination w/o TB linking wasn't requested;

Signed-off-by: Max Filippov <address@hidden>


  Commit: c7159acbbeff32501cb54e52478f2621cfa008db
      
https://github.com/qemu/qemu/commit/c7159acbbeff32501cb54e52478f2621cfa008db
  Author: Max Filippov <address@hidden>
  Date:   2018-10-01 (Mon, 01 Oct 2018)

  Changed paths:
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: make rsr/wsr helpers return void

Now that all logic for TB termination is extracted from rsr/wsr their
return value is not used and may be dropped.

Signed-off-by: Max Filippov <address@hidden>


  Commit: d74624e59a6087ccf233843b936aedc9f8a8050a
      
https://github.com/qemu/qemu/commit/d74624e59a6087ccf233843b936aedc9f8a8050a
  Author: Max Filippov <address@hidden>
  Date:   2018-10-01 (Mon, 01 Oct 2018)

  Changed paths:
    M target/xtensa/translate.c

  Log Message:
  -----------
  target/xtensa: extract gen_check_interrupts call

- mark instructions that affect active IRQ level;
- put call for gen_check_interrupts right after the instruction
  translation; when FLIX is enabled it will need to appear before
  other exits from the TB as well;

Signed-off-by: Max Filippov <address@hidden>


  Commit: 8f09da690f843e2a886f400afc6314aecfdcf9a0
      
https://github.com/qemu/qemu/commit/8f09da690f843e2a886f400afc6314aecfdcf9a0
  Author: Peter Maydell <address@hidden>
  Date:   2018-10-02 (Tue, 02 Oct 2018)

  Changed paths:
    M target/xtensa/cpu.h
    M target/xtensa/helper.c
    M target/xtensa/helper.h
    M target/xtensa/op_helper.c
    M target/xtensa/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/xtensa/tags/20181001-xtensa' into 
staging

target/xtensa: preparation for FLIX support

Separate generation of per-instruction code (such as raising exceptions
and terminating TB) from per-opcode code.

# gpg: Signature made Mon 01 Oct 2018 19:14:34 BST
# gpg:                using RSA key 51F9CC91F83FA044
# gpg: Good signature from "Max Filippov <address@hidden>"
# gpg:                 aka "Max Filippov <address@hidden>"
# gpg:                 aka "Max Filippov <address@hidden>"
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20181001-xtensa:
  target/xtensa: extract gen_check_interrupts call
  target/xtensa: make rsr/wsr helpers return void
  target/xtensa: extract unconditional TB termination via slot 0
  target/xtensa: always end TB on CCOUNT access/CCOMPARE write
  target/xtensa: change SR number checks to assertions
  target/xtensa: extract unconditional TB termination
  target/xtensa: extract test for division by zero
  target/xtensa: extract test for cpdisabled exception
  target/xtensa: extract test for alloca exception
  target/xtensa: extract test for window underflow exception
  target/xtensa: extract test for window overflow exception
  target/xtensa: extract test for debug exception
  target/xtensa: extract test for syscall instruction
  target/xtensa: extract test for privileged instruction
  target/xtensa: extract test for an illegal instruction

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/e32e62f2533c...8f09da690f84
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