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[Qemu-commits] [qemu/qemu] 718a94: RISC-V: Update address bits to suppor
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[Qemu-commits] [qemu/qemu] 718a94: RISC-V: Update address bits to support sv39 and sv... |
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Mon, 24 Sep 2018 09:13:40 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 718a941e19005492015ae7aa5db04d853b5af877
https://github.com/qemu/qemu/commit/718a941e19005492015ae7aa5db04d853b5af877
Author: Michael Clark <address@hidden>
Date: 2018-09-04 (Tue, 04 Sep 2018)
Changed paths:
M target/riscv/cpu.h
Log Message:
-----------
RISC-V: Update address bits to support sv39 and sv48
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Commit: c3b03e5800a7151d3c746f40efceabdfdae08f85
https://github.com/qemu/qemu/commit/c3b03e5800a7151d3c746f40efceabdfdae08f85
Author: Michael Clark <address@hidden>
Date: 2018-09-04 (Tue, 04 Sep 2018)
Changed paths:
M target/riscv/cpu_bits.h
M target/riscv/helper.c
Log Message:
-----------
RISC-V: Improve page table walker spec compliance
- Inline PTE_TABLE check for better readability
- Change access checks from ternary operator to if
- Improve readibility of User page U mode and SUM test
- Disallow non U mode from fetching from User pages
- Add reserved PTE flag check: W or W|X
- Add misaligned PPN check
- Set READ protection for PTE X flag and mstatus.mxr
- Use memory_region_is_ram in pte update
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Commit: d78940ec5d07d3b514f2fd8f941c58118fce2815
https://github.com/qemu/qemu/commit/d78940ec5d07d3b514f2fd8f941c58118fce2815
Author: Michael Clark <address@hidden>
Date: 2018-09-04 (Tue, 04 Sep 2018)
Changed paths:
M hw/riscv/sifive_plic.c
M include/hw/riscv/sifive_plic.h
Log Message:
-----------
RISC-V: Use atomic_cmpxchg to update PLIC bitmaps
The PLIC previously used a mutex to protect against concurrent
access to the claimed and pending bitfields. Instead of using
a mutex, we update the bitfields using atomic_cmpxchg.
Rename sifive_plic_num_irqs_pending to sifive_plic_irqs_pending
and add an early out if any interrupts are pending as the
count of pending interrupts is not used.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Commit: efbdbc26a9fc69c222113abd9b80aa38a036fb6b
https://github.com/qemu/qemu/commit/efbdbc26a9fc69c222113abd9b80aa38a036fb6b
Author: Michael Clark <address@hidden>
Date: 2018-09-04 (Tue, 04 Sep 2018)
Changed paths:
M target/riscv/helper.c
Log Message:
-----------
RISC-V: Simplify riscv_cpu_local_irqs_pending
This commit is intended to improve readability.
There is no change to the logic.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Commit: 6dbebd5545d2563ee74ec049983a7bf65f05d17f
https://github.com/qemu/qemu/commit/6dbebd5545d2563ee74ec049983a7bf65f05d17f
Author: Emilio G. Cota <address@hidden>
Date: 2018-09-05 (Wed, 05 Sep 2018)
Changed paths:
M target/riscv/translate.c
Log Message:
-----------
target/riscv: optimize cross-page direct jumps in softmmu
Signed-off-by: Emilio G. Cota <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Commit: 3070543349712715b6f9337391b1eb592e7524f4
https://github.com/qemu/qemu/commit/3070543349712715b6f9337391b1eb592e7524f4
Author: Emilio G. Cota <address@hidden>
Date: 2018-09-05 (Wed, 05 Sep 2018)
Changed paths:
M target/riscv/translate.c
Log Message:
-----------
target/riscv: optimize indirect branches
Signed-off-by: Emilio G. Cota <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Commit: ccf08e40bfeede0233c065645ca46efb0dd4c6bf
https://github.com/qemu/qemu/commit/ccf08e40bfeede0233c065645ca46efb0dd4c6bf
Author: Emilio G. Cota <address@hidden>
Date: 2018-09-05 (Wed, 05 Sep 2018)
Changed paths:
M target/riscv/translate.c
Log Message:
-----------
target/riscv: call gen_goto_tb on DISAS_TOO_MANY
Performance impact of this and the previous commits, measured with
the very-easy-to-cross-compile rv8-bench:
https://github.com/rv8-io/rv8-bench
Host: Intel(R) Core(TM) i7-4790K CPU @ 4.00GHz
- Key:
before: master
after1,2,3: the 3 commits in this series (i.e. 3 is this commit)
- User-mode:
bench before after1 after2 after3 final speedup
---------------------------------------------------------
aes 1.12s 1.12s 1.10s 1.00s 1.12
bigint 0.78s 0.78s 0.78s 0.78s 1
dhrystone 0.96s 0.97s 0.49s 0.49s 1.9591837
miniz 1.94s 1.94s 1.88s 1.86s 1.0430108
norx 0.51s 0.51s 0.49s 0.48s 1.0625
primes 0.85s 0.85s 0.84s 0.84s 1.0119048
qsort 4.87s 4.88s 1.86s 1.86s 2.6182796
sha512 0.76s 0.77s 0.64s 0.64s 1.1875
(after1 only applies to softmmu, so no surprises here)
- Full-system (fedora):
bench before after1 after2 after3 final speedup
---------------------------------------------------------
aes 2.68s 2.54s 2.60s 2.34s 1.1452991
bigint 1.61s 1.56s 1.55s 1.64s 0.98170732
dhrystone 1.78s 1.67s 1.25s 1.24s 1.4354839
miniz 3.53s 3.35s 3.28s 3.35s 1.0537313
norx 1.13s 1.09s 1.07s 1.06s 1.0660377
primes 15.37s 15.41s 15.20s 15.37s 1
qsort 7.20s 6.71s 3.85s 3.96s 1.8181818
sha512 1.07s 1.04s 0.90s 0.90s 1.1888889
SoftMMU slows things down, so the numbers are less sensitive.
Cross-page jumps improve things a little bit, though.
Note that I'm not showing here averages, just results from a
single run, so with primes there isn't much to worry about.
Signed-off-by: Emilio G. Cota <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Commit: 53f54508dae677bb88d5b7ac46ed05e7da41326e
https://github.com/qemu/qemu/commit/53f54508dae677bb88d5b7ac46ed05e7da41326e
Author: Alistair Francis <address@hidden>
Date: 2018-09-05 (Wed, 05 Sep 2018)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virtio: Set the soc device tree node as a simple-bus
To allow Linux to enumerate devices on the /soc/ node set it as a
"simple-bus".
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Commit: 117caacf9b427ef7d2161f15372e1572f1a384b3
https://github.com/qemu/qemu/commit/117caacf9b427ef7d2161f15372e1572f1a384b3
Author: Alistair Francis <address@hidden>
Date: 2018-09-05 (Wed, 05 Sep 2018)
Changed paths:
M hw/riscv/spike.c
Log Message:
-----------
hw/riscv/spike: Set the soc device tree node as a simple-bus
To allow Linux to enumerate devices on the /soc/ node set it as a
"simple-bus".
Signed-off-by: Alistair Francis <address@hidden>
Commit: 1ca79ece35a5bcdcefb5a2582bc6da91f0640bf2
https://github.com/qemu/qemu/commit/1ca79ece35a5bcdcefb5a2582bc6da91f0640bf2
Author: Igor Mammedov <address@hidden>
Date: 2018-09-05 (Wed, 05 Sep 2018)
Changed paths:
M target/riscv/cpu.h
Log Message:
-----------
riscv: remove define cpu_init()
cpu_init() was removed since 2.12, so drop the define that is now unused.
Signed-off-by: Igor Mammedov <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Commit: ee4402eae1e24f776c2b58dfbe7e26c7a41e06e4
https://github.com/qemu/qemu/commit/ee4402eae1e24f776c2b58dfbe7e26c7a41e06e4
Author: Peter Maydell <address@hidden>
Date: 2018-09-24 (Mon, 24 Sep 2018)
Changed paths:
M hw/riscv/sifive_plic.c
M hw/riscv/spike.c
M hw/riscv/virt.c
M include/hw/riscv/sifive_plic.h
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/helper.c
M target/riscv/translate.c
Log Message:
-----------
Merge remote-tracking branch
'remotes/alistair/tags/pull-riscv-pullreq-20180905' into staging
A misc collection of RISC-V related patches for 3.1.
# gpg: Signature made Wed 05 Sep 2018 23:06:55 BST
# gpg: using RSA key 21E10D29DF977054
# gpg: Good signature from "Alistair Francis <address@hidden>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg: It is not certain that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-pullreq-20180905:
riscv: remove define cpu_init()
hw/riscv/spike: Set the soc device tree node as a simple-bus
hw/riscv/virtio: Set the soc device tree node as a simple-bus
target/riscv: call gen_goto_tb on DISAS_TOO_MANY
target/riscv: optimize indirect branches
target/riscv: optimize cross-page direct jumps in softmmu
RISC-V: Simplify riscv_cpu_local_irqs_pending
RISC-V: Use atomic_cmpxchg to update PLIC bitmaps
RISC-V: Improve page table walker spec compliance
RISC-V: Update address bits to support sv39 and sv48
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/d5a515738ee2...ee4402eae1e2
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