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[Qemu-commits] [qemu/qemu] 2abdfe: softfloat: Add scaling int-to-float r
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[Qemu-commits] [qemu/qemu] 2abdfe: softfloat: Add scaling int-to-float routines |
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Date: |
Fri, 24 Aug 2018 06:45:54 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 2abdfe24402907e7e8c103bdd4166f26b74200c2
https://github.com/qemu/qemu/commit/2abdfe24402907e7e8c103bdd4166f26b74200c2
Author: Richard Henderson <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M fpu/softfloat.c
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: Add scaling int-to-float routines
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 2f6c74be593ec5219e54d7b4abd4e5a98d7f3efc
https://github.com/qemu/qemu/commit/2f6c74be593ec5219e54d7b4abd4e5a98d7f3efc
Author: Richard Henderson <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M fpu/softfloat.c
M include/fpu/softfloat.h
Log Message:
-----------
softfloat: Add scaling float-to-int routines
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: b9b903cf245e4df1199cc7b2b80381ef85a6b1ab
https://github.com/qemu/qemu/commit/b9b903cf245e4df1199cc7b2b80381ef85a6b1ab
Author: Richard Henderson <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Use the int-to-float-scale softfloat routines
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 323cd490845acf663159ca26e35cb977ad9b85a2
https://github.com/qemu/qemu/commit/323cd490845acf663159ca26e35cb977ad9b85a2
Author: Richard Henderson <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Use the float-to-int-scale softfloat routines
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7210918cade19b7c6f14c4403aac0fd381c07b1d
https://github.com/qemu/qemu/commit/7210918cade19b7c6f14c4403aac0fd381c07b1d
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/intc/arm_gic.c
Log Message:
-----------
hw/intc/arm_gic: Make per-cpu GICH memory regions 0x200 bytes large
Reduce the size of the per-cpu GICH memory regions from 0x1000
to 0x200. The registers only cover 0x200 bytes, and the Cortex-A15
wants to map them at a spacing of 0x200 bytes apart. Having the
region be too large interferes with mapping them like that, so
reduce it.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Commit: 33383e9bbb5e5d083d491d84197c60ca8d4a9b4f
https://github.com/qemu/qemu/commit/33383e9bbb5e5d083d491d84197c60ca8d4a9b4f
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/arm/vexpress.c
Log Message:
-----------
hw/arm/vexpress: Connect VIRQ and VFIQ
Connect the VIRQ and VFIQ lines from the GIC to the CPU;
these exist always for both CPU and GIC whether the
virtualization extensions are enabled or not, so we
can just unconditionally connect them.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Commit: 582c8f75a23376d50e9be4f2fa1d21356b32b0c6
https://github.com/qemu/qemu/commit/582c8f75a23376d50e9be4f2fa1d21356b32b0c6
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/arm/highbank.c
Log Message:
-----------
hw/arm/highbank: Connect VIRQ and VFIQ
Connect the VIRQ and VFIQ lines from the GIC to the CPU;
these exist always for both CPU and GIC whether the
virtualization extensions are enabled or not, so we
can just unconditionally connect them.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Commit: 256d3e21f22c2c285d8c170ea6488825cc7c7ae2
https://github.com/qemu/qemu/commit/256d3e21f22c2c285d8c170ea6488825cc7c7ae2
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/arm/fsl-imx6ul.c
Log Message:
-----------
hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ
Connect the VIRQ and VFIQ lines from the GIC to the CPU;
these exist always for both CPU and GIC whether the
virtualization extensions are enabled or not, so we
can just unconditionally connect them.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Commit: b558e295211deecdc769835a0a400f8aa59c53fd
https://github.com/qemu/qemu/commit/b558e295211deecdc769835a0a400f8aa59c53fd
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/arm/fsl-imx7.c
Log Message:
-----------
hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ
Connect the VIRQ and VFIQ lines from the GIC to the CPU;
these exist always for both CPU and GIC whether the
virtualization extensions are enabled or not, so we
can just unconditionally connect them.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Commit: ba3287d117066fef2ebfea9555197f94c950afc5
https://github.com/qemu/qemu/commit/ba3287d117066fef2ebfea9555197f94c950afc5
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/cpu/a15mpcore.c
Log Message:
-----------
hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up
For the A15MPCore internal peripheral object, we handle GIC
security extensions support by checking whether the CPUs
have EL3 enabled; if so then we enable it also on the GIC.
Handle the virtualization extensions in the same way: if the
CPU has EL2 then enable it on the GIC and wire up the
virtualization-specific memory regions and the maintenance
interrupt.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Commit: 3921019abc87bb1ceefb71a9b829614eb98d5ba9
https://github.com/qemu/qemu/commit/3921019abc87bb1ceefb71a9b829614eb98d5ba9
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/arm/vexpress.c
Log Message:
-----------
hw/arm/vexpress: Don't set info->secure_boot if CPU doesn't have EL3
Don't request that the arm_load_kernel() code should boot in secure
state if the CPU doesn't have a secure state. Currently this
doesn't make a difference because the boot.c code only examines
the secure_boot flag in code guarded by an ARM_FEATURE_EL3 check,
but upcoming changes for supporting booting into Hyp mode will
change that.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Commit: cac0d80809d9c323cb0ed06843804844c7e09f6b
https://github.com/qemu/qemu/commit/cac0d80809d9c323cb0ed06843804844c7e09f6b
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/arm/vexpress.c
Log Message:
-----------
hw/arm/vexpress: Add "virtualization" property controlling presence of EL2
Add a "virtualization" property to the vexpress-a15 board,
controlling presence of EL2. As with EL3, we default to
enabling it, but the user can disable it if they have an
older guest which can't cope with it being present.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Commit: 0e0456ab8895a5e85998904549e331d36c2692a5
https://github.com/qemu/qemu/commit/0e0456ab8895a5e85998904549e331d36c2692a5
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement RAZ/WI HACTLR2
The v8 AArch32 HACTLR2 register maps to bits [63:32] of ACTLR_EL2.
We implement ACTLR_EL2 as RAZ/WI, so make HACTLR2 also RAZ/WI.
(We put the regdef next to ACTLR_EL2 as a reminder in case we
ever make ACTLR_EL2 something other than RAZ/WI).
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Commit: ce4afed8396aabaf87cd42fbe8a4c14f7a9d5c10
https://github.com/qemu/qemu/commit/ce4afed8396aabaf87cd42fbe8a4c14f7a9d5c10
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement AArch32 HCR and HCR2
The AArch32 HCR and HCR2 registers alias HCR_EL2
bits [31:0] and [63:32]; implement them.
Since HCR2 exists in ARMv8 but not ARMv7, we need new
regdef arrays for "we have EL3, not EL2, we're ARMv8"
and "we have EL2, we're ARMv8" to hold the definitions.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Commit: dea8378bb3e86f2c6bd05afb3927619f7c51bb47
https://github.com/qemu/qemu/commit/dea8378bb3e86f2c6bd05afb3927619f7c51bb47
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Factor out code for taking an AArch32 exception
Factor out the code which changes the CPU state so as to
actually take an exception to AArch32. We're going to want
to use this for handling exception entry to Hyp mode.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Commit: b9bc21ff9f9bb2d841adf1dc7f6f8ddfb9ab8b5e
https://github.com/qemu/qemu/commit/b9bc21ff9f9bb2d841adf1dc7f6f8ddfb9ab8b5e
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement support for taking exceptions to Hyp mode
Implement the necessary support code for taking exceptions
to Hyp mode in AArch32.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Commit: 829f9fd394ab082753308cbda165c13eaf8fae49
https://github.com/qemu/qemu/commit/829f9fd394ab082753308cbda165c13eaf8fae49
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry
On 32-bit exception entry, CPSR.J must always be set to 0
(see v7A Arm ARM DDI0406C.c B1.8.5). CPSR.IL must also
be cleared on 32-bit exception entry (see v8A Arm ARM
DDI0487C.a G1.10).
Clear these bits. (This fixes a bug which will never be noticed
by non-buggy guests.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Commit: 299953b989878d8f9ea38c7ea2d6760d49c0325e
https://github.com/qemu/qemu/commit/299953b989878d8f9ea38c7ea2d6760d49c0325e
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/arm/boot.c
Log Message:
-----------
hw/arm/boot: AArch32 kernels should be started in Hyp mode if available
The kernel booting specification for an AArch32 kernel requires that
it is booted in Hyp mode if available; otherwise the kernel can't
enable KVM. We were incorrectly leaving the kernel in SVC mode.
If we're booting an AArch32 kernel in the Nonsecure state and Hyp
mode is available, start in it.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
Commit: a1982f90a42b22f2858e7d8497ab7223cd49b65d
https://github.com/qemu/qemu/commit/a1982f90a42b22f2858e7d8497ab7223cd49b65d
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/misc/mps2-fpgaio.c
M include/hw/misc/mps2-fpgaio.h
Log Message:
-----------
hw/misc/mps2-fpgaio: Implement 1Hz and 100Hz counters
The MPS2 FPGAIO block includes some simple free-running counters.
Implement these.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 93739075d28ce81ae06237b48084f26a377cdcad
https://github.com/qemu/qemu/commit/93739075d28ce81ae06237b48084f26a377cdcad
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/misc/mps2-fpgaio.c
M include/hw/misc/mps2-fpgaio.h
Log Message:
-----------
hw/misc/mps2-fpgaio: Implement PSCNTR and COUNTER
In the MPS2 FPGAIO, PSCNTR is a free-running downcounter with
a reload value configured via the PRESCALE register, and
COUNTER counts up by 1 every time PSCNTR reaches zero.
Implement these counters.
We can just increment the counters migration subsection's
version ID because we only added it in the previous commit,
so no released QEMU versions will be using it.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 4f4c6206ca6eda478ec0377545ce26eb41090672
https://github.com/qemu/qemu/commit/4f4c6206ca6eda478ec0377545ce26eb41090672
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M MAINTAINERS
M default-configs/arm-softmmu.mak
M hw/timer/Makefile.objs
A hw/timer/cmsdk-apb-dualtimer.c
M hw/timer/trace-events
A include/hw/timer/cmsdk-apb-dualtimer.h
Log Message:
-----------
hw/timer/cmsdk-apb-dualtimer: Implement CMSDK dual timer module
The Arm Cortex-M System Design Kit includes a "dual-input timer module"
which combines two programmable down-counters. Implement a model
of this device.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 017d069d20866ed50f3422ade69d6cb60ea7522b
https://github.com/qemu/qemu/commit/017d069d20866ed50f3422ade69d6cb60ea7522b
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/arm/iotkit.c
M include/hw/arm/iotkit.h
Log Message:
-----------
hw/arm/iotkit: Wire up the dualtimer
Now we have a model of the CMSDK dual timer, we can wire it
up in the IoTKit.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 595c786b53b2cb515c2d5c1c7f2cc8c9d1721a80
https://github.com/qemu/qemu/commit/595c786b53b2cb515c2d5c1c7f2cc8c9d1721a80
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/arm/mps2.c
Log Message:
-----------
hw/arm/mps2: Wire up dual-timer in mps2-an385 and mps2-an511
The MPS2 FPGA images for the Cortex-M3 (mps2-an385 and mps2-511)
both include a CMSDK dual-timer module. Wire this up.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: d61e4e1ff721ff8ab611f8a81442f8af192c0961
https://github.com/qemu/qemu/commit/d61e4e1ff721ff8ab611f8a81442f8af192c0961
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/arm/iotkit.c
M include/hw/arm/iotkit.h
Log Message:
-----------
hw/arm/iotkit: Wire up the watchdogs
The IoTKit includes three different instances of the
CMSDK APB watchdog; create and wire them up.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: e2d203baba7bf202a64ee321c2754fe918ab909e
https://github.com/qemu/qemu/commit/e2d203baba7bf202a64ee321c2754fe918ab909e
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/arm/iotkit.c
M include/hw/arm/iotkit.h
Log Message:
-----------
hw/arm/iotkit: Wire up the S32KTIMER
The IoTKit has a CMSDK timer device that runs on the S32KCLK.
Create this and wire it up.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 75750e4d43c9c62d26d2b218a1e8c2f8efdf16c4
https://github.com/qemu/qemu/commit/75750e4d43c9c62d26d2b218a1e8c2f8efdf16c4
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M MAINTAINERS
M default-configs/arm-softmmu.mak
M hw/misc/Makefile.objs
A hw/misc/iotkit-sysctl.c
M hw/misc/trace-events
A include/hw/misc/iotkit-sysctl.h
Log Message:
-----------
hw/misc/iotkit-sysctl: Implement IoTKit system control element
The Arm IoTKit includes a system control element which
provides a block of read-only ID registers and a block
of read-write control registers. Implement a minimal
version of this.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: c667a25b324d086c7ea8002dbedeb10929d3b9da
https://github.com/qemu/qemu/commit/c667a25b324d086c7ea8002dbedeb10929d3b9da
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M MAINTAINERS
M default-configs/arm-softmmu.mak
M hw/misc/Makefile.objs
A hw/misc/iotkit-sysinfo.c
A include/hw/misc/iotkit-sysinfo.h
Log Message:
-----------
hw/misc/iotkit-sysinfo: Implement IoTKit system information block
Implement the IoTKit system control element's system information
block; this is just a pair of read-only version/config registers,
plus the usual PID/CID ID registers.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 06e65af39b451c6abe863986a9c60d69bde7718d
https://github.com/qemu/qemu/commit/06e65af39b451c6abe863986a9c60d69bde7718d
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/arm/iotkit.c
M include/hw/arm/iotkit.h
Log Message:
-----------
hw/misc/iotkit: Wire up the sysctl and sysinfo register blocks
Wire up the system control element's register banks
(sysctl and sysinfo).
This is the last of the previously completely unimplemented
components in the IoTKit.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 211e701d669e85f0e33ff6c4404a77519198f35e
https://github.com/qemu/qemu/commit/211e701d669e85f0e33ff6c4404a77519198f35e
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M MAINTAINERS
M default-configs/arm-softmmu.mak
M hw/misc/Makefile.objs
M hw/misc/trace-events
A hw/misc/tz-msc.c
A include/hw/misc/tz-msc.h
Log Message:
-----------
hw/misc/tz-msc: Model TrustZone Master Security Controller
Implement a model of the TrustZone Master Securtiy Controller,
as documented in the Arm CoreLink SIE-200 System IP for
Embedded TRM (DDI0571G):
https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g
The MSC is intended to sit in front of a device which can
be a bus master (eg a DMA controller) and programmably gate
its transactions. This allows a bus-mastering device to be
controlled by non-secure code but still restricted from
making accesses to addresses which are secure-only.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
Commit: 81a75deb1a2363a7f920e8982af4dc8c8d98a0ed
https://github.com/qemu/qemu/commit/81a75deb1a2363a7f920e8982af4dc8c8d98a0ed
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/misc/iotkit-secctl.c
M include/hw/misc/iotkit-secctl.h
Log Message:
-----------
hw/misc/iotkit-secctl: Wire up registers for controlling MSCs
The IoTKit does not have any Master Security Contollers itself,
but it does provide registers in the secure privilege control
block which allow control of MSCs in the external system.
Add support for these registers.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
Commit: 132b475a73574d8c6a7fa678716f2eead1002939
https://github.com/qemu/qemu/commit/132b475a73574d8c6a7fa678716f2eead1002939
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/arm/iotkit.c
M include/hw/arm/iotkit.h
Log Message:
-----------
hw/arm/iotkit: Wire up the lines for MSCs
The IoTKit doesn't have any MSCs itself but it does need
some wiring to connect the external signals from MSCs
in the outer board model up to the registers and the
NVIC IRQ line.
We also need to expose a MemoryRegion corresponding to
the AHB bus, so that MSCs in the outer board model can
use that as their downstream port. (In the FPGA this is
the "AHB Slave Expansion" ports shown in the block
diagram in the AN505 documentation.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
Commit: 28e56f05fc688917cf35c39c0ba97afb7f1ab0f3
https://github.com/qemu/qemu/commit/28e56f05fc688917cf35c39c0ba97afb7f1ab0f3
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Create PL081s and MSCs
The AN505 FPGA image includes four PL081 DMA controllers, each
of which is gated by a Master Security Controller that allows
the guest to prevent a non-secure DMA controller from accessing
memory that is used by secure guest code. Create and wire
up these devices.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
Commit: 1d52866f5a53feef036c2e8f9b3a6a30209d48a7
https://github.com/qemu/qemu/commit/1d52866f5a53feef036c2e8f9b3a6a30209d48a7
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M MAINTAINERS
M hw/ssi/pl022.c
A include/hw/ssi/pl022.h
Log Message:
-----------
hw/ssi/pl022: Allow use as embedded-struct device
Create a new include file for the pl022's device struct,
type macros, etc, so that it can be instantiated using
the "embedded struct" coding style.
While we're adding the new file to MAINTAINERS, add
also the .c file, which was missing an entry.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
Commit: 66d9aa790fa9d5c251dcbd5b8ff1db79e04dc06d
https://github.com/qemu/qemu/commit/66d9aa790fa9d5c251dcbd5b8ff1db79e04dc06d
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/ssi/pl022.c
Log Message:
-----------
hw/ssi/pl022: Set up reset function in class init
Currently the PL022 calls pl022_reset() from its class init
function. Make it register a DeviceState reset method instead,
so that we reset the device on system reset.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
Commit: 275ff67f40b60592d5c4e709ead1fe3e41b2ece5
https://github.com/qemu/qemu/commit/275ff67f40b60592d5c4e709ead1fe3e41b2ece5
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/ssi/pl022.c
Log Message:
-----------
hw/ssi/pl022: Don't directly call vmstate_register()
Use the DeviceState vmsd pointer rather than calling vmstate_register()
directly.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
Commit: 13391a563fc4048736d259b685676b02dd0ba52d
https://github.com/qemu/qemu/commit/13391a563fc4048736d259b685676b02dd0ba52d
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/ssi/pl022.c
Log Message:
-----------
hw/ssi/pl022: Use DeviceState::realize rather than SysBusDevice::init
Move from the legacy SysBusDevice::init method to using
DeviceState::realize.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
Commit: 139d941e5a61d29c895ab422031eb7fd8797e059
https://github.com/qemu/qemu/commit/139d941e5a61d29c895ab422031eb7fd8797e059
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/ssi/pl022.c
Log Message:
-----------
hw/ssi/pl022: Correct wrong value for PL022_INT_RT
The PL022 interrupt registers have bits allocated as:
0: ROR (receive overrun)
1: RT (receive timeout)
2: RX (receive FIFO half full or less)
3: TX (transmit FIFO half full or less)
A cut and paste error meant we had the wrong value for
the PL022_INT_RT constant. This bug doesn't affect device
behaviour, because we don't implement the receive timeout
feature and so never set that interrupt bit.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
Commit: 7d3912f54e74a16dc69c1e427396ebef58ff4976
https://github.com/qemu/qemu/commit/7d3912f54e74a16dc69c1e427396ebef58ff4976
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/ssi/pl022.c
Log Message:
-----------
hw/ssi/pl022: Correct wrong DMACR and ICR handling
In the PL022, register offset 0x20 is the ICR, a write-only
interrupt-clear register. Register offset 0x24 is DMACR, the DMA
control register. We were incorrectly implementing (a stub version
of) DMACR at 0x20, and not implementing anything at 0x24. Fix this
bug.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
Commit: 0d49759b97cb8b62079921c631179ebd6b716a27
https://github.com/qemu/qemu/commit/0d49759b97cb8b62079921c631179ebd6b716a27
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Instantiate SPI controllers
The SPI controllers in the MPS2 AN505 board are PL022s.
We have a model of the PL022, so create these devices.
We don't currently model the LCD controller that sits behind
one of the PL022s; the others are intended to control devices
that sit on the FPGA's general purpose SPI connector or
"shield" expansion connectors.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
Commit: cb159db944b290a4704603baa8b96facde634521
https://github.com/qemu/qemu/commit/cb159db944b290a4704603baa8b96facde634521
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/arm/mps2-tz.c
Log Message:
-----------
hw/arm/mps2-tz: Fix MPS2 SCC config register values
Some of the config register values we were setting for the MPS2 SCC
weren't correct:
* the SCC_AID bits [23:20] specify the FPGA build target board revision,
and the SCC_CFG4 register specifies the actual board revision, so
these should have matching values. Claim to be board revision C,
consistently -- we had the revision in the wrong part of SCC_AID.
* SCC_ID bits [15:4] should be 0x505, not decimal 505
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
Commit: d00584b7cfab3e38f8264bebfcb6fdb02c887ade
https://github.com/qemu/qemu/commit/d00584b7cfab3e38f8264bebfcb6fdb02c887ade
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Untabify translate.c
Untabify the arm translate.c. This affects only some lines,
mostly comments, in the iwMMXt code. We've never touched
that code in years, so it's not going to get fixed up
by our "change when touched" process, and a bulk change
is not going to be too disruptive.
This commit was produced using Emacs "untabify"; it is
a whitespace-only change.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 67aed15551f9814712d5ac25a155919b34fbd627
https://github.com/qemu/qemu/commit/67aed15551f9814712d5ac25a155919b34fbd627
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M target/arm/iwmmxt_helper.c
Log Message:
-----------
target/arm: Untabify iwmmxt_helper.c
Untabify the arm iwmmxt_helper.c. This affects only the iwMMXt code.
We've never touched that code in years, so it's not going to get
fixed up by our "change when touched" process, and a bulk change is
not going to be too disruptive.
This commit was produced using Emacs "untabify" (plus one
by-hand removal of a space to fix a checkpatch nit); it is
a whitespace-only change.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: 6e0fafe2ef02378c696e7cf84ef41511e3b3b81a
https://github.com/qemu/qemu/commit/6e0fafe2ef02378c696e7cf84ef41511e3b3b81a
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M target/arm/arm-semi.c
M target/arm/cpu.h
Log Message:
-----------
target/arm: Remove a handful of stray tabs
Following the bulk conversion of the iwMMXt code, there are
just a handful of hard coded tabs in target/arm; fix them.
This is a whitespace-only patch.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Commit: a02755ece0c0652480ed9d9f2f0355fdc3632fdb
https://github.com/qemu/qemu/commit/a02755ece0c0652480ed9d9f2f0355fdc3632fdb
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/display/bcm2835_fb.c
M hw/misc/bcm2835_property.c
M include/hw/display/bcm2835_fb.h
Log Message:
-----------
hw/misc/bcm2835_fb: Move config fields to their own struct
The handling of framebuffer properties in the bcm2835_property code
is a bit clumsy, because for each of the many fb related properties
we try to track the value we're about to set and whether we're going
to be setting a value, and then we hand all the new values off
to the framebuffer via a function which takes them all as separate
arguments. It would be simpler if the property code could easily
copy all the framebuffer's current settings, update them with
the new specified values and then ask the framebuffer to switch
to the new set.
As the first part of this refactoring, pull all the fb config
settings fields in BCM2835FBState out into their own struct.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 193100b571755023690787bcb1ebc91fcc03ed50
https://github.com/qemu/qemu/commit/193100b571755023690787bcb1ebc91fcc03ed50
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/display/bcm2835_fb.c
M hw/misc/bcm2835_property.c
M include/hw/display/bcm2835_fb.h
Log Message:
-----------
hw/misc/bcm2835_property: Track fb settings using BCM2835FBConfig
Refactor the fb property setting code so that rather than
using a set of pointers to local variables to track
whether a config value has been updated in the current
mbox and if so what its new value is, we just copy
all the current settings of the fb at the start, and
then update that copy as we go along, before asking
the fb to switch to it at the end.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: ea662f7cc8685622f393cdb7f7b7d243797a8af5
https://github.com/qemu/qemu/commit/ea662f7cc8685622f393cdb7f7b7d243797a8af5
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/display/bcm2835_fb.c
M include/hw/display/bcm2835_fb.h
Log Message:
-----------
hw/display/bcm2835_fb: Drop unused size and pitch fields
The BCM2835FBState struct has a 'pitch' field which is a
cached copy of xres * (bpp >> 3), and a 'size' field which is
a cached copy of pitch * yres. However we don't actually do
anything with these fields; delete them. We retain the
now-unused slots in the VMState struct for migration
compatibility.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 9e2938a0fdb6d85d79c9d97b1fe4e626925be9b5
https://github.com/qemu/qemu/commit/9e2938a0fdb6d85d79c9d97b1fe4e626925be9b5
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/display/bcm2835_fb.c
M include/hw/display/bcm2835_fb.h
Log Message:
-----------
hw/display/bcm2835_fb: Reset resolution, etc correctly
The bcm2835_fb's initial resolution and other parameters are set
via QOM properties. We should reset to those initial values on
device reset, which means we need to save the QOM property
values somewhere that they are not overwritten by guest
changes to the framebuffer configuration.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 9a1f03f4ee207d58674fc76aecff546551c9da76
https://github.com/qemu/qemu/commit/9a1f03f4ee207d58674fc76aecff546551c9da76
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/display/bcm2835_fb.c
M hw/misc/bcm2835_property.c
M include/hw/display/bcm2835_fb.h
Log Message:
-----------
hw/display/bcm2835_fb: Abstract out calculation of pitch, size
Abstract out the calculation of the pitch and size of the
framebuffer into functions that operate on the BCM2835FBConfig
struct -- these are about to get a little more complicated
when we add support for virtual and physical sizes differing.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 01f18af98b04dc3f47c37a150ae342fafd7337df
https://github.com/qemu/qemu/commit/01f18af98b04dc3f47c37a150ae342fafd7337df
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/display/bcm2835_fb.c
M hw/misc/bcm2835_property.c
M include/hw/display/bcm2835_fb.h
Log Message:
-----------
hw/display/bcm2835_fb: Fix handling of virtual framebuffer
The raspi framebuffir in bcm2835_fb supports the definition
of a virtual "viewport", which is smaller than the full
physical framebuffer size and at an adjustable offset within
it. Only the viewport area is sent to the screen. This allows
the guest to do things like double buffering, or scrolling
by adjusting the viewport origin. Currently QEMU doesn't
implement this at all.
Add support for this feature:
* the property mailbox code needs to distinguish the
virtual width/height from the physical width/height
* the framebuffer code needs to do something with the
virtual width/height/origin information
Note that the wiki documentation on the semantics of the
virtual and physical height and width has it the wrong way
around -- the virtual size is the size of the allocated
buffer, and the physical size is the size of the display,
so the virtual size is always the same as or larger than
the physical.
If the viewport size is set smaller than the physical
screen size, we ignore the viewport settings completely
and just display the physical screen area.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: f8add62c0c8826ca0fa90e6e3a80b810f63fe1dd
https://github.com/qemu/qemu/commit/f8add62c0c8826ca0fa90e6e3a80b810f63fe1dd
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/display/bcm2835_fb.c
M hw/misc/bcm2835_property.c
M include/hw/display/bcm2835_fb.h
Log Message:
-----------
hw/display/bcm2835_fb: Validate config settings
Validate the config settings that the guest tries to set.
The wiki page documentation is not really accurate here:
generally rather than failing requests to set bad parameters,
the hardware will just clip them to something sensible.
Validate the most important parameters: sizes and
the viewport offsets. This prevents the framebuffer
code from trying to read out-of-range memory.
In the property handling code, we validate the new parameters every
time we encounter a tag that sets them. This means we validate the
config multiple times if the request includes multiple config-setting
tags, but the code would require significant restructuring to do a
validation only once but still return the clipped settings for
get-parameter tags and the buffer allocation tag.
Validation of settings made via the older bcm2835_fb_mbox_push()
function will be done in the next commit.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: cfb7ba983857e40e88bd3219aaab908862581ac0
https://github.com/qemu/qemu/commit/cfb7ba983857e40e88bd3219aaab908862581ac0
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/display/bcm2835_fb.c
Log Message:
-----------
hw/display/bcm2835_fb: Validate bcm2835_fb_mbox_push() config
Refactor bcm2835_fb_mbox_push() to work by calling
bcm2835_fb_validate_config() and bcm2835_fb_reconfigure(),
so that config set this way is also validated.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 239cb6feb298a31faa40b7e97ced107bf9c2f2bf
https://github.com/qemu/qemu/commit/239cb6feb298a31faa40b7e97ced107bf9c2f2bf
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M hw/arm/mps2.c
Log Message:
-----------
hw/arm/mps2: Fix ID register errors on AN511 and AN385
Fix MPS2 SCC config register values for the mps2-an511
and mps2-an385 boards:
* the SCC_AID bits [23:20] specify the FPGA build target board revision,
and the SCC_CFG4 register specifies the actual board revision, so
these should have matching values. Claim to be board revision C,
consistently -- we had the revision in the wrong part of SCC_AID.
* SCC_ID bits [15:4] should be the board number in hex, not decimal
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: f4e8428b9a6ea440bba057ac03ba0355cd87a72f
https://github.com/qemu/qemu/commit/f4e8428b9a6ea440bba057ac03ba0355cd87a72f
Author: Peter Maydell <address@hidden>
Date: 2018-08-24 (Fri, 24 Aug 2018)
Changed paths:
M MAINTAINERS
M default-configs/arm-softmmu.mak
M fpu/softfloat.c
M hw/arm/boot.c
M hw/arm/fsl-imx6ul.c
M hw/arm/fsl-imx7.c
M hw/arm/highbank.c
M hw/arm/iotkit.c
M hw/arm/mps2-tz.c
M hw/arm/mps2.c
M hw/arm/vexpress.c
M hw/cpu/a15mpcore.c
M hw/display/bcm2835_fb.c
M hw/intc/arm_gic.c
M hw/misc/Makefile.objs
M hw/misc/bcm2835_property.c
M hw/misc/iotkit-secctl.c
A hw/misc/iotkit-sysctl.c
A hw/misc/iotkit-sysinfo.c
M hw/misc/mps2-fpgaio.c
M hw/misc/trace-events
A hw/misc/tz-msc.c
M hw/ssi/pl022.c
M hw/timer/Makefile.objs
A hw/timer/cmsdk-apb-dualtimer.c
M hw/timer/trace-events
M include/fpu/softfloat.h
M include/hw/arm/iotkit.h
M include/hw/display/bcm2835_fb.h
M include/hw/misc/iotkit-secctl.h
A include/hw/misc/iotkit-sysctl.h
A include/hw/misc/iotkit-sysinfo.h
M include/hw/misc/mps2-fpgaio.h
A include/hw/misc/tz-msc.h
A include/hw/ssi/pl022.h
A include/hw/timer/cmsdk-apb-dualtimer.h
M target/arm/arm-semi.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/iwmmxt_helper.c
M target/arm/translate.c
Log Message:
-----------
Merge remote-tracking branch
'remotes/pmaydell/tags/pull-target-arm-20180824-1' into staging
target-arm queue:
* Fix rounding errors in scaling float-to-int and int-to-float operations
* Connect virtualization-related IRQs and memory regions of GICv2
in boards that use Cortex-A7 or Cortex-A15
* Support taking exceptions to AArch32 Hyp mode
* Clear CPSR.IL and CPSR.J on 32-bit exception entry
(a minor bug fix that won't affect non-buggy guest code)
* mps2-an505: Implement various missing devices:
dual timer, watchdogs, counters in the FPGAIO registers,
some missing ID/control registers, TrustZone Master Security
Controllers, PL081 DMA controllers, PL022 SPI controllers
* correct ID register values for mps2-an385, -an511, -an505
* fix some hardcoded tabs in untouched backwaters of the
target/arm codebase
* raspi: Refactor framebuffer property handling code and implement
support for the virtual framebuffer/viewport
# gpg: Signature made Fri 24 Aug 2018 13:19:04 BST
# gpg: using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20180824-1: (52 commits)
hw/arm/mps2: Fix ID register errors on AN511 and AN385
hw/display/bcm2835_fb: Validate bcm2835_fb_mbox_push() config
hw/display/bcm2835_fb: Validate config settings
hw/display/bcm2835_fb: Fix handling of virtual framebuffer
hw/display/bcm2835_fb: Abstract out calculation of pitch, size
hw/display/bcm2835_fb: Reset resolution, etc correctly
hw/display/bcm2835_fb: Drop unused size and pitch fields
hw/misc/bcm2835_property: Track fb settings using BCM2835FBConfig
hw/misc/bcm2835_fb: Move config fields to their own struct
target/arm: Remove a handful of stray tabs
target/arm: Untabify iwmmxt_helper.c
target/arm: Untabify translate.c
hw/arm/mps2-tz: Fix MPS2 SCC config register values
hw/arm/mps2-tz: Instantiate SPI controllers
hw/ssi/pl022: Correct wrong DMACR and ICR handling
hw/ssi/pl022: Correct wrong value for PL022_INT_RT
hw/ssi/pl022: Use DeviceState::realize rather than SysBusDevice::init
hw/ssi/pl022: Don't directly call vmstate_register()
hw/ssi/pl022: Set up reset function in class init
hw/ssi/pl022: Allow use as embedded-struct device
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/6b699ae1be9f...f4e8428b9a6e
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