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[Qemu-commits] [qemu/qemu] cc71c7: spapr_cpu_core: vmstate_[un]register
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[Qemu-commits] [qemu/qemu] cc71c7: spapr_cpu_core: vmstate_[un]register per-CPU data ... |
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Date: |
Tue, 21 Aug 2018 07:57:23 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: cc71c7760e263f808c4240a725425671eeeb7e4d
https://github.com/qemu/qemu/commit/cc71c7760e263f808c4240a725425671eeeb7e4d
Author: Bharata B Rao <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M hw/ppc/spapr_cpu_core.c
Log Message:
-----------
spapr_cpu_core: vmstate_[un]register per-CPU data from (un)realizefn
VMStateDescription vmstate_spapr_cpu_state was added by commit
b94020268e0b6 (spapr_cpu_core: migrate per-CPU data) to migrate per-CPU
data with the required vmstate registration and unregistration calls.
However the unregistration is being done only from vcpu creation error path
and not from CPU delete path.
This causes migration to fail with the following error if migration is
attempted after a CPU unplug like this:
Unknown savevm section or instance 'spapr_cpu' 16
Additionally this leaves the source VM unresponsive after migration failure.
Fix this by ensuring the vmstate_unregister happens during CPU removal.
Fixing this becomes easier when vmstate (un)registration calls are moved to
vcpu (un)realize functions which is what this patch does.
Fixes: https://bugs.launchpad.net/qemu/+bug/1785972
Reported-by: Satheesh Rajendran <address@hidden>
Signed-off-by: Bharata B Rao <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 1368898d4b7e36f8a69e4dfd017853e15de6ef81
https://github.com/qemu/qemu/commit/1368898d4b7e36f8a69e4dfd017853e15de6ef81
Author: Alexey Kardashevskiy <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M pc-bios/README
M pc-bios/slof.bin
M roms/SLOF
Log Message:
-----------
pseries: Update SLOF firmware image
This includes gcc8.1 fixes and the image is compiled using gcc 8.1 as well.
The full list of changes is:
> Fix bad assembler statements for compiling with gcc 8.1 / as 2.30
> libelf: Add REL32 to the list of ignored relocations
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e82c42b7c5c1acbcfd5e5fe2b1b850c56e619c0d
https://github.com/qemu/qemu/commit/e82c42b7c5c1acbcfd5e5fe2b1b850c56e619c0d
Author: Richard Henderson <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/translate_init.inc.c
Log Message:
-----------
target/ppc: Enable fp exceptions for user-only
While just setting the MSR bits is sufficient, we can tidy
the helper code by extracting the MSR test to a helper and
then forcing it true for user-only.
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ae13018d79fb4db7c6a648617bfa0d5976f6e47d
https://github.com/qemu/qemu/commit/ae13018d79fb4db7c6a648617bfa0d5976f6e47d
Author: Richard Henderson <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
Log Message:
-----------
target/ppc: Honor fpscr_ze semantics and tidy fdiv
Divide by zero, exception taken, leaves the destination register
unmodified. Therefore we must raise the exception before returning
from helper_fdiv. Move the check from do_float_check_status into
helper_fdiv.
At the same time, tidy the invalid exception checking so that we
rely on softfloat for initial argument validation, and select the
kind of invalid operand exception only when we know we must.
At the same time, pass and return float64 values directly rather
than bounce through the CPU_DoubleU union.
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 79f916331da907b44e5da2c97f57823bcf8db3fb
https://github.com/qemu/qemu/commit/79f916331da907b44e5da2c97f57823bcf8db3fb
Author: Richard Henderson <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
Log Message:
-----------
target/ppc: Tidy helper_fmul
Tidy the invalid exception checking so that we rely on softfloat for
initial argument validation, and select the kind of invalid operand
exception only when we know we must. Pass and return float64 values
directly rather than bounce through the CPU_DoubleU union.
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ac43cec37e9b1661935e946774ec34f0d50c641e
https://github.com/qemu/qemu/commit/ac43cec37e9b1661935e946774ec34f0d50c641e
Author: Richard Henderson <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
Log Message:
-----------
target/ppc: Tidy helper_fadd, helper_fsub
Tidy the invalid exception checking so that we rely on softfloat for
initial argument validation, and select the kind of invalid operand
exception only when we know we must. Pass and return float64 values
directly rather than bounce through the CPU_DoubleU union.
Note that because we know float_flag_invalid was set, we do not have
to re-check the signs of the infinities.
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 49ab52ef69c804264fd2c61a9a61678a23d4fb33
https://github.com/qemu/qemu/commit/49ab52ef69c804264fd2c61a9a61678a23d4fb33
Author: Richard Henderson <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
Log Message:
-----------
target/ppc: Tidy helper_fsqrt
Tidy the invalid exception checking so that we rely on softfloat for
initial argument validation, and select the kind of invalid operand
exception only when we know we must. Pass and return float64 values
directly rather than bounce through the CPU_DoubleU union.
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 384347175588912a75e3b9d14d868fd3d646c9db
https://github.com/qemu/qemu/commit/384347175588912a75e3b9d14d868fd3d646c9db
Author: Richard Henderson <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M target/ppc/fpu_helper.c
Log Message:
-----------
target/ppc: Honor fpscr_ze semantics and tidy fre, fresqrt
Divide by zero, exception taken, leaves the destination register
unmodified. Therefore we must raise the exception before returning
from the respective helpers.
>From helper_fre, divide by zero exception not taken, return the
documented +/- 0.5.
At the same time, tidy the invalid exception checking so that we
rely on softfloat for initial argument validation, and select the
kind of invalid operand exception only when we know we must.
At the same time, pass and return float64 values directly rather
than bounce through the CPU_DoubleU union.
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 86c0cab11aabb0c2a5cc76825bc05dfe2b367412
https://github.com/qemu/qemu/commit/86c0cab11aabb0c2a5cc76825bc05dfe2b367412
Author: Richard Henderson <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/translate/fp-impl.inc.c
Log Message:
-----------
target/ppc: Use non-arithmetic conversions for fp load/store
Memory operations have no side effects on fp state.
The use of a "real" conversions between float64 and float32
would raise exceptions for SNaN and out-of-range inputs.
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 56e0e961ec14f7f89f9d5f20e12b61b9510ed1ad
https://github.com/qemu/qemu/commit/56e0e961ec14f7f89f9d5f20e12b61b9510ed1ad
Author: Yasmin Beatriz <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M target/ppc/int_helper.c
Log Message:
-----------
target/ppc: bcdsub fix sign when result is zero
When the result of bcdsub is equal to zero, the result sign may be
set to negative in some cases, and this does not follow the Power ISA
specifications as to decimal integer arithmetic instructions.
Signed-off-by: Yasmin Beatriz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: c26bc185b76369aab1a86bd726d5ea9e94c297a0
https://github.com/qemu/qemu/commit/c26bc185b76369aab1a86bd726d5ea9e94c297a0
Author: Alexey Kardashevskiy <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M hw/vfio/common.c
M hw/vfio/spapr.c
M include/hw/vfio/vfio-common.h
Log Message:
-----------
vfio/spapr: Allow backing bigger guest IOMMU pages with smaller physical pages
At the moment the PPC64/pseries guest only supports 4K/64K/16M IOMMU
pages and POWER8 CPU supports the exact same set of page size so
so far things worked fine.
However POWER9 supports different set of sizes - 4K/64K/2M/1G and
the last two - 2M and 1G - are not even allowed in the paravirt interface
(RTAS DDW) so we always end up using 64K IOMMU pages, although we could
back guest's 16MB IOMMU pages with 2MB pages on the host.
This stores the supported host IOMMU page sizes in VFIOContainer and uses
this later when creating a new DMA window. This uses the system page size
(64k normally, 2M/16M/1G if hugepages used) as the upper limit of
the IOMMU pagesize.
This changes the type of @pagesize to uint64_t as this is what
memory_region_iommu_get_min_page_size() returns and clz64() takes.
There should be no behavioral changes on platforms other than pseries.
The guest will keep using the IOMMU page size selected by the PHB pagesize
property as this only changes the underlying hardware TCE table
granularity.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 71c55a1eefef66cfc8afd686184d6371e35352cb
https://github.com/qemu/qemu/commit/71c55a1eefef66cfc8afd686184d6371e35352cb
Author: Greg Kurz <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M include/hw/ppc/xics.h
Log Message:
-----------
xics: don't include "target/ppc/cpu-qom.h" in "hw/ppc/xics.h"
The last user of the PowerPCCPU typedef in "hw/ppc/xics.h" vanished with
commit b1fd36c363d73969841468146ebfb9fd84a5ee52. It isn't necessary to
include "target/ppc/cpu-qom.h" there anymore.
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d03b174a839d32f8beef8082753afdcf732be7b6
https://github.com/qemu/qemu/commit/d03b174a839d32f8beef8082753afdcf732be7b6
Author: Yasmin Beatriz <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M target/ppc/int_helper.c
Log Message:
-----------
target/ppc: simplify bcdadd/sub functions
After solving a corner case in bcdsub, this patch simplifies the logic
of both bcdadd/sub instructions by removing some unnecessary local flags.
This commit also rearranges some if-else conditions in bcdadd to make it
easier to read.
Signed-off-by: Yasmin Beatriz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d45360d93d71578919ae8065a142beb941a900fd
https://github.com/qemu/qemu/commit/d45360d93d71578919ae8065a142beb941a900fd
Author: Cédric Le Goater <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: Add a pseries-3.1 machine type
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 82cffa2eb255731b8402e206d0434cc884d99e54
https://github.com/qemu/qemu/commit/82cffa2eb255731b8402e206d0434cc884d99e54
Author: Cédric Le Goater <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M hw/ppc/Makefile.objs
M hw/ppc/spapr.c
M hw/ppc/spapr_events.c
A hw/ppc/spapr_irq.c
M hw/ppc/spapr_pci.c
M hw/ppc/spapr_vio.c
M include/hw/ppc/spapr.h
A include/hw/ppc/spapr_irq.h
Log Message:
-----------
spapr: introduce a fixed IRQ number space
This proposal introduces a new IRQ number space layout using static
numbers for all devices, depending on a device index, and a bitmap
allocator for the MSI IRQ numbers which are negotiated by the guest at
runtime.
As the VIO device model does not have a device index but a "reg"
property, we introduce a formula to compute an IRQ number from a "reg"
value. It should minimize most of the collisions.
The previous layout is kept in pre-3.1 machines raising the
'legacy_irq_allocation' machine class flag.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 7d622ed3ff540f0678a3cca681b8a4a2e72dbc44
https://github.com/qemu/qemu/commit/7d622ed3ff540f0678a3cca681b8a4a2e72dbc44
Author: Peter Maydell <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M hw/ppc/prep.c
Log Message:
-----------
hw/ppc/prep: Remove ifdeffed-out stub of XCSR code
The prep machine has some code which is stubs of accessors
for XCSR registers. This has been disabled via #if 0
since commit b6b8bd1819ff in 2004, and doesn't have any
actual interesting content. It also uses the deprecated
old_mmio accessor functions. Remove it entirely.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Hervé Poussineau <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 878a4607049b0c073e9509b228cba5d9b7e5fa4c
https://github.com/qemu/qemu/commit/878a4607049b0c073e9509b228cba5d9b7e5fa4c
Author: Peter Maydell <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M hw/ppc/ppc405_boards.c
Log Message:
-----------
hw/ppc/ppc_boards: Don't use old_mmio for ref405ep_fpga
Switch the ref405ep_fpga device away from using the old_mmio
MemoryRegion accessors.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 69bd18f84347b1b342443601f10a55da4c87bc9d
https://github.com/qemu/qemu/commit/69bd18f84347b1b342443601f10a55da4c87bc9d
Author: Peter Maydell <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M hw/ppc/ppc405_uc.c
Log Message:
-----------
hw/ppc/ppc405_uc: Convert away from old_mmio
Convert the devices in ppc405_uc away from using the old_mmio
MemoryRegion accessors:
* opba's 32-bit and 16-bit accessors were just calling the
8-bit accessors and assembling a big-endian order number,
which we can do by setting the .impl.max_access_size to 1
and the endianness to DEVICE_BIG_ENDIAN, and letting the
core memory code do the assembly
* ppc405_gpio's accessors were all just stubs
* ppc4xx_gpt's 8-bit and 16-bit accessors were treating the
access as invalid, which we can do by setting the
.valid.min_access_size and .valid.max_access_size fields
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ef01ed9d19ffffbb5d5517ecb424c543cde373a1
https://github.com/qemu/qemu/commit/ef01ed9d19ffffbb5d5517ecb424c543cde373a1
Author: Cédric Le Goater <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_irq.c
M include/hw/ppc/spapr.h
M include/hw/ppc/spapr_irq.h
Log Message:
-----------
spapr: introduce a IRQ controller backend to the machine
This proposal moves all the related IRQ routines of the sPAPR machine
behind a sPAPR IRQ backend interface 'spapr_irq' to prepare for future
changes. First of which will be to increase the size of the IRQ number
space, then, will follow a new backend for the POWER9 XIVE IRQ controller.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 54c86f5a4844d517d2dd09922dd33a70117d0c7d
https://github.com/qemu/qemu/commit/54c86f5a4844d517d2dd09922dd33a70117d0c7d
Author: Hervé Poussineau <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M hw/ppc/prep.c
M tests/boot-serial-test.c
Log Message:
-----------
hw/ppc: deprecate the machine type 'prep', replaced by '40p'
- prep machine is a fictional machine, so has no specifications. Which
devices can be changed/added/removed without impact? Are interrupts
correctly mapped?
- prep firmware (OHW) has support only for IDE drives (no SCSI).
Booting from IDE has been broken approximatively 3 years ago, and nobody
complained.
- OHW is limited on IDE boot to a specific set of OS loaders.
These operating systems are of the 2004 time frame.
- OHW can use -kernel. Linux kernel freezes a long time after PS/2 mouse
detection, and then screen becomes garbage. This was already broken in
QEMU v2.7, 2 years ago, and nobody complained.
On the other side:
- 40p is a real machine, so emulation can be checked against
hardware specifications
- OpenBIOS has support for SCSI block devices, including 40p LSI adapter
- OpenBIOS can start mostly all Linux kernels (including recent ones)
and recent operating system (like NetBSD 7.1.2)
Signed-off-by: Hervé Poussineau <address@hidden>
[dwg: Drop prep from boot-serial test to avoid deprecation warnings]
Signed-off-by: David Gibson <address@hidden>
Commit: 93323287bb5565a1be175e3d0263085eb0c20e67
https://github.com/qemu/qemu/commit/93323287bb5565a1be175e3d0263085eb0c20e67
Author: Hervé Poussineau <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M qemu-deprecated.texi
Log Message:
-----------
qemu-doc: mark ppc/prep machine as deprecated
40p machine type should be used instead.
Signed-off-by: Hervé Poussineau <address@hidden>
Acked-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 0f08085971c4da52c390aaded82911b365323afa
https://github.com/qemu/qemu/commit/0f08085971c4da52c390aaded82911b365323afa
Author: Mark Cave-Ayland <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M hw/ppc/prep.c
Log Message:
-----------
40p: don't use legacy fw_cfg_init_mem() function
Instead initialise the device via qdev to allow us to set device properties
directly as required.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Acked-by: Hervé Poussineau <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 81a0705032213dd48c3c549bf6c71d4919b79986
https://github.com/qemu/qemu/commit/81a0705032213dd48c3c549bf6c71d4919b79986
Author: Mark Cave-Ayland <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M hw/ppc/mac_oldworld.c
Log Message:
-----------
mac_oldworld: don't use legacy fw_cfg_init_mem() function
Instead initialise the device via qdev to allow us to set device properties
directly as required.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 74887ed918a666695d11e717e6f1721139cee1ea
https://github.com/qemu/qemu/commit/74887ed918a666695d11e717e6f1721139cee1ea
Author: Mark Cave-Ayland <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M hw/ppc/mac_newworld.c
Log Message:
-----------
mac_newworld: don't use legacy fw_cfg_init_mem() function
Instead initialise the device via qdev to allow us to set device properties
directly as required.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2c88b098e76fde0c7fcc0476dd3f80ce58409505
https://github.com/qemu/qemu/commit/2c88b098e76fde0c7fcc0476dd3f80ce58409505
Author: Cédric Le Goater <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M hw/ppc/spapr_pci.c
Log Message:
-----------
spapr_pci: factorize the use of SPAPR_MACHINE_GET_CLASS()
It should save us some CPU cycles as these routines perform a lot of
checks.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 0e3bf4890906fa7066a5deafd6ab033934b8d100
https://github.com/qemu/qemu/commit/0e3bf4890906fa7066a5deafd6ab033934b8d100
Author: Roman Kapl <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M target/ppc/cpu.h
M target/ppc/excp_helper.c
M target/ppc/translate.c
M target/ppc/translate_init.inc.c
Log Message:
-----------
ppc: add DBCR based debugging
Add support for DBCR (debug control register) based debugging as used on
BookE ppc. So far supports only branch and single-step events, but these are
the important ones. GDB in Linux guest can now do single-stepping.
Signed-off-by: Roman Kapl <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: ee135aa0428fe5af2af7be04ff16d2b596a9330a
https://github.com/qemu/qemu/commit/ee135aa0428fe5af2af7be04ff16d2b596a9330a
Author: Peter Maydell <address@hidden>
Date: 2018-08-21 (Tue, 21 Aug 2018)
Changed paths:
M hw/ppc/Makefile.objs
M hw/ppc/mac_newworld.c
M hw/ppc/mac_oldworld.c
M hw/ppc/ppc405_boards.c
M hw/ppc/ppc405_uc.c
M hw/ppc/prep.c
M hw/ppc/spapr.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_events.c
A hw/ppc/spapr_irq.c
M hw/ppc/spapr_pci.c
M hw/ppc/spapr_vio.c
M hw/vfio/common.c
M hw/vfio/spapr.c
M include/hw/ppc/spapr.h
A include/hw/ppc/spapr_irq.h
M include/hw/ppc/xics.h
M include/hw/vfio/vfio-common.h
M pc-bios/README
M pc-bios/slof.bin
M qemu-deprecated.texi
M roms/SLOF
M target/ppc/cpu.h
M target/ppc/excp_helper.c
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/int_helper.c
M target/ppc/translate.c
M target/ppc/translate/fp-impl.inc.c
M target/ppc/translate_init.inc.c
M tests/boot-serial-test.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.1-20180821' into
staging
ppc patch queue 2018-08-21
Here's my first ppc & spapr pull request for qemu-3.1. This contains
a bunch of things that have accumulated while 3.0 was in freeze.
Highlights are:
* SLOF firmware update
* A number of floating point cleanups from Richard Henderson and
Yasmin Beatriz
* A new model for assigning irq numbers on spapr, this is an
important preliminary step towards implementing the POWER9
"XIVE" interrupt controller
# gpg: Signature made Tue 21 Aug 2018 05:32:44 BST
# gpg: using RSA key 6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg: aka "David Gibson (Red Hat) <address@hidden>"
# gpg: aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg: aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-3.1-20180821: (26 commits)
ppc: add DBCR based debugging
spapr_pci: factorize the use of SPAPR_MACHINE_GET_CLASS()
mac_newworld: don't use legacy fw_cfg_init_mem() function
mac_oldworld: don't use legacy fw_cfg_init_mem() function
40p: don't use legacy fw_cfg_init_mem() function
qemu-doc: mark ppc/prep machine as deprecated
hw/ppc: deprecate the machine type 'prep', replaced by '40p'
spapr: introduce a IRQ controller backend to the machine
hw/ppc/ppc405_uc: Convert away from old_mmio
hw/ppc/ppc_boards: Don't use old_mmio for ref405ep_fpga
hw/ppc/prep: Remove ifdeffed-out stub of XCSR code
spapr: introduce a fixed IRQ number space
spapr: Add a pseries-3.1 machine type
target/ppc: simplify bcdadd/sub functions
xics: don't include "target/ppc/cpu-qom.h" in "hw/ppc/xics.h"
vfio/spapr: Allow backing bigger guest IOMMU pages with smaller physical pages
target/ppc: bcdsub fix sign when result is zero
target/ppc: Use non-arithmetic conversions for fp load/store
target/ppc: Honor fpscr_ze semantics and tidy fre, fresqrt
target/ppc: Tidy helper_fsqrt
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/659b11e7a723...ee135aa0428f
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