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[Qemu-commits] [qemu/qemu] 2544e9: docs: add guidance on configuring CPU

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 2544e9: docs: add guidance on configuring CPU models for x...
Date: Fri, 17 Aug 2018 04:49:10 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 2544e9e4aa2bcef8ac069057a681a5ff37a23e49
      
https://github.com/qemu/qemu/commit/2544e9e4aa2bcef8ac069057a681a5ff37a23e49
  Author: Daniel P. Berrangé <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M MAINTAINERS
    M Makefile
    A docs/qemu-cpu-models.texi
    M qemu-doc.texi

  Log Message:
  -----------
  docs: add guidance on configuring CPU models for x86

With the recent set of CPU hardware vulnerabilities on x86, it is
increasingly difficult to understand which CPU configurations are
good to use and what flaws they might be vulnerable to.

This doc attempts to help management applications and administrators in
picking sensible CPU configuration on x86 hosts. It outlines which of
the named CPU models are good choices, and describes which extra CPU
flags should be enabled to allow the guest to mitigate hardware flaws.

Signed-off-by: Daniel P. Berrangé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 8c80c99fcceabd0708a5a83f08577e778c9419f5
      
https://github.com/qemu/qemu/commit/8c80c99fcceabd0708a5a83f08577e778c9419f5
  Author: Robert Hoo <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M target/i386/cpu.h

  Log Message:
  -----------
  i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES

IA32_PRED_CMD MSR gives software a way to issue commands that affect the state
of indirect branch predictors. Enumerated by CPUID.(EAX=7H,ECX=0):EDX[26].
IA32_ARCH_CAPABILITIES MSR enumerates architectural features of RDCL_NO and
IBRS_ALL. Enumerated by CPUID.(EAX=07H, ECX=0):EDX[29].

https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf

Signed-off-by: Robert Hoo <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 3fc7c73139d2d38ae80c3b0bc963b1ac1555924c
      
https://github.com/qemu/qemu/commit/3fc7c73139d2d38ae80c3b0bc963b1ac1555924c
  Author: Robert Hoo <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M target/i386/cpu.c
    M target/i386/cpu.h

  Log Message:
  -----------
  i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR

Support of IA32_PRED_CMD MSR already be enumerated by same CPUID bit as
SPEC_CTRL.

At present, mark CPUID_7_0_EDX_ARCH_CAPABILITIES unmigratable, per Paolo's
comment.

Signed-off-by: Robert Hoo <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 5131dc433df54b37e8e918d8fba7fe10344e7a7b
      
https://github.com/qemu/qemu/commit/5131dc433df54b37e8e918d8fba7fe10344e7a7b
  Author: Robert Hoo <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M target/i386/cpu.c
    M target/i386/cpu.h

  Log Message:
  -----------
  i386: Add CPUID bit for PCONFIG

PCONFIG: Platform configuration, enumerated by CPUID.(EAX=07H, ECX=0):
EDX[bit18].

Signed-off-by: Robert Hoo <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 59a80a19ca31a6fff9fdbb6b4cf55a5a0767c3bc
      
https://github.com/qemu/qemu/commit/59a80a19ca31a6fff9fdbb6b4cf55a5a0767c3bc
  Author: Robert Hoo <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M target/i386/cpu.c
    M target/i386/cpu.h

  Log Message:
  -----------
  i386: Add CPUID bit for WBNOINVD

WBNOINVD: Write back and do not invalidate cache, enumerated by
CPUID.(EAX=80000008H, ECX=0):EBX[bit 9].

Signed-off-by: Robert Hoo <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 8a11c62da9146dd89aee98947e6bd831e65a970d
      
https://github.com/qemu/qemu/commit/8a11c62da9146dd89aee98947e6bd831e65a970d
  Author: Robert Hoo <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: Add new CPU model Icelake-{Server,Client}

New CPU models mostly inherit features from ancestor Skylake, while addin new
features: UMIP, New Instructions ( PCONIFIG (server only), WBNOINVD,
AVX512_VBMI2, GFNI, AVX512_VNNI, VPCLMULQDQ, VAES, AVX512_BITALG),
Intel PT and 5-level paging (Server only). As well as
IA32_PRED_CMD, SSBD support for speculative execution
side channel mitigations.

Note:
For 5-level paging, Guest physical address width can be configured, with
parameter "phys-bits". Unless explicitly specified, we still use its default
value, even for Icelake-Server cpu model.
At present, hold on expose IA32_ARCH_CAPABILITIES to guest, as 1) This MSR
actually presents more than 1 'feature', maintainers are considering expanding 
current
features presentation of only CPUIDs to MSR bits; 2) a reasonable default value
for MSR_IA32_ARCH_CAPABILITIES needs to settled first. These 2 are actully
beyond Icelake CPU model itself but fundamental. So split these work apart
and do it later.
https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00774.html
https://lists.gnu.org/archive/html/qemu-devel/2018-07/msg00796.html

Signed-off-by: Robert Hoo <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 7f710c32bb893c68b931c68265f0427c032eb7f4
      
https://github.com/qemu/qemu/commit/7f710c32bb893c68b931c68265f0427c032eb7f4
  Author: Wanpeng Li <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  target-i386: adds PV_SEND_IPI CPUID feature bit

Adds PV_SEND_IPI CPUID feature bit.

Cc: Paolo Bonzini <address@hidden>
Cc: Eduardo Habkost <address@hidden>
Cc: Radim Krčmář <address@hidden>
Cc: Vitaly Kuznetsov <address@hidden>
Signed-off-by: Wanpeng Li <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 7210a02c58572b2686a3a8d610c6628f87864aed
      
https://github.com/qemu/qemu/commit/7210a02c58572b2686a3a8d610c6628f87864aed
  Author: Eduardo Habkost <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: Disable TOPOEXT by default on "-cpu host"

Enabling TOPOEXT is always allowed, but it can't be enabled
blindly by "-cpu host" because it may make guests crash if the
rest of the cache topology information isn't provided or isn't
consistent.

This addresses the bug reported at:
https://bugzilla.redhat.com/show_bug.cgi?id=1613277

Signed-off-by: Eduardo Habkost <address@hidden>
Message-Id: <address@hidden>
Tested-by: Richard W.M. Jones <address@hidden>
Reviewed-by: Babu Moger <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 0abaa41d936becd914a16ee1fe2a981d96d19428
      
https://github.com/qemu/qemu/commit/0abaa41d936becd914a16ee1fe2a981d96d19428
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-17 (Fri, 17 Aug 2018)

  Changed paths:
    M MAINTAINERS
    M Makefile
    A docs/qemu-cpu-models.texi
    M qemu-doc.texi
    M target/i386/cpu.c
    M target/i386/cpu.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' 
into staging

x86 queue, 2018-08-16

Bug fix:
* Some guests may crash when using "-cpu host" due to TOPOEXT,
  disable it by default

Features:
* PV_SEND_IPI feature bit
* Icelake-{Server,Client} CPU models
* New CPUID feature bits: PV_SEND_IPI, WBNOINVD, PCONFIG, ARCH_CAPABILITIES

Documentation:
* docs/qemu-cpu-models.texi

# gpg: Signature made Fri 17 Aug 2018 02:33:09 BST
# gpg:                using RSA key 2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <address@hidden>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-next-pull-request:
  i386: Disable TOPOEXT by default on "-cpu host"
  target-i386: adds PV_SEND_IPI CPUID feature bit
  i386: Add new CPU model Icelake-{Server,Client}
  i386: Add CPUID bit for WBNOINVD
  i386: Add CPUID bit for PCONFIG
  i386: Add CPUID bit and feature words for IA32_ARCH_CAPABILITIES MSR
  i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES
  docs: add guidance on configuring CPU models for x86

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/b8f7ff1e10b4...0abaa41d936b
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