[Qemu-commits] [qemu/qemu] 573ec0: target/arm: Fix typo in helper_sve

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[Qemu-commits] [qemu/qemu] 573ec0: target/arm: Fix typo in helper_sve_ld

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 573ec0: target/arm: Fix typo in helper_sve_ld1hss_r
Date:	Thu, 16 Aug 2018 09:18:00 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 573ec0fe40b9a412085ac7dfb41975a0fc2b28dd
      
https://github.com/qemu/qemu/commit/573ec0fe40b9a412085ac7dfb41975a0fc2b28dd
  Author: Richard Henderson <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M target/arm/sve_helper.c

  Log Message:
  -----------
  target/arm: Fix typo in helper_sve_ld1hss_r

Cc: address@hidden (3.0.1)
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 19f2acc915a0f8f443a959844540a6f09133cc96
      
https://github.com/qemu/qemu/commit/19f2acc915a0f8f443a959844540a6f09133cc96
  Author: Richard Henderson <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Fix sign-extension in sve do_ldr/do_str

The expression (int) imm + (uint32_t) len_align turns into uint32_t
and thus with negative imm produces a memory operation at the wrong
offset.  None of the numbers involved are particularly large, so
change everything to use int.

Cc: address@hidden (3.0.1)
Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d0e372b0298f897993f831dbff7ad4f1c70f138e
      
https://github.com/qemu/qemu/commit/d0e372b0298f897993f831dbff7ad4f1c70f138e
  Author: Richard Henderson <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Fix offset for LD1R instructions

The immediate should be scaled by the size of the memory reference,
not the size of the elements into which it is loaded.

Cc: address@hidden (3.0.1)
Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 50ef1cbf31caad21019ae6fa8036ed6f29244ba5
      
https://github.com/qemu/qemu/commit/50ef1cbf31caad21019ae6fa8036ed6f29244ba5
  Author: Richard Henderson <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Fix offset scaling for LD_zprr and ST_zprr

The scaling should be solely on the memory operation size; the number
of registers being loaded does not come in to the initial computation.

Cc: address@hidden (3.0.1)
Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3cb506a399854c481c2fd2efabecda0654700c47
      
https://github.com/qemu/qemu/commit/3cb506a399854c481c2fd2efabecda0654700c47
  Author: Richard Henderson <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Reformat integer register dump

With PC, there are 33 registers.  Three per line lines up nicely
without overflowing 80 columns.

Cc: address@hidden (3.0.1)
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2bf5f3f91bb4e3faa2a19aec042138a938afbf6a
      
https://github.com/qemu/qemu/commit/2bf5f3f91bb4e3faa2a19aec042138a938afbf6a
  Author: Richard Henderson <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Dump SVE state if enabled

Also fold the FPCR/FPSR state onto the same line as PSTATE,
and mention but do not dump disabled FPU state.

Cc: address@hidden (3.0.1)
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: adf92eab90e3f5f34c285da6d14d48952b7a8e72
      
https://github.com/qemu/qemu/commit/adf92eab90e3f5f34c285da6d14d48952b7a8e72
  Author: Richard Henderson <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M linux-user/syscall.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add sve-max-vq cpu property to -cpu max

This allows the default (and maximum) vector length to be set
from the command-line.  Which is extraordinarily helpful in
debugging problems depending on vector length without having to
bake knowledge of PR_SET_SVE_VL into every guest binary.

Cc: address@hidden (3.0.1)
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 781182e10fa13c8cb7e39e3d4e97fb7e3b210664
      
https://github.com/qemu/qemu/commit/781182e10fa13c8cb7e39e3d4e97fb7e3b210664
  Author: Jean-Christophe Dubois <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M hw/misc/Makefile.objs
    A hw/misc/imx6ul_ccm.c
    M hw/misc/trace-events
    A include/hw/misc/imx6ul_ccm.h

  Log Message:
  -----------
  i.MX6UL: Add i.MX6UL specific CCM device

Signed-off-by: Jean-Christophe Dubois <address@hidden>
Message-id: address@hidden
[PMM: fixed some comment typos etc]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 31cbf933f0ed02e5cb9f015bcfde23b35e87d3e0
      
https://github.com/qemu/qemu/commit/31cbf933f0ed02e5cb9f015bcfde23b35e87d3e0
  Author: Jean-Christophe Dubois <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/arm/Makefile.objs
    A hw/arm/fsl-imx6ul.c
    A include/hw/arm/fsl-imx6ul.h

  Log Message:
  -----------
  i.MX6UL: Add i.MX6UL SOC

Signed-off-by: Jean-Christophe Dubois <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0550e3bf7fd446bbce4768baa39bd64c3ab94636
      
https://github.com/qemu/qemu/commit/0550e3bf7fd446bbce4768baa39bd64c3ab94636
  Author: Jean-Christophe Dubois <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M hw/arm/Makefile.objs
    A hw/arm/mcimx6ul-evk.c

  Log Message:
  -----------
  i.MX6UL: Add Freescale i.MX6 UltraLite 14x14 EVK Board

Tested by booting linux 4.18 (built using imx_v6_v7_defconfig) on the
emulated board.

Signed-off-by: Jean-Christophe Dubois <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a1c5a06224173043eb4ac5b280f0b78718121fa2
      
https://github.com/qemu/qemu/commit/a1c5a06224173043eb4ac5b280f0b78718121fa2
  Author: Stefan Hajnoczi <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M hw/arm/armv7m.c
    M hw/arm/mps2.c
    M hw/arm/msf2-soc.c
    M hw/arm/stellaris.c
    M hw/arm/stm32f205_soc.c
    M include/hw/arm/armv7m.h

  Log Message:
  -----------
  hw/arm: make bitbanded IO optional on ARMv7-M

Some ARM CPUs have bitbanded IO, a memory region that allows convenient
bit access via 32-bit memory loads/stores.  This eliminates the need for
read-modify-update instruction sequences.

This patch makes this optional feature an ARMv7MState qdev property,
allowing boards to choose whether they want bitbanding or not.

Status of boards:
 * iotkit (Cortex M33), no bitband
 * mps2 (Cortex M3), bitband
 * msf2 (Cortex M3), bitband
 * stellaris (Cortex M3), bitband
 * stm32f205 (Cortex M3), bitband

As a side-effect of this patch, Peter Maydell noted that the Ethernet
controller on mps2 board is now accessible.  Previously they were hidden
by the bitband region (which does not exist on the real board).

Signed-off-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 191776b96a381b5d2b8d3f90c1c02b3e4779e5f7
      
https://github.com/qemu/qemu/commit/191776b96a381b5d2b8d3f90c1c02b3e4779e5f7
  Author: Stefan Hajnoczi <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: add "cortex-m0" CPU model

Define a "cortex-m0" ARMv6-M CPU model.

Most of the register reset values set by other CPU models are not
relevant for the cut-down ARMv6-M architecture.

Signed-off-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e7f59933548097dbb2272c49f2e0a4ece92697ff
      
https://github.com/qemu/qemu/commit/e7f59933548097dbb2272c49f2e0a4ece92697ff
  Author: Stefan Hajnoczi <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M hw/core/loader.c

  Log Message:
  -----------
  loader: extract rom_free() function

The next patch will need to free a rom.  There is already code to do
this in rom_add_file().

Note that rom_add_file() uses:

  rom = g_malloc0(sizeof(*rom));
  ...
  if (rom->fw_dir) {
      g_free(rom->fw_dir);
      g_free(rom->fw_file);
  }

The conditional is unnecessary since g_free(NULL) is a no-op.

Signed-off-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e2336043cc40eafc302c5ea8fa1d5c01438c06bb
      
https://github.com/qemu/qemu/commit/e2336043cc40eafc302c5ea8fa1d5c01438c06bb
  Author: Stefan Hajnoczi <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M hw/core/loader.c
    M include/hw/loader.h

  Log Message:
  -----------
  loader: add rom transaction API

Image file loaders may add a series of roms.  If an error occurs partway
through loading there is no easy way to drop previously added roms.

This patch adds a transaction mechanism that works like this:

  rom_transaction_begin();
  ...call rom_add_*()...
  rom_transaction_end(ok);

If ok is false then roms added in this transaction are dropped.

Signed-off-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e4a25ed91947af1ec87f23725de4ac86a3353b48
      
https://github.com/qemu/qemu/commit/e4a25ed91947af1ec87f23725de4ac86a3353b48
  Author: Su Hang <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M hw/core/generic-loader.c
    M hw/core/loader.c
    M include/hw/loader.h

  Log Message:
  -----------
  loader: Implement .hex file loader

This patch adds Intel Hexadecimal Object File format support to the
generic loader device.  The file format specification is available here:
http://www.piclist.com/techref/fileext/hex/intel.htm

This file format is often used with microcontrollers such as the
micro:bit, Arduino, STM32, etc.  Users expect to be able to run .hex
files directly with without first converting them to ELF.  Most
micro:bit code is developed in web-based IDEs without direct user access
to binutils so it is important for QEMU to handle this file format
natively.

Signed-off-by: Su Hang <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 645d3cbebb10b4ba3a3f25da7f3ad8a1f79fd1cc
      
https://github.com/qemu/qemu/commit/645d3cbebb10b4ba3a3f25da7f3ad8a1f79fd1cc
  Author: Su Hang <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M MAINTAINERS
    M configure
    M tests/Makefile.include
    A tests/hex-loader-check-data/test.hex
    A tests/hexloader-test.c

  Log Message:
  -----------
  Add QTest testcase for the Intel Hexadecimal

'test.hex' file is a memory test pattern stored in Hexadecimal Object
Format.  It loads at 0x10000 in RAM and contains values from 0 through
255.

The test case verifies that the expected memory test pattern was loaded.

Reviewed-by: Stefan Hajnoczi <address@hidden>
Suggested-by: Steffen Gortz <address@hidden>
Suggested-by: Stefan Hajnoczi <address@hidden>
Signed-off-by: Su Hang <address@hidden>
Signed-off-by: Stefan Hajnoczi <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
[PMM: changed qtest_startf() to qtest_initf() to work with
 current master after the refactoring in commit 88b988c895e3c2]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 016d4b0127bc8c76f1385c398ac7506e83b5ab39
      
https://github.com/qemu/qemu/commit/016d4b0127bc8c76f1385c398ac7506e83b5ab39
  Author: Trent Piepho <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M hw/ssi/imx_spi.c

  Log Message:
  -----------
  imx_spi: Unset XCH when TX FIFO becomes empty

The current emulation will clear the XCH bit when a burst finishes.
This is not quite correct.  According to the i.MX7d referemce manual,
Rev 0.1, §10.1.7.3:

    This bit [XCH] is cleared automatically when all data in the TXFIFO
    and the shift register has been shifted out.

So XCH should be cleared when the FIFO empties, not on completion of a
burst.  The FIFO is 64 x 32 bits = 2048 bits, while the max burst size
is larger at 4096 bits.  So it's possible that the burst is not finished
after the TXFIFO empties.

Sending a large block (> 2048 bits) with the Linux driver will use a
burst that is larger than the TXFIFO.  After the TXFIFO has emptied XCH
does not become unset, as the burst is not yet finished.

What should happen after the TXFIFO empties is the driver will refill it
and set XCH.  The rising edge of XCH will trigger another transfer to
begin.  However, since the emulation does not set XCH to 0, there is no
rising edge and the next trasfer never begins.

Signed-off-by: Trent Piepho <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a40085d2ee5fc4482d95e91c22212a228175a73d
      
https://github.com/qemu/qemu/commit/a40085d2ee5fc4482d95e91c22212a228175a73d
  Author: Joel Stanley <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M include/hw/misc/aspeed_sdmc.h

  Log Message:
  -----------
  aspeed_sdmc: Extend number of valid registers

The SDMC on the ast2500 has 170 registers.

Signed-off-by: Joel Stanley <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d131bc28a6094191471fb935a0535ae5a4df4ab3
      
https://github.com/qemu/qemu/commit/d131bc28a6094191471fb935a0535ae5a4df4ab3
  Author: Joel Stanley <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M hw/misc/aspeed_sdmc.c
    M include/hw/misc/aspeed_sdmc.h

  Log Message:
  -----------
  aspeed_sdmc: Fix saved values

This fixes the intended protection of read-only values in the
configuration register. They were being always set to zero by mistake.

The read-only fields depend on the configured memory size of the system,
so they cannot be fixed at compile time. The most straight forward
option was to store them in the state structure.

Signed-off-by: Joel Stanley <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b33f1e0b8921c95d744880e9f963b16a00653cad
      
https://github.com/qemu/qemu/commit/b33f1e0b8921c95d744880e9f963b16a00653cad
  Author: Joel Stanley <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M hw/misc/aspeed_sdmc.c

  Log Message:
  -----------
  aspeed_sdmc: Set 'cache initial sequence' always true

The SDRAM training routine sets the 'Enable cache initial' bit, and then
waits for the 'cache initial sequence' to be done.

Have it always return done, as there is no other side effects that the
model needs to implement. This allows the upstream u-boot training to
proceed on the ast2500-evb board.

Signed-off-by: Joel Stanley <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 33883ce840b291f4f5767aea911b56acae8dfb66
      
https://github.com/qemu/qemu/commit/33883ce840b291f4f5767aea911b56acae8dfb66
  Author: Joel Stanley <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M hw/misc/aspeed_sdmc.c

  Log Message:
  -----------
  aspeed_sdmc: Init status always idle

The ast2500 SDRAM training routine busy waits on the 'init cycle busy
state' bit in DDR PHY Control/Status register #1 (MCR60).

This ensures the bit always reads zero, and allows training to
complete with upstream u-boot on the ast2500-evb.

Signed-off-by: Joel Stanley <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a7b4569a4dddf0255d29ec56045c65f9bcb60919
      
https://github.com/qemu/qemu/commit/a7b4569a4dddf0255d29ec56045c65f9bcb60919
  Author: Joel Stanley <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M hw/misc/aspeed_sdmc.c

  Log Message:
  -----------
  aspeed_sdmc: Handle ECC training

This is required to ensure u-boot SDRAM training completes.

Signed-off-by: Joel Stanley <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ebe31c0a8ef7b59fd96171fe694339ce69ee24a6
      
https://github.com/qemu/qemu/commit/ebe31c0a8ef7b59fd96171fe694339ce69ee24a6
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M hw/arm/aspeed.c
    M hw/arm/aspeed_soc.c
    M hw/misc/aspeed_sdmc.c
    M include/hw/misc/aspeed_sdmc.h

  Log Message:
  -----------
  aspeed: add a max_ram_size property to the memory controller

This will be used to construct a memory region beyond the RAM region
to let firmwares scan the address space with load/store to guess how
much RAM the SoC has.

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: Joel Stanley <address@hidden>
Tested-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0b62159be33d45d00dfa34a317c6d3da30ffb480
      
https://github.com/qemu/qemu/commit/0b62159be33d45d00dfa34a317c6d3da30ffb480
  Author: Richard Henderson <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Adjust FPCR_MASK for FZ16

When support for FZ16 was added, we failed to include the bit
within FPCR_MASK, which means that it could never be set.
Continue to zero FZ16 when ARMv8.2-FP16 is not enabled.

Fixes: d81ce0ef2c4
Cc: address@hidden (3.0.1)
Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 19062c169e5bcdda3d60df9161228e107bf0f96e
      
https://github.com/qemu/qemu/commit/19062c169e5bcdda3d60df9161228e107bf0f96e
  Author: Richard Henderson <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Ignore float_flag_input_denormal from fp_status_f16

When FZ is set, input_denormal exceptions are recognized, but this does
not happen with FZ16.  The softfloat code has no way to distinguish
these bits and will raise such exceptions into fp_status_f16.flags,
so ignore them when computing the accumulated flags.

Cc: address@hidden (3.0.1)
Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 52a339b11d1719a6589de40606859939875fda9a
      
https://github.com/qemu/qemu/commit/52a339b11d1719a6589de40606859939875fda9a
  Author: Richard Henderson <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M target/arm/sve_helper.c

  Log Message:
  -----------
  target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h

This makes float16_muladd correctly use FZ16 not FZ.

Fixes: 6ceabaad110
Cc: address@hidden (3.0.1)
Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e4ab5124a5c2e2291006b24bdc21c3dd8d087ff4
      
https://github.com/qemu/qemu/commit/e4ab5124a5c2e2291006b24bdc21c3dd8d087ff4
  Author: Richard Henderson <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half

We were using the wrong flush-to-zero bit for the non-half input.

Fixes: 46d33d1e3c9
Cc: address@hidden (3.0.1)
Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b8a4a96db3639e17ab5e5cdc14fca4b19fbf5b3b
      
https://github.com/qemu/qemu/commit/b8a4a96db3639e17ab5e5cdc14fca4b19fbf5b3b
  Author: Richard Henderson <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Fix aa64 FCADD and FCMLA decode

These insns require u=1; failed to include that in the switch
cases.  This probably happened during one of the rebases just
before final commit.

Fixes: d17b7cdcf4e
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 64d450a0eaad5f02f9d6bba1dd451446297bb4dc
      
https://github.com/qemu/qemu/commit/64d450a0eaad5f02f9d6bba1dd451446297bb4dc
  Author: Richard Henderson <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M fpu/softfloat.c

  Log Message:
  -----------
  softfloat: Fix missing inexact for floating-point add

For 0x1.0000000000003p+0 + 0x1.ffffffep+14 = 0x1.0001fffp+15
we dropped the sticky bit and so failed to raise inexact.

Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Tested-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fcf13ca556f462b52956059bf8fa622bc8575edb
      
https://github.com/qemu/qemu/commit/fcf13ca556f462b52956059bf8fa622bc8575edb
  Author: Thomas Huth <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj()

Now that we've got the common sysbus_init_child_obj() function, we do
not need the local init_sysbus_child() anymore.

Signed-off-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bb16c0412a572c2c9cd44496deb3ad430bc49c1a
      
https://github.com/qemu/qemu/commit/bb16c0412a572c2c9cd44496deb3ad430bc49c1a
  Author: Peter Maydell <address@hidden>
  Date:   2018-08-16 (Thu, 16 Aug 2018)

  Changed paths:
    M MAINTAINERS
    M configure
    M default-configs/arm-softmmu.mak
    M fpu/softfloat.c
    M hw/arm/Makefile.objs
    M hw/arm/armv7m.c
    M hw/arm/aspeed.c
    M hw/arm/aspeed_soc.c
    A hw/arm/fsl-imx6ul.c
    A hw/arm/mcimx6ul-evk.c
    M hw/arm/mps2-tz.c
    M hw/arm/mps2.c
    M hw/arm/msf2-soc.c
    M hw/arm/stellaris.c
    M hw/arm/stm32f205_soc.c
    M hw/core/generic-loader.c
    M hw/core/loader.c
    M hw/misc/Makefile.objs
    M hw/misc/aspeed_sdmc.c
    A hw/misc/imx6ul_ccm.c
    M hw/misc/trace-events
    M hw/ssi/imx_spi.c
    M include/hw/arm/armv7m.h
    A include/hw/arm/fsl-imx6ul.h
    M include/hw/loader.h
    M include/hw/misc/aspeed_sdmc.h
    A include/hw/misc/imx6ul_ccm.h
    M linux-user/syscall.c
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/cpu64.c
    M target/arm/helper.c
    M target/arm/sve_helper.c
    M target/arm/translate-a64.c
    M target/arm/translate-sve.c
    M tests/Makefile.include
    A tests/hex-loader-check-data/test.hex
    A tests/hexloader-test.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180816' 
into staging

target-arm queue:
 * Fixes for various bugs in SVE instructions
 * Add model of Freescale i.MX6 UltraLite 14x14 EVK Board
 * hw/arm: make bitbanded IO optional on ARMv7-M
 * Add model of Cortex-M0 CPU
 * Add support for loading Intel HEX files to the generic loader
 * imx_spi: Unset XCH when TX FIFO becomes empty
 * aspeed_sdmc: fix various bugs
 * Fix bugs in Arm FP16 instruction support
 * Fix aa64 FCADD and FCMLA decode
 * softfloat: Fix missing inexact for floating-point add
 * hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj()

# gpg: Signature made Thu 16 Aug 2018 14:33:41 BST
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180816: (30 commits)
  hw/arm/mps2-tz: Replace init_sysbus_child() with sysbus_init_child_obj()
  softfloat: Fix missing inexact for floating-point add
  target/arm: Fix aa64 FCADD and FCMLA decode
  target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half
  target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h
  target/arm: Ignore float_flag_input_denormal from fp_status_f16
  target/arm: Adjust FPCR_MASK for FZ16
  aspeed: add a max_ram_size property to the memory controller
  aspeed_sdmc: Handle ECC training
  aspeed_sdmc: Init status always idle
  aspeed_sdmc: Set 'cache initial sequence' always true
  aspeed_sdmc: Fix saved values
  aspeed_sdmc: Extend number of valid registers
  imx_spi: Unset XCH when TX FIFO becomes empty
  Add QTest testcase for the Intel Hexadecimal
  loader: Implement .hex file loader
  loader: add rom transaction API
  loader: extract rom_free() function
  target/arm: add "cortex-m0" CPU model
  hw/arm: make bitbanded IO optional on ARMv7-M
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/c542a9f9794e...bb16c0412a57
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