[Qemu-commits] [qemu/qemu] 230809: hw/riscv/sifive_u: Create a SiFive U SoC object

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 2308092b2b78e6e083092bd3599cec6a0769319e
      
https://github.com/qemu/qemu/commit/2308092b2b78e6e083092bd3599cec6a0769319e
  Author: Alistair Francis <address@hidden>
  Date:   2018-07-05 (Thu, 05 Jul 2018)

  Changed paths:
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  hw/riscv/sifive_u: Create a SiFive U SoC object

Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine.

We leave the SoC, RAM, device tree and reset/fdt loading as part of the
machine. All the other device creation has been moved to the SoC.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Michael Clark <address@hidden>


  Commit: 651cd8b7e18eda46a36cf073428452d04bb354f2
      
https://github.com/qemu/qemu/commit/651cd8b7e18eda46a36cf073428452d04bb354f2
  Author: Alistair Francis <address@hidden>
  Date:   2018-07-05 (Thu, 05 Jul 2018)

  Changed paths:
    M hw/riscv/sifive_e.c
    M include/hw/riscv/sifive_e.h

  Log Message:
  -----------
  hw/riscv/sifive_e: Create a SiFive E SoC object

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Michael Clark <address@hidden>


  Commit: 647a70a10f257bdeba33ff5f1bcb2b26518a9f4c
      
https://github.com/qemu/qemu/commit/647a70a10f257bdeba33ff5f1bcb2b26518a9f4c
  Author: Alistair Francis <address@hidden>
  Date:   2018-07-05 (Thu, 05 Jul 2018)

  Changed paths:
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_plic.c
    M hw/riscv/sifive_u.c
    M hw/riscv/virt.c
    M include/hw/riscv/sifive_plic.h

  Log Message:
  -----------
  hw/riscv/sifive_plic: Use gpios instead of irqs

Instead of creating the interrupt in lines with qemu_allocate_irq() use
qdev_init_gpio_in() as this gives us the ability to use the qdev*gpio*()
helpers later on.

Signed-off-by: Alistair Francis <address@hidden>
Suggested-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Michael Clark <address@hidden>


  Commit: 2a1a6f6d47f192a12a3765a3558a11d619d25237
      
https://github.com/qemu/qemu/commit/2a1a6f6d47f192a12a3765a3558a11d619d25237
  Author: Alistair Francis <address@hidden>
  Date:   2018-07-05 (Thu, 05 Jul 2018)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv/sifive_u: Set the soc device tree node as a simple-bus

To allow Linux to ennumerate devices on the /soc/ node set it as a
"simple-bus".

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Michael Clark <address@hidden>


  Commit: 98ceee7fdc04526b7c264823a14ef5977b90040a
      
https://github.com/qemu/qemu/commit/98ceee7fdc04526b7c264823a14ef5977b90040a
  Author: Alistair Francis <address@hidden>
  Date:   2018-07-05 (Thu, 05 Jul 2018)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv/sifive_u: Set the interrupt controller number of interrupts

Set the interrupt-controller ndev to the correct number taken from the
HiFive Unleashed board.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Michael Clark <address@hidden>


  Commit: bde3ab9a9f2c2d08c7dabe77f19528b3f094b620
      
https://github.com/qemu/qemu/commit/bde3ab9a9f2c2d08c7dabe77f19528b3f094b620
  Author: Alistair Francis <address@hidden>
  Date:   2018-07-05 (Thu, 05 Jul 2018)

  Changed paths:
    M hw/riscv/sifive_u.c

  Log Message:
  -----------
  hw/riscv/sifive_u: Move the uart device tree node under /soc/

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Michael Clark <address@hidden>


  Commit: 5a7f76a3d47a75290868968682c0585d380764a4
      
https://github.com/qemu/qemu/commit/5a7f76a3d47a75290868968682c0585d380764a4
  Author: Alistair Francis <address@hidden>
  Date:   2018-07-05 (Thu, 05 Jul 2018)

  Changed paths:
    M default-configs/riscv32-softmmu.mak
    M default-configs/riscv64-softmmu.mak
    M hw/riscv/sifive_u.c
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device

Connect the Cadence GEM ethernet device. This also requires us to
expose the plic interrupt lines.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Michael Clark <address@hidden>


  Commit: a428594042bad540479733548b748b78a1a234b8
      
https://github.com/qemu/qemu/commit/a428594042bad540479733548b748b78a1a234b8
  Author: Peter Maydell <address@hidden>
  Date:   2018-07-06 (Fri, 06 Jul 2018)

  Changed paths:
    M default-configs/riscv32-softmmu.mak
    M default-configs/riscv64-softmmu.mak
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_plic.c
    M hw/riscv/sifive_u.c
    M hw/riscv/virt.c
    M include/hw/riscv/sifive_e.h
    M include/hw/riscv/sifive_plic.h
    M include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-pull-20180705' 
into staging

RISC-V: SoCify SiFive boards and connect GEM

This series has three tasks:
 1. To convert the SiFive U and E machines into SoCs and boards
 2. To connect the Cadence GEM device to the SiFive U board
 3. Fix some device tree problems with the SiFive U board

After this series the SiFive E and U boards have their SoCs split into
seperate QEMU objects, which can be used on future boards if desired.

The RISC-V Virt and Spike boards have not been converted. They haven't
been converted as they aren't physical boards, so it doesn't make a
whole lot of sense to split them into an SoC and board. The only
disadvantage with this is that they now differ to the SiFive boards.

This series also connect the Cadence GEM device to the SiFive U board.
There are some interrupt line changes requried before this is possible.

# gpg: Signature made Fri 06 Jul 2018 02:17:21 BST
# gpg:                using RSA key 21E10D29DF977054
# gpg: Good signature from "Alistair Francis <address@hidden>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-pull-20180705:
  hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device
  hw/riscv/sifive_u: Move the uart device tree node under /soc/
  hw/riscv/sifive_u: Set the interrupt controller number of interrupts
  hw/riscv/sifive_u: Set the soc device tree node as a simple-bus
  hw/riscv/sifive_plic: Use gpios instead of irqs
  hw/riscv/sifive_e: Create a SiFive E SoC object
  hw/riscv/sifive_u: Create a SiFive U SoC object

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/cee35138b59c...a428594042ba
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