[Qemu-commits] [qemu/qemu] c3513c: target/openrisc: Fix mtspr shadow gprs

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: c3513c836e4c19cd7a2a7f691995fdef587cec72
      
https://github.com/qemu/qemu/commit/c3513c836e4c19cd7a2a7f691995fdef587cec72
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-02 (Mon, 02 Jul 2018)

  Changed paths:
    M target/openrisc/sys_helper.c

  Log Message:
  -----------
  target/openrisc: Fix mtspr shadow gprs

Missing break when this feature was added in 89e71e873d
("target/openrisc: implement shadow registers").  This was causing
strange issues as we get writes into the translation block jump cache
and other bits of state.

Fixes: 89e71e873d ("target/openrisc: implement shadow registers")
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: d5cabcce62aeef63afd2b45ec634334df53c70c9
      
https://github.com/qemu/qemu/commit/d5cabcce62aeef63afd2b45ec634334df53c70c9
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/Makefile.objs
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h
    A target/openrisc/disas.c
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Add print_insn_or1k

Rather than emit disassembly while translating, reuse the
generated decoder to build a separate disassembler.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: 378cd36f3cfbc601381439a852fc68126b60131e
      
https://github.com/qemu/qemu/commit/378cd36f3cfbc601381439a852fc68126b60131e
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/interrupt.c

  Log Message:
  -----------
  target/openrisc: Log interrupts

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: c86395c850d43047e65892ea41942c18eb29a39d
      
https://github.com/qemu/qemu/commit/c86395c850d43047e65892ea41942c18eb29a39d
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP

These values are unused.

Reviewed-by: Stafford Horne <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: 64e46c958162d986cc6e0cdfd6fb8f11b6f31748
      
https://github.com/qemu/qemu/commit/64e46c958162d986cc6e0cdfd6fb8f11b6f31748
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/interrupt_helper.c
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB

No need to use the interrupt mechanisms when we can
simply exit the tb directly.

Reviewed-by: Stafford Horne <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: e0a369cf88041a71cf5d902f1d78c9a645a6709e
      
https://github.com/qemu/qemu/commit/e0a369cf88041a71cf5d902f1d78c9a645a6709e
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Fix singlestep_enabled

We failed to store to cpu_pc before raising the exception,
which caused us to re-execute the same insn that we stepped.

Reviewed-by: Stafford Horne <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: 8000ba56cc534dd917ae54f6ef0e898813c12b24
      
https://github.com/qemu/qemu/commit/8000ba56cc534dd917ae54f6ef0e898813c12b24
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Link more translation blocks

Track direct jumps via dc->jmp_pc_imm.  Use that in
preference to jmp_pc when possible.  Emit goto_tb in
that case, and lookup_and_goto_tb otherwise.

Reviewed-by: Stafford Horne <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: 2ba6541792782fc0d20dab6678f5f90a3c8978c9
      
https://github.com/qemu/qemu/commit/2ba6541792782fc0d20dab6678f5f90a3c8978c9
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Split out is_user

This allows us to limit the amount of ifdefs and isolate
the test for usermode.

Reviewed-by: Stafford Horne <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: 01ec3ec930c90374a8870e99e0da63c17d708d47
      
https://github.com/qemu/qemu/commit/01ec3ec930c90374a8870e99e0da63c17d708d47
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Exit the TB after l.mtspr

A store to SR changes interrupt state, which should return
to the main loop to recognize that state.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: c28fa81f915b03834b00187e43604e42768f15fa
      
https://github.com/qemu/qemu/commit/c28fa81f915b03834b00187e43604e42768f15fa
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/helper.h
    M target/openrisc/sys_helper.c
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Form the spr index from tcg

Rather than pass base+offset to the helper, pass the full index.
In most cases the base is r0 and optimization yields a constant.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: 455d45d22cc3b2c29c7840f2478647a0a3d9d8b4
      
https://github.com/qemu/qemu/commit/455d45d22cc3b2c29c7840f2478647a0a3d9d8b4
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/cpu.h
    M target/openrisc/interrupt.c
    M target/openrisc/interrupt_helper.c
    M target/openrisc/machine.c
    M target/openrisc/mmu.c
    M target/openrisc/sys_helper.c

  Log Message:
  -----------
  target/openrisc: Merge tlb allocation into CPUOpenRISCState

There is no reason to allocate this separately.  This was probably
copied from target/mips which makes the same mistake.

While doing so, move tlb into the clear-on-reset range.  While not
all of the TLB bits are guaranteed zero on reset, all of the valid
bits are cleared, and the rest of the bits are unspecified.
Therefore clearing the whole of the TLB is correct.

Reviewed-by: Stafford Horne <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: 23d45ebdb198378ae580c98ac898aa4b615059fd
      
https://github.com/qemu/qemu/commit/23d45ebdb198378ae580c98ac898aa4b615059fd
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h
    M target/openrisc/interrupt.c
    M target/openrisc/interrupt_helper.c
    M target/openrisc/machine.c
    M target/openrisc/mmu.c
    M target/openrisc/sys_helper.c

  Log Message:
  -----------
  target/openrisc: Remove indirect function calls for mmu

There is no reason to use an indirect branch instead
of simply testing the SR bits that control mmu state.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: fd992ee7e3fb12aea888744313a2869c8848ef9d
      
https://github.com/qemu/qemu/commit/fd992ee7e3fb12aea888744313a2869c8848ef9d
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/Makefile.objs
    M target/openrisc/mmu.c
    R target/openrisc/mmu_helper.c

  Log Message:
  -----------
  target/openrisc: Merge mmu_helper.c into mmu.c

With tlb_fill in mmu.c, we can simplify things further.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: 2acaa2331b96ee92f0df213784f9b6454c3d5edc
      
https://github.com/qemu/qemu/commit/2acaa2331b96ee92f0df213784f9b6454c3d5edc
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/cpu.h
    M target/openrisc/machine.c
    M target/openrisc/mmu.c
    M target/openrisc/sys_helper.c

  Log Message:
  -----------
  target/openrisc: Reduce tlb to a single dimension

While we had defines for *_WAYS, we didn't define more than 1.
Reduce the complexity by eliminating this unused dimension.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: fffde6695f4be3cf484f068f24e894280d7360ea
      
https://github.com/qemu/qemu/commit/fffde6695f4be3cf484f068f24e894280d7360ea
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/sys_helper.c

  Log Message:
  -----------
  target/openrisc: Fix tlb flushing in mtspr

The previous code was confused, avoiding the flush of the old entry
if the new entry is invalid.  We need to flush the old page if the
old entry is valid and the new page if the new entry is valid.

This bug was masked by over-flushing elsewhere.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: b9bed1b9ab37a6ae62e88a52cbcbd2ad81aa1056
      
https://github.com/qemu/qemu/commit/b9bed1b9ab37a6ae62e88a52cbcbd2ad81aa1056
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/cpu.h
    M target/openrisc/interrupt.c
    M target/openrisc/interrupt_helper.c
    M target/openrisc/mmu.c
    M target/openrisc/sys_helper.c
    M target/openrisc/translate.c

  Log Message:
  -----------
  target/openrisc: Fix cpu_mmu_index

The code in cpu_mmu_index does not properly honor SR_DME.
This bug has workarounds elsewhere in that we flush the
tlb more often than necessary, on the state changes that
should be reflected in a change of mmu_index.

Fixing this means that we can respect the mmu_index that
is given to tlb_flush.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: 56c3a1415653bd485b06e718c6f14e32dcfe59b3
      
https://github.com/qemu/qemu/commit/56c3a1415653bd485b06e718c6f14e32dcfe59b3
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/cpu.h
    M target/openrisc/machine.c
    M target/openrisc/mmu.c
    M target/openrisc/sys_helper.c

  Log Message:
  -----------
  target/openrisc: Use identical sizes for ITLB and DTLB

The sizes are already the same, however, we can improve things
if they are identical by design.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: 5ce5dad3527e024c297f73f9eb79098235efba6b
      
https://github.com/qemu/qemu/commit/5ce5dad3527e024c297f73f9eb79098235efba6b
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/mmu.c

  Log Message:
  -----------
  target/openrisc: Stub out handle_mmu_fault for softmmu

This hook is only used by CONFIG_USER_ONLY.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: 1cc9e5d896695091eeb126f5c578b02ddd0fc0e4
      
https://github.com/qemu/qemu/commit/1cc9e5d896695091eeb126f5c578b02ddd0fc0e4
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h
    M target/openrisc/machine.c

  Log Message:
  -----------
  target/openrisc: Increase the TLB size

The architecture supports 128 TLB entries.  There is no reason
not to provide all of them.  In the process we need to fix a
bug that failed to parameterize the configuration register that
tells the operating system the number of entries.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>

---
v2:
  - Change VMState version.


  Commit: f0655423ca72797fc12763c6a46b69d3eae90a1c
      
https://github.com/qemu/qemu/commit/f0655423ca72797fc12763c6a46b69d3eae90a1c
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/cpu.h
    M target/openrisc/mmu.c

  Log Message:
  -----------
  target/openrisc: Reorg tlb lookup

While openrisc has a split i/d tlb, qemu does not.  Perform a
lookup on both i & d tlbs in parallel and put the composite
rights into qemu's tlb.  This avoids ping-ponging the qemu tlb
between EXEC and READ.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: ecbed7280c832220d9ac8ea7c0b6163393e3cb1a
      
https://github.com/qemu/qemu/commit/ecbed7280c832220d9ac8ea7c0b6163393e3cb1a
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M scripts/qemu-binfmt-conf.sh

  Log Message:
  -----------
  target/openrisc: Add support in scripts/qemu-binfmt-conf.sh

Reviewed-by: Laurent Vivier <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: e8f29049b1e904068ce874e6a40b6ad18b26e121
      
https://github.com/qemu/qemu/commit/e8f29049b1e904068ce874e6a40b6ad18b26e121
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M linux-user/openrisc/signal.c
    M linux-user/openrisc/target_syscall.h
    M linux-user/signal.c
    M target/openrisc/cpu.c

  Log Message:
  -----------
  linux-user: Implement signals for openrisc

All of the existing code was boilerplate from elsewhere,
and would crash the guest upon the first signal.

Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>

---
v2:
  Add a comment to the new definition of target_pt_regs.
  Install the signal mask into the ucontext.
v3:
  Incorporate feedback from Laurent.


  Commit: 4151e530192996d1f4db1f43e436a21a4c6f707d
      
https://github.com/qemu/qemu/commit/4151e530192996d1f4db1f43e436a21a4c6f707d
  Author: Richard Henderson <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M linux-user/openrisc/target_signal.h

  Log Message:
  -----------
  linux-user: Fix struct sigaltstack for openrisc

Reviewed-by: Laurent Vivier <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: 9f6e8afad7b7bd03de6474ea871fcb724630cc0b
      
https://github.com/qemu/qemu/commit/9f6e8afad7b7bd03de6474ea871fcb724630cc0b
  Author: Stafford Horne <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/interrupt.c

  Log Message:
  -----------
  target/openrisc: Fix delay slot exception flag to match spec

The delay slot exception flag is only set on the SR register during
exception.  Previously it was being set on both the ESR and SR this
caused QEMU to differ from the spec.  The was apparent as the linux
kernel had a bug where it could boot on QEMU but not on real hardware.

The fixed logic now matches hardware.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: dfc84745bbaa0fea2abc8575dd349f6e4bb7edc7
      
https://github.com/qemu/qemu/commit/dfc84745bbaa0fea2abc8575dd349f6e4bb7edc7
  Author: Stafford Horne <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M target/openrisc/sys_helper.c

  Log Message:
  -----------
  target/openrisc: Fix writes to interrupt mask register

The interrupt controller mask register (PICMR) allows writing any value
to any of the 32 interrupt mask bits.  Writing a 0 masks the interrupt
writing a 1 unmasks (enables) the the interrupt.

For some reason the old code was or'ing the write values to the PICMR
meaning it was not possible to ever mask a interrupt once it was
enabled.

I have tested this by running linux 4.18 and my regular checks, I don't
see any issues.

Reported-by: Davidson Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: f988c7e191141e92de2059d04a5f9a9bb01f399c
      
https://github.com/qemu/qemu/commit/f988c7e191141e92de2059d04a5f9a9bb01f399c
  Author: Peter Maydell <address@hidden>
  Date:   2018-07-03 (Tue, 03 Jul 2018)

  Changed paths:
    M linux-user/openrisc/signal.c
    M linux-user/openrisc/target_signal.h
    M linux-user/openrisc/target_syscall.h
    M linux-user/signal.c
    M scripts/qemu-binfmt-conf.sh
    M target/openrisc/Makefile.objs
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h
    A target/openrisc/disas.c
    M target/openrisc/helper.h
    M target/openrisc/interrupt.c
    M target/openrisc/interrupt_helper.c
    M target/openrisc/machine.c
    M target/openrisc/mmu.c
    R target/openrisc/mmu_helper.c
    M target/openrisc/sys_helper.c
    M target/openrisc/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/shorne/tags/pull-or-20180703' into 
staging

OpenRISC cleanups and Fixes for QEMU 3.0

Mostly patches from Richard Henderson fixing multiple things:
 * Fix singlestepping in GDB.
 * Use more TB linking.
 * Fixes to exit TB after updating SPRs to enable registering of state
   changes.
 * Significant optimizations and refactors to the TLB
 * Split out disassembly from translation.
 * Add qemu-or1k to qemu-binfmt-conf.sh.
 * Implement signal handling for linux-user.

Then there are a few fixups from me:
 * Fix delay slot detections to match hardware, this was masking a bug
   in the linus kernel.
 * Fix stores to the PIC mask register

# gpg: Signature made Tue 03 Jul 2018 14:44:10 BST
# gpg:                using RSA key C3B31C2D5E6627E4
# gpg: Good signature from "Stafford Horne <address@hidden>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25  EFF1 C3B3 1C2D 5E66 27E4

* remotes/shorne/tags/pull-or-20180703: (25 commits)
  target/openrisc: Fix writes to interrupt mask register
  target/openrisc: Fix delay slot exception flag to match spec
  linux-user: Fix struct sigaltstack for openrisc
  linux-user: Implement signals for openrisc
  target/openrisc: Add support in scripts/qemu-binfmt-conf.sh
  target/openrisc: Reorg tlb lookup
  target/openrisc: Increase the TLB size
  target/openrisc: Stub out handle_mmu_fault for softmmu
  target/openrisc: Use identical sizes for ITLB and DTLB
  target/openrisc: Fix cpu_mmu_index
  target/openrisc: Fix tlb flushing in mtspr
  target/openrisc: Reduce tlb to a single dimension
  target/openrisc: Merge mmu_helper.c into mmu.c
  target/openrisc: Remove indirect function calls for mmu
  target/openrisc: Merge tlb allocation into CPUOpenRISCState
  target/openrisc: Form the spr index from tcg
  target/openrisc: Exit the TB after l.mtspr
  target/openrisc: Split out is_user
  target/openrisc: Link more translation blocks
  target/openrisc: Fix singlestep_enabled
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/b07cd3e748b3...f988c7e19114
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