[Qemu-commits] [qemu/qemu] 072130: aspeed/smc: fix dummy cycles count when in dual IO...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 0721309ed77100e857a7149dd563a4d1a0d07d68
      
https://github.com/qemu/qemu/commit/0721309ed77100e857a7149dd563a4d1a0d07d68
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: fix dummy cycles count when in dual IO mode

When configured in dual I/O mode, address and data are sent in dual
mode, including the dummy byte cycles in between. Adapt the count to
the IO setting.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a57baeb45e1471f88db4a8da11a307603cfc8657
      
https://github.com/qemu/qemu/commit/a57baeb45e1471f88db4a8da11a307603cfc8657
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: fix HW strapping

Only the flash type is strapped by HW. The 4BYTE mode is set by
firmware when the flash device is detected.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 96c4be955b6ee37544d10bb8a123226bb0f014cd
      
https://github.com/qemu/qemu/commit/96c4be955b6ee37544d10bb8a123226bb0f014cd
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/ssi/aspeed_smc.c

  Log Message:
  -----------
  aspeed/smc: rename aspeed_smc_flash_send_addr() to aspeed_smc_flash_setup()

Also handle the fake transfers for dummy bytes in this setup
routine. It will be useful when we activate MMIO execution.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1f7161d2c83a4ebba296ffece26f992be5754471
      
https://github.com/qemu/qemu/commit/1f7161d2c83a4ebba296ffece26f992be5754471
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Adopt the Gumstix computers-on-module machines

These COMs are hard to find, and the companie dropped the support
few years ago.

Per the "Gumstix Product Changes, Known Issues, and EOL" pdf:

- Phasing out: PXA270-based Verdex product line
  September 2012

- Phasing out: PXA255-based Basix & Connex
  September 2009

However there are still booting SD card image availables, very
convenient to stress test the QEMU SD card implementation.
Therefore I volunteer to keep an eye on this file, while it
is useful for testing.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 21d887cde954ca683f37d9c7d20371cdf26686be
      
https://github.com/qemu/qemu/commit/21d887cde954ca683f37d9c7d20371cdf26686be
  Author: Sai Pavan Boddu <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/ssi/xilinx_spips.c
    M include/hw/ssi/xilinx_spips.h

  Log Message:
  -----------
  xilinx_spips: Make dma transactions as per dma_burst_size

Qspi dma has a burst length of 64 bytes, So limit the transactions w.r.t
dma-burst-size property.

Signed-off-by: Sai Pavan Boddu <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f87db1babe9fc3853657c43309f06e08527ad66f
      
https://github.com/qemu/qemu/commit/f87db1babe9fc3853657c43309f06e08527ad66f
  Author: Joel Stanley <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add ASPEED BMCs

This adds Cedric as the maintainer, with Andrew and I as reviewers, for
the ASPEED boards and the peripherals we have developed.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Acked-by: Cédric Le Goater <address@hidden>
Signed-off-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c2e846bba52301b7410a527937987b63c67aad3c
      
https://github.com/qemu/qemu/commit/c2e846bba52301b7410a527937987b63c67aad3c
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/input/pckbd.c

  Log Message:
  -----------
  hw/input/pckbd: Use qemu_log_mask(GUEST_ERROR) instead of fprintf

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 56112168abcdaa145fe8463d38cab218c11891dc
      
https://github.com/qemu/qemu/commit/56112168abcdaa145fe8463d38cab218c11891dc
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/input/tsc2005.c

  Log Message:
  -----------
  hw/input/tsc2005: Use qemu_log_mask(GUEST_ERROR) instead of fprintf

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f3724bf5e635f9cecaa37668b7aa3ea010a1ffb6
      
https://github.com/qemu/qemu/commit/f3724bf5e635f9cecaa37668b7aa3ea010a1ffb6
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/dma/omap_dma.c

  Log Message:
  -----------
  hw/dma/omap_dma: Use qemu_log_mask(UNIMP) instead of printf

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e26745d5573461bb9e2e9ad70b1fc6acd8fe040a
      
https://github.com/qemu/qemu/commit/e26745d5573461bb9e2e9ad70b1fc6acd8fe040a
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/dma/omap_dma.c

  Log Message:
  -----------
  hw/dma/omap_dma: Use qemu_log_mask(GUEST_ERROR) instead of fprintf

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 31a1246df674c83b46445b93206898da65104524
      
https://github.com/qemu/qemu/commit/31a1246df674c83b46445b93206898da65104524
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/ssi/omap_spi.c

  Log Message:
  -----------
  hw/ssi/omap_spi: Use qemu_log_mask(GUEST_ERROR) instead of fprintf

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 25b98b96af0df0ca224d42e2b0dadaa06f5d49af
      
https://github.com/qemu/qemu/commit/25b98b96af0df0ca224d42e2b0dadaa06f5d49af
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/sd/omap_mmc.c

  Log Message:
  -----------
  hw/sd/omap_mmc: Use qemu_log_mask(UNIMP) instead of printf

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8d2774f0ff953f945167dcf7259e1f7a6091d19f
      
https://github.com/qemu/qemu/commit/8d2774f0ff953f945167dcf7259e1f7a6091d19f
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/i2c/omap_i2c.c

  Log Message:
  -----------
  hw/i2c/omap_i2c: Use qemu_log_mask(UNIMP) instead of fprintf

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 415202d4c98e660b333a6dfefe5d4b33b7e67595
      
https://github.com/qemu/qemu/commit/415202d4c98e660b333a6dfefe5d4b33b7e67595
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/arm/omap1.c
    M include/hw/arm/omap.h

  Log Message:
  -----------
  hw/arm/omap1: Use qemu_log_mask(GUEST_ERROR) instead of fprintf

TCMI_VERBOSE is no more used, drop the OMAP_8/16/32B_REG macros.

Suggested-by: Thomas Huth <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 84b335c6d00a89265cc7f1eaf2a381706c87ac9a
      
https://github.com/qemu/qemu/commit/84b335c6d00a89265cc7f1eaf2a381706c87ac9a
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M include/hw/arm/omap.h

  Log Message:
  -----------
  hw/arm/omap: Use qemu_log_mask(GUEST_ERROR) instead of fprintf

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9194524b0d555dbf0b1cefb303cc362a0458586f
      
https://github.com/qemu/qemu/commit/9194524b0d555dbf0b1cefb303cc362a0458586f
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/arm/stellaris.c

  Log Message:
  -----------
  hw/arm/stellaris: Use qemu_log_mask(UNIMP) instead of fprintf

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5786e35da7beb10e7267e9762b56dfff95a7f0c7
      
https://github.com/qemu/qemu/commit/5786e35da7beb10e7267e9762b56dfff95a7f0c7
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/net/stellaris_enet.c

  Log Message:
  -----------
  hw/net/stellaris_enet: Fix a typo

Suggested-by: Thomas Huth <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: f6de99571437fca0ead566a4a1f26a1bdaa2316a
      
https://github.com/qemu/qemu/commit/f6de99571437fca0ead566a4a1f26a1bdaa2316a
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/net/stellaris_enet.c

  Log Message:
  -----------
  hw/net/stellaris_enet: Use qemu_log_mask(GUEST_ERROR) instead of hw_error

hw_error() finally calls abort(), but there is no need to abort here.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b9992d122da35f433b0d825523e4b722509e824e
      
https://github.com/qemu/qemu/commit/b9992d122da35f433b0d825523e4b722509e824e
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/net/smc91c111.c

  Log Message:
  -----------
  hw/net/smc91c111: Use qemu_log_mask(GUEST_ERROR) instead of hw_error

hw_error() finally calls abort(), but there is no need to abort here.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 637e5d86fce4859c3b0bb7204bd06d803caf803c
      
https://github.com/qemu/qemu/commit/637e5d86fce4859c3b0bb7204bd06d803caf803c
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/net/smc91c111.c

  Log Message:
  -----------
  hw/net/smc91c111: Use qemu_log_mask(UNIMP) instead of fprintf

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bc281efff60f81fdde6014daa24ca81484b42814
      
https://github.com/qemu/qemu/commit/bc281efff60f81fdde6014daa24ca81484b42814
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/arm/stellaris.c

  Log Message:
  -----------
  hw/arm/stellaris: Fix gptm_write() error message

Missed in df3692e04b2.

Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d29183d3c0174e248b31bb2ee58b889f7baa3cfe
      
https://github.com/qemu/qemu/commit/d29183d3c0174e248b31bb2ee58b889f7baa3cfe
  Author: Philippe Mathieu-Daudé <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/arm/stellaris.c

  Log Message:
  -----------
  hw/arm/stellaris: Use HWADDR_PRIx to display register address

Suggested-by: Thomas Huth <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 55df6fcf5476b44bc1b95554e686ab3e91d725c5
      
https://github.com/qemu/qemu/commit/55df6fcf5476b44bc1b95554e686ab3e91d725c5
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M accel/tcg/cputlb.c
    M accel/tcg/softmmu_template.h
    M include/exec/cpu-all.h

  Log Message:
  -----------
  tcg: Support MMU protection regions smaller than TARGET_PAGE_SIZE

Add support for MMU protection regions that are smaller than
TARGET_PAGE_SIZE. We do this by marking the TLB entry for those
pages with a flag TLB_RECHECK. This flag causes us to always
take the slow-path for accesses. In the slow path we can then
special case them to always call tlb_fill() again, so we have
the correct information for the exact address being accessed.

This change allows us to handle reading and writing from small
regions; we cannot deal with execution from the small region.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: e5e40999b5e03567ef654546e3d448431643f8f3
      
https://github.com/qemu/qemu/commit/e5e40999b5e03567ef654546e3d448431643f8f3
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Set page (region) size in get_phys_addr_pmsav7()

We want to handle small MPU region sizes for ARMv7M. To do this,
make get_phys_addr_pmsav7() set the page size to the region
size if it is less that TARGET_PAGE_SIZE, rather than working
only in TARGET_PAGE_SIZE chunks.

Since the core TCG code con't handle execution from small
MPU regions, we strip the exec permission from them so that
any execution attempts will cause an MPU exception, rather
than allowing it to end up with a cpu_abort() in
get_page_addr_code().

(The previous code's intention was to make any small page be
treated as having no permissions, but unfortunately errors
in the implementation meant that it didn't behave that way.
It's possible that some binaries using small regions were
accidentally working with our old behaviour and won't now.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 720424359917887c926a33d248131fbff84c9c28
      
https://github.com/qemu/qemu/commit/720424359917887c926a33d248131fbff84c9c28
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Handle small regions in get_phys_addr_pmsav8()

Allow ARMv8M to handle small MPU and SAU region sizes, by making
get_phys_add_pmsav8() set the page size to the 1 if the MPU or
SAU region covers less than a TARGET_PAGE_SIZE.

We choose to use a size of 1 because it makes no difference to
the core code, and avoids having to track both the base and
limit for SAU and MPU and then convert into an artificially
restricted "page size" that the core code will then ignore.

Since the core TCG code can't handle execution from small
MPU regions, we strip the exec permission from them so that
any execution attempts will cause an MPU exception, rather
than allowing it to end up with a cpu_abort() in
get_page_addr_code().

(The previous code's intention was to make any small page be
treated as having no permissions, but unfortunately errors
in the implementation meant that it didn't behave that way.
It's possible that some binaries using small regions were
accidentally working with our old behaviour and won't now.)

We also retain an existing bug, where we ignored the possibility
that the SAU region might not cover the entire page, in the
case of executable regions. This is necessary because some
currently-working guest code images rely on being able to
execute from addresses which are covered by a page-sized
MPU region but a smaller SAU region. We can remove this
workaround if we ever support execution from small regions.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 9122bea9862edc0e665c796f79d99319b6638929
      
https://github.com/qemu/qemu/commit/9122bea9862edc0e665c796f79d99319b6638929
  Author: Jia He <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/arm/smmuv3-internal.h
    M hw/arm/smmuv3.c
    M hw/arm/trace-events

  Log Message:
  -----------
  hw/arm/smmuv3: Fix translate error handling

In case the STE's config is "Bypass" we currently don't set the
IOMMUTLBEntry perm flags and the access does not succeed. Also
if the config is 0b0xx (Aborted/Reserved), decode_ste and
smmuv3_decode_config currently returns -EINVAL and we don't enter
the expected code path: we record an event whereas we should not.

This patch fixes those bugs and simplifies the error handling.
decode_ste and smmuv3_decode_config now return 0 if aborted or
bypassed config was found. Only bad config info produces negative
error values. In smmuv3_translate we more clearly differentiate
errors, bypass/smmu disabled, aborted and success cases. Also
trace points are differentiated.

Fixes: 9bde7f0674fe ("hw/arm/smmuv3: Implement translate callback")
Reported-by: address@hidden
Signed-off-by: address@hidden
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 32cfd7f39e0811036efd3a7a12d0f975ef57fdb3
      
https://github.com/qemu/qemu/commit/32cfd7f39e0811036efd3a7a12d0f975ef57fdb3
  Author: Eric Auger <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/arm/smmu-common.c
    M hw/arm/smmuv3.c
    M hw/arm/trace-events
    M include/hw/arm/smmu-common.h
    M include/hw/arm/smmuv3.h

  Log Message:
  -----------
  hw/arm/smmuv3: Cache/invalidate config data

Let's cache config data to avoid fetching and parsing STE/CD
structures on each translation. We invalidate them on data structure
invalidation commands.

We put in place a per-smmu mutex to protect the config cache. This
will be useful too to protect the IOTLB cache. The caches can be
accessed without BQL, ie. in IO dataplane. The same kind of mutex was
put in place in the intel viommu.

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: cc27ed81cf11d5b7ffc7eca9f31dfcd82c983c56
      
https://github.com/qemu/qemu/commit/cc27ed81cf11d5b7ffc7eca9f31dfcd82c983c56
  Author: Eric Auger <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/arm/smmu-common.c
    M hw/arm/smmuv3.c
    M hw/arm/trace-events
    M include/hw/arm/smmu-common.h

  Log Message:
  -----------
  hw/arm/smmuv3: IOTLB emulation

We emulate a TLB cache of size SMMU_IOTLB_MAX_SIZE=256.
It is implemented as a hash table whose key is a combination
of the 16b asid and 48b IOVA (Jenkins hash).

Entries are invalidated on TLB invalidation commands, either
globally, or per asid, or per asid/iova.

Signed-off-by: Eric Auger <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 832e4222c82071e4399cffdecd605abed5ac0c27
      
https://github.com/qemu/qemu/commit/832e4222c82071e4399cffdecd605abed5ac0c27
  Author: Eric Auger <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/arm/smmu-common.c
    M hw/arm/smmuv3.c
    M hw/arm/trace-events
    M include/hw/arm/smmu-common.h

  Log Message:
  -----------
  hw/arm/smmuv3: Add notifications on invalidation

On TLB invalidation commands, let's call registered
IOMMU notifiers. Those can only be UNMAP notifiers.
SMMUv3 does not support notification on MAP (VFIO).

This patch allows vhost use case where IOTLB API is notified
on each guest IOTLB invalidation.

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fda9aaa60ec27dfdbc1b70605e5439a6d1b30c2e
      
https://github.com/qemu/qemu/commit/fda9aaa60ec27dfdbc1b70605e5439a6d1b30c2e
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/misc/aspeed_scu.c
    M include/hw/misc/aspeed_scu.h

  Log Message:
  -----------
  aspeed/scu: introduce clock frequencies

All Aspeed SoC clocks are driven by an input source clock which can
have different frequencies : 24MHz or 25MHz, and also, on the Aspeed
AST2400 SoC, 48MHz. The H-PLL (CPU) clock is defined from a
calculation using parameters in the H-PLL Parameter register or from a
predefined set of frequencies if the setting is strapped by hardware
(Aspeed AST2400 SoC). The other clocks of the SoC are then defined
from the H-PLL using dividers.

We introduce first the APB clock because it should be used to drive
the Aspeed timer model.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e2a11ca859af1ffb4eb18abd9f3a73391008e2e4
      
https://github.com/qemu/qemu/commit/e2a11ca859af1ffb4eb18abd9f3a73391008e2e4
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/arm/aspeed_soc.c

  Log Message:
  -----------
  aspeed: initialize the SCU controller first

The System Control Unit should be initialized first as it drives all
the configuration of the SoC and other device models.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Acked-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9b945a9ee36a34eaeca412ef9ef35fbfe33c2c85
      
https://github.com/qemu/qemu/commit/9b945a9ee36a34eaeca412ef9ef35fbfe33c2c85
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M hw/arm/aspeed_soc.c
    M hw/timer/aspeed_timer.c
    M include/hw/timer/aspeed_timer.h

  Log Message:
  -----------
  aspeed/timer: use the APB frequency from the SCU

The timer controller can be driven by either an external 1MHz clock or
by the APB clock. Today, the model makes the assumption that the APB
frequency is always set to 24MHz but this is incorrect.

The AST2400 SoC on the palmetto machines uses a 48MHz input clock
source and the APB can be set to 48MHz. The consequence is a general
system slowdown. The QEMU machines using the AST2500 SoC do not seem
impacted today because the APB frequency is still set to 24MHz.

We fix the timer frequency for all SoCs by linking the Timer model to
the SCU model. The APB frequency driving the timers is now the one
configured for the SoC.

Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 00928a421d47f49691cace1207481b7aad31b1f1
      
https://github.com/qemu/qemu/commit/00928a421d47f49691cace1207481b7aad31b1f1
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M MAINTAINERS
    M accel/tcg/cputlb.c
    M accel/tcg/softmmu_template.h
    M hw/arm/aspeed_soc.c
    M hw/arm/omap1.c
    M hw/arm/smmu-common.c
    M hw/arm/smmuv3-internal.h
    M hw/arm/smmuv3.c
    M hw/arm/stellaris.c
    M hw/arm/trace-events
    M hw/dma/omap_dma.c
    M hw/i2c/omap_i2c.c
    M hw/input/pckbd.c
    M hw/input/tsc2005.c
    M hw/misc/aspeed_scu.c
    M hw/net/smc91c111.c
    M hw/net/stellaris_enet.c
    M hw/sd/omap_mmc.c
    M hw/ssi/aspeed_smc.c
    M hw/ssi/omap_spi.c
    M hw/ssi/xilinx_spips.c
    M hw/timer/aspeed_timer.c
    M include/exec/cpu-all.h
    M include/hw/arm/omap.h
    M include/hw/arm/smmu-common.h
    M include/hw/arm/smmuv3.h
    M include/hw/misc/aspeed_scu.h
    M include/hw/ssi/xilinx_spips.h
    M include/hw/timer/aspeed_timer.h
    M target/arm/helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180626' 
into staging

target-arm queue:
 * aspeed: set APB clocks correctly (fixes slowdown on palmetto)
 * smmuv3: cache config data and TLB entries
 * v7m/v8m: support read/write from MPU regions smaller than 1K
 * various: clean up logging/debug messages
 * xilinx_spips: Make dma transactions as per dma_burst_size

# gpg: Signature made Tue 26 Jun 2018 17:55:46 BST
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180626: (32 commits)
  aspeed/timer: use the APB frequency from the SCU
  aspeed: initialize the SCU controller first
  aspeed/scu: introduce clock frequencies
  hw/arm/smmuv3: Add notifications on invalidation
  hw/arm/smmuv3: IOTLB emulation
  hw/arm/smmuv3: Cache/invalidate config data
  hw/arm/smmuv3: Fix translate error handling
  target/arm: Handle small regions in get_phys_addr_pmsav8()
  target/arm: Set page (region) size in get_phys_addr_pmsav7()
  tcg: Support MMU protection regions smaller than TARGET_PAGE_SIZE
  hw/arm/stellaris: Use HWADDR_PRIx to display register address
  hw/arm/stellaris: Fix gptm_write() error message
  hw/net/smc91c111: Use qemu_log_mask(UNIMP) instead of fprintf
  hw/net/smc91c111: Use qemu_log_mask(GUEST_ERROR) instead of hw_error
  hw/net/stellaris_enet: Use qemu_log_mask(GUEST_ERROR) instead of hw_error
  hw/net/stellaris_enet: Fix a typo
  hw/arm/stellaris: Use qemu_log_mask(UNIMP) instead of fprintf
  hw/arm/omap: Use qemu_log_mask(GUEST_ERROR) instead of fprintf
  hw/arm/omap1: Use qemu_log_mask(GUEST_ERROR) instead of fprintf
  hw/i2c/omap_i2c: Use qemu_log_mask(UNIMP) instead of fprintf
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/7e2d08863b5c...00928a421d47
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