[Qemu-commits] [qemu/qemu] ed7846: i386: Add support for CPUID_8000_001E for AMD

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: ed78467a214595a63af7800a073a03ffe37cd7db
      
https://github.com/qemu/qemu/commit/ed78467a214595a63af7800a073a03ffe37cd7db
  Author: Babu Moger <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: Add support for CPUID_8000_001E for AMD

Add support for cpuid leaf CPUID_8000_001E. Build the config that closely
match the underlying hardware. Please refer to the Processor Programming
Reference (PPR) for AMD Family 17h Model for more details.

Signed-off-by: Babu Moger <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 081492ca8ab23f90d56414595ecfd09ddbacb8f6
      
https://github.com/qemu/qemu/commit/081492ca8ab23f90d56414595ecfd09ddbacb8f6
  Author: Daniel P. Berrangé <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: improve alignment of CPU model listing

Since the addition of the -IBRS CPU model variants, the descriptions
shown by '-cpu help' are not well aligned, as several model names
overflow the space allowed. Right aligning the CPU model names is also
not attractive, because it obscures the common name prefixes of many
models. The CPU model name field needs to be 4 characters larger, and
be left aligned instead.

Signed-off-by: Daniel P. Berrangé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: c7dbff4b3a6655f4769e6d283f34191122450384
      
https://github.com/qemu/qemu/commit/c7dbff4b3a6655f4769e6d283f34191122450384
  Author: Daniel P. Berrangé <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: improve sorting of CPU model names

The current list of CPU model names output by "-cpu help" is sorted
alphabetically based on the internal QOM class name. The text that is
displayed, however, uses the CPU model name, which is equivalent to the
QOM class name, minus a suffix. Unfortunately that suffix has an effect
on the sort ordering, for example, causing the various Broadwell
variants to appear reversed:

  x86 486
  x86 Broadwell-IBRS        Intel Core Processor (Broadwell, IBRS)
  x86 Broadwell-noTSX-IBRS  Intel Core Processor (Broadwell, no TSX, IBRS
  x86 Broadwell-noTSX       Intel Core Processor (Broadwell, no TSX)
  x86 Broadwell             Intel Core Processor (Broadwell)
  x86 Conroe                Intel Celeron_4x0 (Conroe/Merom Class Core 2)

By sorting on the actual CPU model name text that is displayed, the
result is

  x86 486
  x86 Broadwell             Intel Core Processor (Broadwell)
  x86 Broadwell-IBRS        Intel Core Processor (Broadwell, IBRS)
  x86 Broadwell-noTSX       Intel Core Processor (Broadwell, no TSX)
  x86 Broadwell-noTSX-IBRS  Intel Core Processor (Broadwell, no TSX, IBRS)
  x86 Conroe                Intel Celeron_4x0 (Conroe/Merom Class Core 2)

This requires extra string allocations during sorting, but this is not a
concern given the usage scenario and the number of CPU models that exist.

Signed-off-by: Daniel P. Berrangé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: cc643b1e7898414b56f551bbd42d4ed8c2ae127a
      
https://github.com/qemu/qemu/commit/cc643b1e7898414b56f551bbd42d4ed8c2ae127a
  Author: Daniel P. Berrangé <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: display known CPUID features linewrapped, in alphabetical order

When using '-cpu help' the list of CPUID features is grouped according
to the internal low level CPUID grouping. The data printed results in
very long lines too.

This combines to make it hard for users to read the output and identify
if QEMU knows about the feature they wish to use.

This change gets rid of the grouping of features and treats all flags as
single list. The list is sorted into alphabetical order and the printing
with line wrapping at the 77th column.

Signed-off-by: Daniel P. Berrangé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: f1a23522b03a569f13aad49294bb4c4b1a9500c7
      
https://github.com/qemu/qemu/commit/f1a23522b03a569f13aad49294bb4c4b1a9500c7
  Author: Eduardo Habkost <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: Remove osxsave CPUID flag name

OSXAVE is not a static feature flag: it changes dynamically at
runtime depending on CR4, and it was never configurable: KVM
never returned OSXSAVE on GET_SUPPORTED_CPUID, and it is not
included in TCG_EXT_FEATURES.

Remove OSXSAVE from the feature name array so users don't try to
configure it manually.

Signed-off-by: Eduardo Habkost <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 9ccb9784b57804f5c74434ad6ccb66650a015ffc
      
https://github.com/qemu/qemu/commit/9ccb9784b57804f5c74434ad6ccb66650a015ffc
  Author: Eduardo Habkost <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: Remove ospke CPUID flag name

OSPKE is not a static feature flag: it changes dynamically at
runtime depending on CR4, and it was never configurable: KVM
never returned OSPKE on GET_SUPPORTED_CPUID, and on TCG enables
it automatically if CR4_PKE_MASK is set.

Remove OSPKE from the feature name array so users don't try to
configure it manually.

Signed-off-by: Eduardo Habkost <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: a764f3f7197f4d7ad8fe8424269933de912224cb
      
https://github.com/qemu/qemu/commit/a764f3f7197f4d7ad8fe8424269933de912224cb
  Author: Konrad Rzeszutek Wilk <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: define the AMD 'amd-ssbd' CPUID feature bit

AMD future CPUs expose _two_ ways to utilize the Intel equivalant
of the Speculative Store Bypass Disable. The first is via
the virtualized VIRT_SPEC CTRL MSR (0xC001_011f) and the second
is via the SPEC_CTRL MSR (0x48). The document titled:
124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf

gives priority of SPEC CTRL MSR over the VIRT SPEC CTRL MSR.

A copy of this document is available at
      https://bugzilla.kernel.org/show_bug.cgi?id=199889

Anyhow, this means that on future AMD CPUs there will be  _two_ ways to
deal with SSBD.

Signed-off-by: Konrad Rzeszutek Wilk <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 254790a909a2f153d689bfa7d8e8f0386cda870d
      
https://github.com/qemu/qemu/commit/254790a909a2f153d689bfa7d8e8f0386cda870d
  Author: Konrad Rzeszutek Wilk <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: Define AMD's no SSB mitigation needed.

AMD future CPUs expose a mechanism to tell the guest that the
Speculative Store Bypass Disable is not needed and that the
CPU is all good.

This is exposed via the CPUID 8000_0008.EBX[26] bit.

See 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf

A copy of this document is available at
  https://bugzilla.kernel.org/show_bug.cgi?id=199889

Signed-off-by: Konrad Rzeszutek Wilk <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: f98bbd8304112187cafc3e636c31b2a3865d2717
      
https://github.com/qemu/qemu/commit/f98bbd8304112187cafc3e636c31b2a3865d2717
  Author: Babu Moger <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M target/i386/kvm.c

  Log Message:
  -----------
  i386: Allow TOPOEXT to be enabled on older kernels

Enabling TOPOEXT feature might cause compatibility issues if
older kernels does not set this feature. Lets set this feature
unconditionally.

Signed-off-by: Babu Moger <address@hidden>
Message-Id: <address@hidden>
[ehabkost: rewrite comment and commit message]
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 631be32155dbafa1fe886f2488127956c9120ba6
      
https://github.com/qemu/qemu/commit/631be32155dbafa1fe886f2488127956c9120ba6
  Author: Babu Moger <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: Fix up the Node id for CPUID_8000_001E

This is part of topoext support. To keep the compatibility, it is better
we support all the combination of nr_cores and nr_threads currently
supported. By allowing more nr_cores and nr_threads, we might end up with
more nodes than we can actually support with the real hardware. We need to
fix up the node id to make this work. We can achieve this by shifting the
socket_id bits left to address more nodes.

Signed-off-by: Babu Moger <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: e00516475c270dcb6705753da96063f95699abf2
      
https://github.com/qemu/qemu/commit/e00516475c270dcb6705753da96063f95699abf2
  Author: Babu Moger <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M include/hw/i386/pc.h
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: Enable TOPOEXT feature on AMD EPYC CPU

Enable TOPOEXT feature on EPYC CPU. This is required to support
hyperthreading on VM guests. Also extend xlevel to 0x8000001E.

Disable topoext on PC_COMPAT_2_12 and keep xlevel 0x8000000a.

Signed-off-by: Babu Moger <address@hidden>
Message-Id: <address@hidden>
[ehabkost: Added EPYC-IBPB.xlevel to PC_COMPAT_2_12]
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 6b2942f966d5e54c37d305c80f5f98d504c2bc55
      
https://github.com/qemu/qemu/commit/6b2942f966d5e54c37d305c80f5f98d504c2bc55
  Author: Babu Moger <address@hidden>
  Date:   2018-06-22 (Fri, 22 Jun 2018)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: Remove generic SMT thread check

Remove generic non-intel check while validating hyperthreading support.
Certain AMD CPUs can support hyperthreading now.

CPU family with TOPOEXT feature can support hyperthreading now.

Signed-off-by: Babu Moger <address@hidden>
Tested-by: Geoffrey McRae <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 0b6e9aa89e02c8b213af019aad816e00ba8243f8
      
https://github.com/qemu/qemu/commit/0b6e9aa89e02c8b213af019aad816e00ba8243f8
  Author: Eduardo Habkost <address@hidden>
  Date:   2018-06-25 (Mon, 25 Jun 2018)

  Changed paths:
    M accel/stubs/tcg-stub.c
    M audio/audio.c
    M cpus.c
    M exec.c
    M hw/audio/hda-codec.c
    M hw/audio/intel-hda.c
    M hw/audio/trace-events
    M include/hw/compat.h
    M scripts/qmp/qemu-ga-client
    M scripts/qmp/qmp
    M scripts/qmp/qmp-shell
    M scripts/qmp/qom-fuse
    M scripts/qmp/qom-get
    M scripts/qmp/qom-list
    M scripts/qmp/qom-set
    M scripts/qmp/qom-tree

  Log Message:
  -----------
  Merge branch 'master' of git://git.qemu.org/qemu into x86-next


  Commit: e409d9a158c77c650651e8118f6c86c8dc76eba6
      
https://github.com/qemu/qemu/commit/e409d9a158c77c650651e8118f6c86c8dc76eba6
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-26 (Tue, 26 Jun 2018)

  Changed paths:
    M include/hw/i386/pc.h
    M target/i386/cpu.c
    M target/i386/kvm.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' 
into staging

x86 queue, 2018-06-25

* Add TOPOEXT feature to EPYC CPU model
* AMD's amd-ssbd and amd-no-ssbd CPUID features
* Removed unused CPUID flag names: ospke, osxsave
* Better formatting of '-cpu help'

# gpg: Signature made Mon 25 Jun 2018 23:18:51 BST
# gpg:                using RSA key 2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <address@hidden>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-next-pull-request:
  i386: Remove generic SMT thread check
  i386: Enable TOPOEXT feature on AMD EPYC CPU
  i386: Fix up the Node id for CPUID_8000_001E
  i386: Allow TOPOEXT to be enabled on older kernels
  i386: Define AMD's no SSB mitigation needed.
  i386: define the AMD 'amd-ssbd' CPUID feature bit
  i386: Remove ospke CPUID flag name
  i386: Remove osxsave CPUID flag name
  i386: display known CPUID features linewrapped, in alphabetical order
  i386: improve sorting of CPU model names
  i386: improve alignment of CPU model listing
  i386: Add support for CPUID_8000_001E for AMD

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/595123df1d54...e409d9a158c7
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