[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 072f41: target/ppc: Don't require private l1d
|
From: |
GitHub |
|
Subject: |
[Qemu-commits] [qemu/qemu] 072f41: target/ppc: Don't require private l1d cache on POW... |
|
Date: |
Tue, 19 Jun 2018 04:57:49 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 072f416a53ead5211c987cb2068ee9dbd7ba06cc
https://github.com/qemu/qemu/commit/072f416a53ead5211c987cb2068ee9dbd7ba06cc
Author: Suraj Jitindar Singh <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M target/ppc/kvm.c
Log Message:
-----------
target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache
For cap_ppc_safe_cache to be set to workaround, we require both a l1d
cache flush instruction and private l1d cache.
On POWER8 don't require private l1d cache. This means a guest on a
POWER8 machine can make use of the cache flush workarounds.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b2540203bdf4a390c3489146eae82ce237303653
https://github.com/qemu/qemu/commit/b2540203bdf4a390c3489146eae82ce237303653
Author: Suraj Jitindar Singh <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/ppc/spapr_caps.c
Log Message:
-----------
ppc/spapr_caps: Don't disable cap_cfpc on POWER8 by default
In default_caps_with_cpu() we set spapr_cap_cfpc to broken for POWER8
processors and before.
Since we no longer require private l1d cache on POWER8 for this cap to
be set to workaround change this to default to broken for POWER7
processors and before.
Signed-off-by: Suraj Jitindar Singh <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e493786c9585d3f1d1a951c46c656821a47f5b34
https://github.com/qemu/qemu/commit/e493786c9585d3f1d1a951c46c656821a47f5b34
Author: Greg Kurz <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: drop empty #if/#endif block
Commit 9d6f106552fa moved the last line in this block to somewhere else,
but it forgot to remove the now useless #if/#endif.
Signed-off-by: Greg Kurz <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2c9dfdacc5a9f4db941c8f80597abae4658954ac
https://github.com/qemu/qemu/commit/2c9dfdacc5a9f4db941c8f80597abae4658954ac
Author: Greg Kurz <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/ppc/spapr_hcall.c
Log Message:
-----------
spapr: fix leak in h_client_architecture_support()
If the negotiated compat mode can't be set, but raw mode is supported,
we decide to ignore the error. An so, we should free it to prevent a
memory leak.
Signed-off-by: Greg Kurz <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 06fe3a5bf107e93a4478e9cb5ef306ca65a0dcc1
https://github.com/qemu/qemu/commit/06fe3a5bf107e93a4478e9cb5ef306ca65a0dcc1
Author: Mark Cave-Ayland <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/ppc/mac.h
M hw/ppc/mac_newworld.c
Log Message:
-----------
ppc: introduce Core99MachinesState for the mac99 machine
This is in preparation for adding configuration controlled via machine
options.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: f1114c17eeda907d0a290f25f970d695fc3b16de
https://github.com/qemu/qemu/commit/f1114c17eeda907d0a290f25f970d695fc3b16de
Author: Mark Cave-Ayland <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/misc/macio/macio.c
M hw/ppc/mac.h
M hw/ppc/mac_newworld.c
M include/hw/misc/macio/macio.h
M include/hw/ppc/ppc.h
Log Message:
-----------
mac_newworld: add via machine option to control mac99 VIA/ADB configuration
This option allows the VIA configuration to be controlled between 3
different possible setups: cuda, pmu-adb and pmu with USB rather than ADB
keyboard/mouse.
For the moment we don't do anything with the configuration except to pass
it to the macio device (the via-cuda parent) and also to the firmware via
the fw_cfg interface so that it can present the correct device tree.
The default is cuda which is the current default and so will have no
change in behaviour.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 7c4166a971b54a65900d9624ccd9669ba99d75ad
https://github.com/qemu/qemu/commit/7c4166a971b54a65900d9624ccd9669ba99d75ad
Author: Mark Cave-Ayland <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M default-configs/ppc-softmmu.mak
M hw/misc/macio/Makefile.objs
A hw/misc/macio/gpio.c
M hw/misc/macio/macio.c
M hw/misc/macio/trace-events
M hw/ppc/mac.h
A include/hw/misc/macio/gpio.h
M include/hw/misc/macio/macio.h
Log Message:
-----------
mac_newworld: add gpios to macio devices with PMU enabled
PMU-enabled New World Macs expose their GPIOs via a separate memory region
within the macio device.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 8f55ac13049f3c737373d9de8598a2a03e6a03f9
https://github.com/qemu/qemu/commit/8f55ac13049f3c737373d9de8598a2a03e6a03f9
Author: Mark Cave-Ayland <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/misc/macio/gpio.c
Log Message:
-----------
mac_newworld: wire up programmer switch to NMI handler
The programmer switch is wired up via an external GPIO pin and can be used
to aid debugging Mac guests.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: fb6649f172d6ea1a8d8980b7f93d31808eb06ff8
https://github.com/qemu/qemu/commit/fb6649f172d6ea1a8d8980b7f93d31808eb06ff8
Author: Mark Cave-Ayland <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/input/adb-kbd.c
M hw/input/adb-mouse.c
Log Message:
-----------
adb: fix read reg 3 byte ordering
According to the Apple ADB documentation, register 3 is a 2-byte register
with the device address in the first byte, and the handler ID in the second
byte.
This is currently the opposite away to which QEMU returns them so switch the
order around.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 84051eb400495745035b52e27fe67b962b7a58fa
https://github.com/qemu/qemu/commit/84051eb400495745035b52e27fe67b962b7a58fa
Author: Mark Cave-Ayland <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/input/adb-kbd.c
M hw/input/adb-mouse.c
M hw/input/adb.c
M include/hw/input/adb.h
Log Message:
-----------
adb: add property to disable direct reg 3 writes
MacOS 9 has a bug in its PMU driver whereby after configuring the ADB bus
devices it sends another write to reg 3 on both devices resetting them
both back to the same address.
Add a new disable_direct_reg3_writes property to ADBDevice to disable these
direct writes which can enabled just for the upcoming pmu-adb support.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: d811d61fbc6ca5f2be2185fd7cfa916e7ba613ce
https://github.com/qemu/qemu/commit/d811d61fbc6ca5f2be2185fd7cfa916e7ba613ce
Author: Mark Cave-Ayland <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M default-configs/ppc-softmmu.mak
M hw/misc/macio/Makefile.objs
M hw/misc/macio/macio.c
A hw/misc/macio/pmu.c
M hw/misc/macio/trace-events
M hw/ppc/mac.h
M hw/ppc/mac_newworld.c
M include/hw/misc/macio/macio.h
A include/hw/misc/macio/pmu.h
Log Message:
-----------
mac_newworld: add PMU device
The PMU device supercedes the CUDA device found on older New World Macs and
is supported by a larger number of guest OSs from OS 9 to OS X 10.5.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 52b438815ecc1cb799d943ef4fd710fe67cc7702
https://github.com/qemu/qemu/commit/52b438815ecc1cb799d943ef4fd710fe67cc7702
Author: Cédric Le Goater <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/intc/xics_kvm.c
Log Message:
-----------
xics_kvm: fix a build break
On CentOS 7.5, gcc-4.8.5-28.el7_5.1.ppc64le fails to build QEMU due to :
hw/intc/xics_kvm.c: In function ‘ics_set_kvm_state’:
hw/intc/xics_kvm.c:281:13: error: ‘ret’ may be used uninitialized in this
function [-Werror=maybe-uninitialized]
return ret;
Fix the breakage and also remove the extra error reporting as
kvm_device_access() already provides a substantial error message.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 7f5d6517e303e39d79f57ca92919725e03c9fad8
https://github.com/qemu/qemu/commit/7f5d6517e303e39d79f57ca92919725e03c9fad8
Author: Mark Cave-Ayland <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/misc/mos6522.c
Log Message:
-----------
mos6522: only clear the shift register interrupt upon write
According to the 6522 datasheet the shift register (SR) interrupt flag is
cleared upon write with no mention of any other interrupt flags.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 32a8c27b5dfc834abf7ada7c55fcc69c97ae0140
https://github.com/qemu/qemu/commit/32a8c27b5dfc834abf7ada7c55fcc69c97ae0140
Author: Mark Cave-Ayland <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/misc/mos6522.c
Log Message:
-----------
mos6522: remove additional interrupt flag filter from mos6522_update_irq()
The datasheet indicates that the interrupt is generated by ANDing the
interrupt flags register (IFR) with the interrupt enable register (IER)
but currently there is an extra filter for the SR and timer interrupts.
Remove this extra filter to allow interrupts to be generated by external
inputs on bits 1 and 2 of ports A and B.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b6c7e42f74ab244545e157a0f90a31c70a66f3eb
https://github.com/qemu/qemu/commit/b6c7e42f74ab244545e157a0f90a31c70a66f3eb
Author: Mark Cave-Ayland <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/misc/mos6522.c
M include/hw/misc/mos6522.h
Log Message:
-----------
mos6522: expose mos6522_update_irq() through MOS6522DeviceClass
In the case where we have an interrupt generated externally from inputs to
bits 1 and 2 of port A and/or port B, it is necessary to expose
mos6522_update_irq() so it can be called by the interrupt source.
Signed-off-by: Mark Cave-Ayland <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 2100b6b21ef9c64a3cca1582dbd573c17c97bc4a
https://github.com/qemu/qemu/commit/2100b6b21ef9c64a3cca1582dbd573c17c97bc4a
Author: BALATON Zoltan <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/display/sm501.c
Log Message:
-----------
sm501: Do not clear read only bits when writing registers
When writing registers that have read only bits we have to avoid
changing these bits as they may have non zero values. Make sure we use
the correct masks to mask out read only and reserved bits when
changing registers.
Also remove extra spaces from dram_control and arbitration_control
assignments.
Signed-off-by: BALATON Zoltan <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: b1d40d6e09c205dac108e0c21ec2fdaeb1bbaae8
https://github.com/qemu/qemu/commit/b1d40d6e09c205dac108e0c21ec2fdaeb1bbaae8
Author: David Gibson <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/ppc/spapr_cpu_core.c
Log Message:
-----------
spapr: Clean up cpu realize/unrealize paths
spapr_cpu_init() and spapr_cpu_destroy() are only called from the spapr
cpu core realize/unrealize paths, and really can only be called from there.
Those are all short functions, so fold the pairs together for simplicity.
While we're there rename some functions and change some parameter types
for brevity and clarity.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: 937c2146a6694b5bc987c2fa89917db4acc9ae39
https://github.com/qemu/qemu/commit/937c2146a6694b5bc987c2fa89917db4acc9ae39
Author: David Gibson <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/ppc/pnv_core.c
Log Message:
-----------
pnv: Fix some error handling cpu realize()
In pnv_core_realize() we call two functions with an Error * parameter in
succession, which will go badly if they both cause errors. In fact, a
failure in either of them indicates a qemu internal error, so we can just
use &error_abort in both cases.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: 08304a8689ef726fe1e3f61645a870fb53f67895
https://github.com/qemu/qemu/commit/08304a8689ef726fe1e3f61645a870fb53f67895
Author: David Gibson <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
M include/hw/ppc/pnv_core.h
Log Message:
-----------
pnv_core: Allocate cpu thread objects individually
Currently, we allocate space for all the cpu objects within a single core
in one big block. This was copied from an older version of the spapr code
and requires some ugly pointer manipulation to extract the individual
objects.
This design was due to a misunderstanding of qemu lifetime conventions and
has already been changed in spapr (in 94ad93bd "spapr_cpu_core: instantiate
CPUs separately".
Make an equivalent change in pnv_core to get rid of the nasty pointer
arithmetic.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: 3a24752112a046a5f9745b6b72e16646b4b0bcfd
https://github.com/qemu/qemu/commit/3a24752112a046a5f9745b6b72e16646b4b0bcfd
Author: David Gibson <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/ppc/pnv_core.c
Log Message:
-----------
pnv: Clean up cpu realize path
pnv_cpu_init() is only called from the the pnv cpu core realize path, and
really only can be called from there. So fold it into its caller, which
we also rename for brevity.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: 5e22e29201d80124bca0124f2034e72b698cbb6f
https://github.com/qemu/qemu/commit/5e22e29201d80124bca0124f2034e72b698cbb6f
Author: David Gibson <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/ppc/pnv_core.c
Log Message:
-----------
pnv: Add cpu unrealize path
Currently we don't have any unrealize path for pnv cpu cores. We get away
with this because we don't yet support cpu hotplug for pnv.
However, we're going to want it eventually, and in the meantime, it makes
it non-obvious why there are a bunch of allocations on the realize() path
that don't have matching frees.
So, implement the missing unrealize path.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Commit: dbb3e8d5da028a6cc4c576c6a0960bcf740cb035
https://github.com/qemu/qemu/commit/dbb3e8d5da028a6cc4c576c6a0960bcf740cb035
Author: Greg Kurz <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/ppc/spapr_cpu_core.c
Log Message:
-----------
spapr_cpu_core: convert last snprintf() to g_strdup_printf()
Because this is the preferred practice in QEMU.
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 27607c1cdc0d2939cc3059106f919bf6271ae652
https://github.com/qemu/qemu/commit/27607c1cdc0d2939cc3059106f919bf6271ae652
Author: Greg Kurz <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/ppc/spapr_cpu_core.c
Log Message:
-----------
spapr_cpu_core: fix potential leak in spapr_cpu_core_realize()
Commit 94ad93bd97684 (QEMU 2.12) switched to instantiate CPUs separately
but it missed to adapt the error path accordingly. If something fails in
the CPU creation loop, then the CPU object that was just created is leaked.
The error paths in this function are a bit obfuscated, and adding
yet another label to free this CPU object makes it worse. We should
move the block of the loop to a separate function, with a proper
rollback path, but this is a bigger cleanup.
For now, let's just fix the bug by adding the missing calls to
object_unref(). This will allow easier backport to older QEMU
versions.
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 9986ddec4ccdc1f6320c158be50274fe390b7bb2
https://github.com/qemu/qemu/commit/9986ddec4ccdc1f6320c158be50274fe390b7bb2
Author: Greg Kurz <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/ppc/spapr_cpu_core.c
Log Message:
-----------
spapr_cpu_core: add missing rollback on realization path
The spapr_realize_vcpu() function doesn't rollback in case of error.
This isn't a problem with coldplugged CPUs because the machine won't
start and QEMU will exit. Hotplug is a different story though: the
CPU thread is started under object_property_set_bool() and it assumes
it can access the CPU object.
If icp_create() fails, we return an error without unregistering the
reset handler for this CPU, and we let the underlying QEMU thread for
this CPU alive. Since spapr_cpu_core_realize() doesn't care to unrealize
already realized CPUs either, but happily frees all of them anyway, the
CPU thread crashes instantly:
(qemu) device_add host-spapr-cpu-core,core-id=1,id=gku
GKU: failing icp_create (cpu 0x11497fd0)
^^^^^^^^^^
Program received signal SIGSEGV, Segmentation fault.
[Switching to Thread 0x7fffee3feaa0 (LWP 24725)]
0x00000000104c8374 in object_dynamic_cast_assert (obj=0x11497fd0,
^^^^^^^^^^^^^^
pointer to the CPU object
623 trace_object_dynamic_cast_assert(obj ? obj->class->type->name
(gdb) p obj->class->type
$1 = (Type) 0x0
(gdb) p * obj
$2 = {class = 0x10ea9c10, free = 0x11244620,
^^^^^^^^^^
should be g_free
(gdb) p g_free
$3 = {<text variable, no debug info>} 0x7ffff282bef0 <g_free>
obj is a dangling pointer to the CPU that was just destroyed in
spapr_cpu_core_realize().
This patch adds proper rollback to both spapr_realize_vcpu() and
spapr_cpu_core_realize().
Signed-off-by: Greg Kurz <address@hidden>
[dwg: Fixed a conflict due to a change in my tree]
Signed-off-by: David Gibson <address@hidden>
Commit: d9f0e34cb7174aefa2a1f4a7d6631c62b1e0d05d
https://github.com/qemu/qemu/commit/d9f0e34cb7174aefa2a1f4a7d6631c62b1e0d05d
Author: Greg Kurz <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/ppc/spapr_cpu_core.c
Log Message:
-----------
spapr_cpu_core: introduce spapr_create_vcpu()
This moves some code out from spapr_cpu_core_realize() for clarity. No
functional change.
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 51c047283c567ea27084827c979681f3e28b920e
https://github.com/qemu/qemu/commit/51c047283c567ea27084827c979681f3e28b920e
Author: Cédric Le Goater <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: introduce a pnv_chip_core_realize() routine
This extracts from the PvChip realize routine the part creating the
cores. On Power9, we will need to create the cores after the Xive
interrupt controller is created.
Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: 7388efafc27c2f45d22c8edbc14b3154c0381c2e
https://github.com/qemu/qemu/commit/7388efafc27c2f45d22c8edbc14b3154c0381c2e
Author: David Gibson <address@hidden>
Date: 2018-06-16 (Sat, 16 Jun 2018)
Changed paths:
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_hcall.c
M include/hw/ppc/spapr_cpu_core.h
M target/ppc/cpu.h
M target/ppc/kvm.c
M target/ppc/translate_init.inc.c
Log Message:
-----------
target/ppc, spapr: Move VPA information to machine_data
CPUPPCState currently contains a number of fields containing the state of
the VPA. The VPA is a PAPR specific concept covering several guest/host
shared memory areas used to communicate some information with the
hypervisor.
As a PAPR concept this is really machine specific information, although it
is per-cpu, so it doesn't really belong in the core CPU state structure.
There's also other information that's per-cpu, but platform/machine
specific. So create a (void *)machine_data in PowerPCCPU which can be
used by the machine to locate per-cpu data. Intialization, lifetime and
cleanup of machine_data is entirely up to the machine type.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Greg Kurz <address@hidden>
Tested-by: Greg Kurz <address@hidden>
Commit: 844afc54ae229515a37f63519855661ad2d01d19
https://github.com/qemu/qemu/commit/844afc54ae229515a37f63519855661ad2d01d19
Author: Greg Kurz <address@hidden>
Date: 2018-06-18 (Mon, 18 Jun 2018)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
spapr: fix xics_system_init() error path
Commit 3d85885a1b1f3 tried to fix error handling, but it actually
went into the wrong direction by dropping the local Error *.
In the default KVM case, the rationale is to try the in-kernel XICS first,
and if not possible, to fallback to userland XICS. Passing errp everywhere
makes this fallback impossible if errp is &error_fatal (which happens to
be the case). And anyway, if the caller would pass a regular &local_err,
things would be worse: we could possibly pass an already set *errp to
error_setg() and crash, or return an error even in case of success.
So we definitely need a local Error * and only propagate it when we're
done with the fallback logic. This is what this patch does.
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>
Commit: e4a9a7303a70397a89ea23072419976032de4ddc
https://github.com/qemu/qemu/commit/e4a9a7303a70397a89ea23072419976032de4ddc
Author: Peter Maydell <address@hidden>
Date: 2018-06-19 (Tue, 19 Jun 2018)
Changed paths:
M default-configs/ppc-softmmu.mak
M hw/display/sm501.c
M hw/input/adb-kbd.c
M hw/input/adb-mouse.c
M hw/input/adb.c
M hw/intc/xics_kvm.c
M hw/misc/macio/Makefile.objs
A hw/misc/macio/gpio.c
M hw/misc/macio/macio.c
A hw/misc/macio/pmu.c
M hw/misc/macio/trace-events
M hw/misc/mos6522.c
M hw/ppc/mac.h
M hw/ppc/mac_newworld.c
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
M hw/ppc/spapr.c
M hw/ppc/spapr_caps.c
M hw/ppc/spapr_cpu_core.c
M hw/ppc/spapr_hcall.c
M include/hw/input/adb.h
A include/hw/misc/macio/gpio.h
M include/hw/misc/macio/macio.h
A include/hw/misc/macio/pmu.h
M include/hw/misc/mos6522.h
M include/hw/ppc/pnv_core.h
M include/hw/ppc/ppc.h
M include/hw/ppc/spapr_cpu_core.h
M target/ppc/cpu.h
M target/ppc/kvm.c
M target/ppc/translate_init.inc.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.0-20180618' into
staging
ppc patch queue 2018-06-18
Next batch of ppc and spapr related patches for the 3.0 release.
* Improved handling of Spectre/Meltdown mitigations for POWER8
* Numerous Mac machine type cleanups and improvements
* Cleanup to cpu realize/unrealize path for spapr
* Create a place for machine-specific per-cpu information, and
start moving some things to it
* Assorted bugfixes
# gpg: Signature made Mon 18 Jun 2018 04:52:37 BST
# gpg: using RSA key 6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg: aka "David Gibson (Red Hat) <address@hidden>"
# gpg: aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg: aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-3.0-20180618: (28 commits)
spapr: fix xics_system_init() error path
target/ppc, spapr: Move VPA information to machine_data
ppc/pnv: introduce a pnv_chip_core_realize() routine
spapr_cpu_core: introduce spapr_create_vcpu()
spapr_cpu_core: add missing rollback on realization path
spapr_cpu_core: fix potential leak in spapr_cpu_core_realize()
spapr_cpu_core: convert last snprintf() to g_strdup_printf()
pnv: Add cpu unrealize path
pnv: Clean up cpu realize path
pnv_core: Allocate cpu thread objects individually
pnv: Fix some error handling cpu realize()
spapr: Clean up cpu realize/unrealize paths
sm501: Do not clear read only bits when writing registers
mos6522: expose mos6522_update_irq() through MOS6522DeviceClass
mos6522: remove additional interrupt flag filter from mos6522_update_irq()
mos6522: only clear the shift register interrupt upon write
xics_kvm: fix a build break
mac_newworld: add PMU device
adb: add property to disable direct reg 3 writes
adb: fix read reg 3 byte ordering
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/c5ee5cd9db1e...e4a9a7303a70
**NOTE:** This service been marked for deprecation:
https://developer.github.com/changes/2018-04-25-github-services-deprecation/
Functionality will be removed from GitHub.com on January 31st, 2019.
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Qemu-commits] [qemu/qemu] 072f41: target/ppc: Don't require private l1d cache on POW...,
GitHub <=