[Qemu-commits] [qemu/qemu] 1dcf36: arm_gicv3_kvm: kvm_dist_get/put

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[Qemu-commits] [qemu/qemu] 1dcf36: arm_gicv3_kvm: kvm_dist_get/put_prior

From:	GitHub
Subject:	[Qemu-commits] [qemu/qemu] 1dcf36: arm_gicv3_kvm: kvm_dist_get/put_priority: skip the...
Date:	Fri, 15 Jun 2018 08:29:30 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 1dcf3675196a1cec616ce71b067d9498590a60a6
      
https://github.com/qemu/qemu/commit/1dcf3675196a1cec616ce71b067d9498590a60a6
  Author: Shannon Zhao <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M hw/intc/arm_gicv3_kvm.c

  Log Message:
  -----------
  arm_gicv3_kvm: kvm_dist_get/put_priority: skip the registers banked by 
GICR_IPRIORITYR

While for_each_dist_irq_reg loop starts from GIC_INTERNAL, it forgot to
offset the date array and index. This will overlap the GICR registers
value and leave the last GIC_INTERNAL irq's registers out of update.

Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Signed-off-by: Shannon Zhao <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 519655e62590f8eaed1a17d159b70be24d74967e
      
https://github.com/qemu/qemu/commit/519655e62590f8eaed1a17d159b70be24d74967e
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M hw/arm/mps2-tz.c

  Log Message:
  -----------
  hw/arm/mps2-tz: Put ethernet controller behind PPC

The ethernet controller in the AN505 MPC FPGA image is behind
the same AHB Peripheral Protection Controller that handles
the graphics and GPIOs. (In the documentation this is clear
in the block diagram but the ethernet controller was omitted
from the table listing devices connected to the PPC.)
The ethernet sits behind AHB PPCEXP0 interface 5. We had
incorrectly claimed that this was a "gpio4", but there are
only 4 GPIOs in this image.

Correct the QEMU model to match the hardware.

Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden


  Commit: d2af524a18dae38691cd13e1aa70d133e9c645b7
      
https://github.com/qemu/qemu/commit/d2af524a18dae38691cd13e1aa70d133e9c645b7
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M hw/sh4/sh7750.c

  Log Message:
  -----------
  hw/sh/sh7750: Convert away from old_mmio

Convert the sh7750 device away from using the old_mmio field
of MemoryRegionOps. This device is used by the sh4 r2d board.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: bb428791c8bf9ffed6940e15c6c255c28ea74e72
      
https://github.com/qemu/qemu/commit/bb428791c8bf9ffed6940e15c6c255c28ea74e72
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M hw/m68k/mcf5206.c

  Log Message:
  -----------
  hw/m68k/mcf5206: Convert away from old_mmio

Convert the mcf5206 device away from using the old_mmio field
of MemoryRegionOps. This device is used by the an5206 board.

Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Thomas Huth <address@hidden>
Message-id: address@hidden


  Commit: a4afb28dae411dae1cc6e5b0d28afd818609cb3d
      
https://github.com/qemu/qemu/commit/a4afb28dae411dae1cc6e5b0d28afd818609cb3d
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M hw/block/pflash_cfi02.c

  Log Message:
  -----------
  hw/block/pflash_cfi02: Convert away from old_mmio

Convert the pflash_cfi02 device away from using the old_mmio field
of MemoryRegionOps.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Acked-by: Max Reitz <address@hidden>
Message-id: address@hidden


  Commit: a821541edf2bf8e73d6a5a4d9f80fec2b4110db2
      
https://github.com/qemu/qemu/commit/a821541edf2bf8e73d6a5a4d9f80fec2b4110db2
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M hw/watchdog/wdt_i6300esb.c

  Log Message:
  -----------
  hw/watchdog/wdt_i6300esb: Convert away from old_mmio

Convert the wdt_i6300esb device away from using the old_mmio field
of MemoryRegionOps.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: 5876503c0fb4728ae875e30fe9da82c09ba38ddd
      
https://github.com/qemu/qemu/commit/5876503c0fb4728ae875e30fe9da82c09ba38ddd
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M hw/input/pckbd.c

  Log Message:
  -----------
  hw/input/pckbd: Convert away from old_mmio

Convert the pckbd device away from using the old_mmio field
of MemoryRegionOps. This change only affects the memory-mapped
variant of the i8042, which is used by the Unicore32 'puv3'
board and the MIPS Jazz boards 'magnum' and 'pica61'.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: 05b4940bf1d6f6b32169d233562fafde1789cdbe
      
https://github.com/qemu/qemu/commit/05b4940bf1d6f6b32169d233562fafde1789cdbe
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M hw/char/parallel.c

  Log Message:
  -----------
  hw/char/parallel: Convert away from old_mmio

Convert the parallel device away from using the old_mmio field
of MemoryRegionOps. This change only affects the memory-mapped
variant, which is used by the MIPS Jazz boards 'magnum' and 'pica61'.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: f04d44654d85e25f71e00d3295db03a4ea95d8d8
      
https://github.com/qemu/qemu/commit/f04d44654d85e25f71e00d3295db03a4ea95d8d8
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M hw/arm/stellaris.c

  Log Message:
  -----------
  stellaris: Stop using armv7m_init()

The stellaris board is still using the legacy armv7m_init() function,
which predates conversion of the ARMv7M into a proper QOM container
object. Make the board code directly create the ARMv7M object instead.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden


  Commit: 38d81dafb316291356db9591e6752b27848b2ea4
      
https://github.com/qemu/qemu/commit/38d81dafb316291356db9591e6752b27848b2ea4
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M hw/arm/armv7m.c
    M include/hw/arm/arm.h

  Log Message:
  -----------
  hw/arm/armv7m: Remove unused armv7m_init() function

Remove the now-unused armv7m_init() function. This was a legacy from
before we properly QOMified ARMv7M, and it has some flaws:

 * it combines work that needs to be done by an SoC object (creating
   and initializing the TYPE_ARMV7M object) with work that needs to
   be done by the board model (setting the system up to load the ELF
   file specified with -kernel)
 * TYPE_ARMV7M creation failure is fatal, but an SoC object wants to
   arrange to propagate the failure outward
 * it uses allocate-and-create via qdev_create() whereas the current
   preferred style for SoC objects is to do creation in-place

Board and SoC models can instead do the two jobs this function
was doing themselves, in the right places and with whatever their
preferred style/error handling is.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden


  Commit: 95f875654ae8b433b50a2bc7858e34af957cbaa4
      
https://github.com/qemu/qemu/commit/95f875654ae8b433b50a2bc7858e34af957cbaa4
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M hw/arm/armv7m.c
    M hw/intc/armv7m_nvic.c
    M target/arm/cpu.c

  Log Message:
  -----------
  arm: Don't crash if user tries to use a Cortex-M CPU without an NVIC

The Cortex-M CPU and its NVIC are two intimately intertwined parts of
the same hardware; it is not possible to use one without the other.
Unfortunately a lot of our board models don't do any sanity checking
on the CPU type the user asks for, so a command line like
    qemu-system-arm -M versatilepb -cpu cortex-m3
will create an M3 without an NVIC, and coredump immediately.
In the other direction, trying a non-M-profile CPU in an M-profile
board won't blow up, but doesn't do anything useful either:
    qemu-system-arm -M lm3s6965evb -cpu arm926

Add some checking in the NVIC and CPU realize functions that the
user isn't trying to use an NVIC without an M-profile CPU or
an M-profile CPU without an NVIC, so we can produce a helpful
error message rather than a core dump.

Fixes: https://bugs.launchpad.net/qemu/+bug/1766896
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: f81804a52b5d4609f68ea367a55a2ccb4cc99f77
      
https://github.com/qemu/qemu/commit/f81804a52b5d4609f68ea367a55a2ccb4cc99f77
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M hw/core/or-irq.c
    M include/hw/or-irq.h

  Log Message:
  -----------
  hw/core/or-irq: Support more than 16 inputs to an OR gate

For the IoTKit MPC support, we need to wire together the
interrupt outputs of 17 MPCs; this exceeds the current
value of MAX_OR_LINES. Increase MAX_OR_LINES to 32 (which
should be enough for anyone).

The tricky part is retaining the migration compatibility for
existing OR gates; we add a subsection which is only used
for larger OR gates, and define it such that we can freely
increase MAX_OR_LINES in future (or even move to a dynamically
allocated levels[] array without an upper size limit) without
breaking compatibility.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: ace4109011b4912b24e76f152e2cf010e78819c5
      
https://github.com/qemu/qemu/commit/ace4109011b4912b24e76f152e2cf010e78819c5
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M accel/tcg/cputlb.c
    M include/exec/cpu-defs.h

  Log Message:
  -----------
  cpu-defs.h: Document CPUIOTLBEntry 'addr' field

The 'addr' field in the CPUIOTLBEntry struct has a rather non-obvious
use; add a comment documenting it (reverse-engineered from what
the code that sets it is doing).

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 2d54f19401bc54b3b56d1cc44c96e4087b604b97
      
https://github.com/qemu/qemu/commit/2d54f19401bc54b3b56d1cc44c96e4087b604b97
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M accel/tcg/cputlb.c
    M exec.c
    M include/exec/exec-all.h

  Log Message:
  -----------
  cputlb: Pass cpu_transaction_failed() the correct physaddr

The API for cpu_transaction_failed() says that it takes the physical
address for the failed transaction. However we were actually passing
it the offset within the target MemoryRegion. We don't currently
have any target CPU implementations of this hook that require the
physical address; fix this bug so we don't get confused if we ever
do add one.

Suggested-by: Paolo Bonzini <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 2948f0cde3974185ad22d6721438cf85df852877
      
https://github.com/qemu/qemu/commit/2948f0cde3974185ad22d6721438cf85df852877
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M CODING_STYLE

  Log Message:
  -----------
  CODING_STYLE: Define our preferred form for multiline comments

The codebase has a bit of a mix of different multiline
comment styles. State a preference for the Linux kernel
style:
    /*
     * Star on the left for each line.
     * Leading slash-star and trailing star-slash
     * each go on a line of their own.
     */

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Eric Blake <address@hidden>
Reviewed-by: Cornelia Huck <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Reviewed-by: Alex Williamson <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: John Snow <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden


  Commit: afa4f6653dca095f63f3fe7f2001e9334f5676c1
      
https://github.com/qemu/qemu/commit/afa4f6653dca095f63f3fe7f2001e9334f5676c1
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M docs/devel/loads-stores.rst
    M include/exec/cpu-all.h
    M include/qemu/bswap.h

  Log Message:
  -----------
  bswap: Add new stn_*_p() and ldn_*_p() memory access functions

There's a common pattern in QEMU where a function needs to perform
a data load or store of an N byte integer in a particular endianness.
At the moment this is handled by doing a switch() on the size and
calling the appropriate ld*_p or st*_p function for each size.

Provide a new family of functions ldn_*_p() and stn_*_p() which
take the size as an argument and do the switch() themselves.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 22672c6075a16d1998e37686f02ed4bd2fb30f78
      
https://github.com/qemu/qemu/commit/22672c6075a16d1998e37686f02ed4bd2fb30f78
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M exec.c

  Log Message:
  -----------
  exec.c: Don't accidentally sign-extend 4-byte loads in subpage_read()

In subpage_read() we perform a load of the data into a local buffer
which we then access using ldub_p(), lduw_p(), ldl_p() or ldq_p()
depending on its size, storing the result into the uint64_t *data.
Since ldl_p() returns an 'int', this means that for the 4-byte
case we will sign-extend the data, whereas for 1 and 2 byte
reads we zero-extend it.

This ought not to matter since the caller will likely ignore values in
the high bytes of the data, but add a cast so that we're consistent.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 6d3ede5410e05c5f6221dab1daf99164fd6bf879
      
https://github.com/qemu/qemu/commit/6d3ede5410e05c5f6221dab1daf99164fd6bf879
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M exec.c

  Log Message:
  -----------
  exec.c: Use stn_p() and ldn_p() instead of explicit switches

Now we have stn_p() and ldn_p() we can use them in various
functions in exec.c that used to have their own switch-on-size code.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 66f2dbd783d0b6172043e3679171421b2d0bac11
      
https://github.com/qemu/qemu/commit/66f2dbd783d0b6172043e3679171421b2d0bac11
  Author: Richard Henderson <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M target/arm/translate-a64.h

  Log Message:
  -----------
  target/arm: Extend vec_reg_offset to larger sizes

Rearrange the arithmetic so that we are agnostic about the total size
of the vector and the size of the element.  This will allow us to index
up to the 32nd byte and with 16-byte elements.

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 30562ab716bcec0bf718b47b5268949856b17604
      
https://github.com/qemu/qemu/commit/30562ab716bcec0bf718b47b5268949856b17604
  Author: Richard Henderson <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE Permute - Unpredicated Group

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d731d8cb3c74258669211f065c918353eb7b8f4a
      
https://github.com/qemu/qemu/commit/d731d8cb3c74258669211f065c918353eb7b8f4a
  Author: Richard Henderson <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE Permute - Predicates Group

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 234b48e9c68759aea78ff5a1e49c2ba806cd1d83
      
https://github.com/qemu/qemu/commit/234b48e9c68759aea78ff5a1e49c2ba806cd1d83
  Author: Richard Henderson <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE Permute - Interleaving Group

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 3ca879aeb3412bc2be35d01a7bedf5fada960b5d
      
https://github.com/qemu/qemu/commit/3ca879aeb3412bc2be35d01a7bedf5fada960b5d
  Author: Richard Henderson <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE compress active elements

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ef23cb726dc32375bc2fca7ac3e9f34816f6ee13
      
https://github.com/qemu/qemu/commit/ef23cb726dc32375bc2fca7ac3e9f34816f6ee13
  Author: Richard Henderson <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE conditionally broadcast/extract element

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 792a557847697235037fea30eaaacb9b45b4c9e5
      
https://github.com/qemu/qemu/commit/792a557847697235037fea30eaaacb9b45b4c9e5
  Author: Richard Henderson <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M target/arm/sve.decode
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE copy to vector (predicated)

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: dae8fb9019d2aa6ccb151a19871df40de6c98e29
      
https://github.com/qemu/qemu/commit/dae8fb9019d2aa6ccb151a19871df40de6c98e29
  Author: Richard Henderson <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE reverse within elements

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b48ff24098c72f86e187e6abb7e9ca4de40a7fb4
      
https://github.com/qemu/qemu/commit/b48ff24098c72f86e187e6abb7e9ca4de40a7fb4
  Author: Richard Henderson <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE vector splice (predicated)

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d3fe4a29d754dee73cbf3cb7584db222981179ac
      
https://github.com/qemu/qemu/commit/d3fe4a29d754dee73cbf3cb7584db222981179ac
  Author: Richard Henderson <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE Select Vectors Group

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 757f9cff1b63895bfd6fc8d66a6e52d7c40baa7b
      
https://github.com/qemu/qemu/commit/757f9cff1b63895bfd6fc8d66a6e52d7c40baa7b
  Author: Richard Henderson <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE Integer Compare - Vectors Group

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 38cadeba0daf0f16cf2aeaa5b2752b26fb0676c5
      
https://github.com/qemu/qemu/commit/38cadeba0daf0f16cf2aeaa5b2752b26fb0676c5
  Author: Richard Henderson <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE Integer Compare - Immediate Group

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 35da316f5e847292ffbe7b6d16cd3988043dfe22
      
https://github.com/qemu/qemu/commit/35da316f5e847292ffbe7b6d16cd3988043dfe22
  Author: Richard Henderson <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE Partition Break Group

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9ee3a611de28b8d0862fa687215b04b5aad20747
      
https://github.com/qemu/qemu/commit/9ee3a611de28b8d0862fa687215b04b5aad20747
  Author: Richard Henderson <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE Predicate Count Group

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: caf1cefc72be98497e0907d0e07f4327fc641e96
      
https://github.com/qemu/qemu/commit/caf1cefc72be98497e0907d0e07f4327fc641e96
  Author: Richard Henderson <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE Integer Compare - Scalars Group

Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ed49196125360c037d7f23c1c315a85cc234e72d
      
https://github.com/qemu/qemu/commit/ed49196125360c037d7f23c1c315a85cc234e72d
  Author: Richard Henderson <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M target/arm/sve.decode
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement FDUP/DUP

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6e6a157d683058d86a224cf128320d67b0915365
      
https://github.com/qemu/qemu/commit/6e6a157d683058d86a224cf128320d67b0915365
  Author: Richard Henderson <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-sve.c

  Log Message:
  -----------
  target/arm: Implement SVE Integer Wide Immediate - Unpredicated Group

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 29b80469dc51ae4064e9ef9223967882d2610523
      
https://github.com/qemu/qemu/commit/29b80469dc51ae4064e9ef9223967882d2610523
  Author: Richard Henderson <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M target/arm/helper-sve.h
    M target/arm/helper.h
    M target/arm/sve.decode
    M target/arm/translate-sve.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  target/arm: Implement SVE Floating Point Arithmetic - Unpredicated Group

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: acd9575e59da1bfc21a1feccb00c5dddd45328f7
      
https://github.com/qemu/qemu/commit/acd9575e59da1bfc21a1feccb00c5dddd45328f7
  Author: Joel Stanley <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M hw/misc/aspeed_scu.c

  Log Message:
  -----------
  aspeed_scu: Implement RNG register

The ASPEED SoCs contain a single register that returns random data when
read. This models that register so that guests can use it.

The random number data register has a corresponding control register,
however it returns data regardless of the state of the enabled bit, so
the model follows this behaviour.

When the qcrypto call fails we exit as the guest uses the random number
device to feed it's entropy pool, which is used for cryptographic
purposes.

Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2151b044fdca74a4fe7148f302ba9d6191516744
      
https://github.com/qemu/qemu/commit/2151b044fdca74a4fe7148f302ba9d6191516744
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  m25p80: add support for two bytes WRSR for Macronix chips

On Macronix chips, two bytes can written to the WRSR. First byte will
configure the status register and the second the configuration
register. It is important to save the configuration value as it
contains the dummy cycle setting when using dual or quad IO mode.

Signed-off-by: Cédric Le Goater <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 21f402093c5ee7363f5ba56916cd5c651b424fef
      
https://github.com/qemu/qemu/commit/21f402093c5ee7363f5ba56916cd5c651b424fef
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M include/exec/memory.h
    M memory.c

  Log Message:
  -----------
  iommu: Add IOMMU index concept to IOMMU API

If an IOMMU supports mappings that care about the memory
transaction attributes, then it no longer has a unique
address -> output mapping, but more than one. We can
represent these using an IOMMU index, analogous to TCG's
mmu indexes.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: cb1efcf462a2ff72926e0c5267a2e1d95490f347
      
https://github.com/qemu/qemu/commit/cb1efcf462a2ff72926e0c5267a2e1d95490f347
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M hw/i386/intel_iommu.c
    M hw/ppc/spapr_iommu.c
    M hw/s390x/s390-pci-inst.c
    M hw/vfio/common.c
    M hw/virtio/vhost.c
    M include/exec/memory.h
    M memory.c

  Log Message:
  -----------
  iommu: Add IOMMU index argument to notifier APIs

Add support for multiple IOMMU indexes to the IOMMU notifier APIs.
When initializing a notifier with iommu_notifier_init(), the caller
must pass the IOMMU index that it is interested in. When a change
happens, the IOMMU implementation must pass
memory_region_notify_iommu() the IOMMU index that has changed and
that notifiers must be called for.

IOMMUs which support only a single index don't need to change.
Callers which only really support working with IOMMUs with a single
index can use the result of passing MEMTXATTRS_UNSPECIFIED to
memory_region_iommu_attrs_to_index().

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: 2c91bcf273ffb95898d2ca901b699558d9e73fd1
      
https://github.com/qemu/qemu/commit/2c91bcf273ffb95898d2ca901b699558d9e73fd1
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M exec.c
    M hw/alpha/typhoon.c
    M hw/arm/smmuv3.c
    M hw/dma/rc4030.c
    M hw/i386/amd_iommu.c
    M hw/i386/intel_iommu.c
    M hw/ppc/spapr_iommu.c
    M hw/s390x/s390-pci-bus.c
    M hw/sparc/sun4m_iommu.c
    M hw/sparc64/sun4u_iommu.c
    M include/exec/memory.h
    M memory.c

  Log Message:
  -----------
  iommu: Add IOMMU index argument to translate method

Add an IOMMU index argument to the translate method of
IOMMUs. Since all of our current IOMMU implementations
support only a single IOMMU index, this has no effect
on the behaviour.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: 1f871c5e6b0f30644a60a81a6a7aadb3afb030ac
      
https://github.com/qemu/qemu/commit/1f871c5e6b0f30644a60a81a6a7aadb3afb030ac
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M accel/tcg/cputlb.c
    M exec.c
    M include/exec/exec-all.h
    M include/qom/cpu.h

  Log Message:
  -----------
  exec.c: Handle IOMMUs in address_space_translate_for_iotlb()

Currently we don't support board configurations that put an IOMMU
in the path of the CPU's memory transactions, and instead just
assert() if the memory region fonud in address_space_translate_for_iotlb()
is an IOMMUMemoryRegion.

Remove this limitation by having the function handle IOMMUs.
This is mostly straightforward, but we must make sure we have
a notifier registered for every IOMMU that a transaction has
passed through, so that we can flush the TLB appropriately
when any of the IOMMUs change their mappings.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: 14120108f87b3f9e1beacdf0a6096e464e62bb65
      
https://github.com/qemu/qemu/commit/14120108f87b3f9e1beacdf0a6096e464e62bb65
  Author: Julia Suvorova <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Allow ARMv6-M Thumb2 instructions

ARMv6-M supports 6 Thumb2 instructions. This patch checks for these
instructions and allows their execution.
Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit.

This patch is required for future Cortex-M0 support.

Signed-off-by: Julia Suvorova <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Message-id: address@hidden
[PMM: move armv6m_insn[] and armv6m_mask[] closer to
 point of use, and mark 'const'. Check for M-and-not-v7
 rather than M-and-6.]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 81d386479640879d87ab9661c8fb44d586c965ec
      
https://github.com/qemu/qemu/commit/81d386479640879d87ab9661c8fb44d586c965ec
  Author: Peter Maydell <address@hidden>
  Date:   2018-06-15 (Fri, 15 Jun 2018)

  Changed paths:
    M CODING_STYLE
    M accel/tcg/cputlb.c
    M docs/devel/loads-stores.rst
    M exec.c
    M hw/alpha/typhoon.c
    M hw/arm/armv7m.c
    M hw/arm/mps2-tz.c
    M hw/arm/smmuv3.c
    M hw/arm/stellaris.c
    M hw/block/m25p80.c
    M hw/block/pflash_cfi02.c
    M hw/char/parallel.c
    M hw/core/or-irq.c
    M hw/dma/rc4030.c
    M hw/i386/amd_iommu.c
    M hw/i386/intel_iommu.c
    M hw/input/pckbd.c
    M hw/intc/arm_gicv3_kvm.c
    M hw/intc/armv7m_nvic.c
    M hw/m68k/mcf5206.c
    M hw/misc/aspeed_scu.c
    M hw/ppc/spapr_iommu.c
    M hw/s390x/s390-pci-bus.c
    M hw/s390x/s390-pci-inst.c
    M hw/sh4/sh7750.c
    M hw/sparc/sun4m_iommu.c
    M hw/sparc64/sun4u_iommu.c
    M hw/vfio/common.c
    M hw/virtio/vhost.c
    M hw/watchdog/wdt_i6300esb.c
    M include/exec/cpu-all.h
    M include/exec/cpu-defs.h
    M include/exec/exec-all.h
    M include/exec/memory.h
    M include/hw/arm/arm.h
    M include/hw/or-irq.h
    M include/qemu/bswap.h
    M include/qom/cpu.h
    M memory.c
    M target/arm/cpu.c
    M target/arm/helper-sve.h
    M target/arm/helper.h
    M target/arm/sve.decode
    M target/arm/sve_helper.c
    M target/arm/translate-a64.h
    M target/arm/translate-sve.c
    M target/arm/translate.c
    M target/arm/vec_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180615' 
into staging

target-arm and miscellaneous queue:
 * fix KVM state save/restore for GICv3 priority registers for high IRQ numbers
 * hw/arm/mps2-tz: Put ethernet controller behind PPC
 * hw/sh/sh7750: Convert away from old_mmio
 * hw/m68k/mcf5206: Convert away from old_mmio
 * hw/block/pflash_cfi02: Convert away from old_mmio
 * hw/watchdog/wdt_i6300esb: Convert away from old_mmio
 * hw/input/pckbd: Convert away from old_mmio
 * hw/char/parallel: Convert away from old_mmio
 * armv7m: refactor to get rid of armv7m_init() function
 * arm: Don't crash if user tries to use a Cortex-M CPU without an NVIC
 * hw/core/or-irq: Support more than 16 inputs to an OR gate
 * cpu-defs.h: Document CPUIOTLBEntry 'addr' field
 * cputlb: Pass cpu_transaction_failed() the correct physaddr
 * CODING_STYLE: Define our preferred form for multiline comments
 * Add and use new stn_*_p() and ldn_*_p() memory access functions
 * target/arm: More parts of the upcoming SVE support
 * aspeed_scu: Implement RNG register
 * m25p80: add support for two bytes WRSR for Macronix chips
 * exec.c: Handle IOMMUs being in the path of TCG CPU memory accesses
 * target/arm: Allow ARMv6-M Thumb2 instructions

# gpg: Signature made Fri 15 Jun 2018 15:24:03 BST
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180615: (43 commits)
  target/arm: Allow ARMv6-M Thumb2 instructions
  exec.c: Handle IOMMUs in address_space_translate_for_iotlb()
  iommu: Add IOMMU index argument to translate method
  iommu: Add IOMMU index argument to notifier APIs
  iommu: Add IOMMU index concept to IOMMU API
  m25p80: add support for two bytes WRSR for Macronix chips
  aspeed_scu: Implement RNG register
  target/arm: Implement SVE Floating Point Arithmetic - Unpredicated Group
  target/arm: Implement SVE Integer Wide Immediate - Unpredicated Group
  target/arm: Implement FDUP/DUP
  target/arm: Implement SVE Integer Compare - Scalars Group
  target/arm: Implement SVE Predicate Count Group
  target/arm: Implement SVE Partition Break Group
  target/arm: Implement SVE Integer Compare - Immediate Group
  target/arm: Implement SVE Integer Compare - Vectors Group
  target/arm: Implement SVE Select Vectors Group
  target/arm: Implement SVE vector splice (predicated)
  target/arm: Implement SVE reverse within elements
  target/arm: Implement SVE copy to vector (predicated)
  target/arm: Implement SVE conditionally broadcast/extract element
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/2702c2d3eb74...81d386479640
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