[Qemu-commits] [qemu/qemu] a18495: i386: add KnightsMill cpu model

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: a18495159a35e9c5973d9aa0f612a97318bf684d
      
https://github.com/qemu/qemu/commit/a18495159a35e9c5973d9aa0f612a97318bf684d
  Author: Boqun Feng <address@hidden>
  Date:   2018-05-15 (Tue, 15 May 2018)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: add KnightsMill cpu model

A new cpu model called "KnightsMill" is added to model Knights Mill
processors.  Compared to "Skylake-Server" cpu model, the following
features are added:

        avx512_4vnniw avx512_4fmaps avx512pf avx512er avx512_vpopcntdq

and the following features are removed:

        pcid invpcid clflushopt avx512dq avx512bw clwb smap rtm mpx
        xsavec xgetbv1 hle

Signed-off-by: Boqun Feng <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 0da0fb062841d0dcd8ba47e4a989d2e952cdf0ff
      
https://github.com/qemu/qemu/commit/0da0fb062841d0dcd8ba47e4a989d2e952cdf0ff
  Author: Jingqi Liu <address@hidden>
  Date:   2018-05-15 (Tue, 15 May 2018)

  Changed paths:
    M target/i386/cpu.c
    M target/i386/cpu.h

  Log Message:
  -----------
  x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu feature

The CLDEMOTE instruction hints to hardware that the cache line that
contains the linear address should be moved("demoted") from
the cache(s) closest to the processor core to a level more distant
from the processor core. This may accelerate subsequent accesses
to the line by other cores in the same coherence domain,
especially if the line was written by the core that demotes the line.

Intel Snow Ridge has added new cpu feature, CLDEMOTE.
The new cpu feature needs to be exposed to guest VM.

The bit definition:
CPUID.(EAX=7,ECX=0):ECX[bit 25] CLDEMOTE

The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf

Signed-off-by: Jingqi Liu <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 7e3482f824809e1f6ffeb5bb8103ba27a7d1a52a
      
https://github.com/qemu/qemu/commit/7e3482f824809e1f6ffeb5bb8103ba27a7d1a52a
  Author: Eduardo Habkost <address@hidden>
  Date:   2018-05-15 (Tue, 15 May 2018)

  Changed paths:
    M target/i386/cpu.c
    M target/i386/cpu.h

  Log Message:
  -----------
  i386: Helpers to encode cache information consistently

Instead of having a collection of macros that need to be used in
complex expressions to build CPUID data, define a CPUCacheInfo
struct that can hold information about a given cache.  Helper
functions will take a CPUCacheInfo struct as input to encode
CPUID leaves for a cache.

This will help us ensure consistency between cache information
CPUID leaves, and make the existing inconsistencies in CPUID info
more visible.

Signed-off-by: Eduardo Habkost <address@hidden>
Signed-off-by: Babu Moger <address@hidden>
Tested-by: Geoffrey McRae <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 6aaeb05492ef668f415324f43e7d875c0f1e90b3
      
https://github.com/qemu/qemu/commit/6aaeb05492ef668f415324f43e7d875c0f1e90b3
  Author: Babu Moger <address@hidden>
  Date:   2018-05-15 (Tue, 15 May 2018)

  Changed paths:
    M target/i386/cpu.c
    M target/i386/cpu.h

  Log Message:
  -----------
  i386: Add cache information in X86CPUDefinition

Add cache information in X86CPUDefinition and CPUX86State.

Signed-off-by: Babu Moger <address@hidden>
Tested-by: Geoffrey McRae <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: fe52acd2a054b97765963a42037f2f886545e30c
      
https://github.com/qemu/qemu/commit/fe52acd2a054b97765963a42037f2f886545e30c
  Author: Babu Moger <address@hidden>
  Date:   2018-05-15 (Tue, 15 May 2018)

  Changed paths:
    M target/i386/cpu.c

  Log Message:
  -----------
  i386: Initialize cache information for EPYC family processors

Initialize pre-determined cache information for EPYC processors.

Signed-off-by: Babu Moger <address@hidden>
Tested-by: Geoffrey McRae <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 968ee4ad25934717b9192dfed6650a6282854e17
      
https://github.com/qemu/qemu/commit/968ee4ad25934717b9192dfed6650a6282854e17
  Author: Babu Moger <address@hidden>
  Date:   2018-05-15 (Tue, 15 May 2018)

  Changed paths:
    M hw/i386/pc_piix.c
    M hw/i386/pc_q35.c
    M include/hw/i386/pc.h

  Log Message:
  -----------
  pc: add 2.13 machine types

Add pc-q35-2.13 and pc-i440fx-2.13 machine types

Signed-off-by: Babu Moger <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: ab8f992e3e63e91be257e4e343d386dae7be4bcb
      
https://github.com/qemu/qemu/commit/ab8f992e3e63e91be257e4e343d386dae7be4bcb
  Author: Babu Moger <address@hidden>
  Date:   2018-05-15 (Tue, 15 May 2018)

  Changed paths:
    M include/hw/i386/pc.h
    M target/i386/cpu.c
    M target/i386/cpu.h

  Log Message:
  -----------
  i386: Add new property to control cache info

The property legacy-cache will be used to control the cache information.
If user passes "-cpu legacy-cache" then older information will
be displayed even if the hardware supports new information. Otherwise
use the statically loaded cache definitions if available.

Renamed the previous cache structures to legacy_*. If there is any change in
the cache information, then it needs to be initialized in builtin_x86_defs.

Signed-off-by: Babu Moger <address@hidden>
Tested-by: Geoffrey McRae <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>


  Commit: 61126a8b4bea43212b575169d4140dc403fc7e90
      
https://github.com/qemu/qemu/commit/61126a8b4bea43212b575169d4140dc403fc7e90
  Author: Peter Maydell <address@hidden>
  Date:   2018-05-17 (Thu, 17 May 2018)

  Changed paths:
    M hw/i386/pc_piix.c
    M hw/i386/pc_q35.c
    M include/hw/i386/pc.h
    M target/i386/cpu.c
    M target/i386/cpu.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' 
into staging

x86 queue, 2018-05-15

* KnightsMill CPU model
* CLDEMOTE(Demote Cache Line) cpu feature
* pc-i440fx-2.13 and pc-q35-2.13 machine-types
* Add model-specific cache information to EPYC CPU model

# gpg: Signature made Tue 15 May 2018 22:53:12 BST
# gpg:                using RSA key 2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <address@hidden>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-next-pull-request:
  i386: Add new property to control cache info
  pc: add 2.13 machine types
  i386: Initialize cache information for EPYC family processors
  i386: Add cache information in X86CPUDefinition
  i386: Helpers to encode cache information consistently
  x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu feature
  i386: add KnightsMill cpu model

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/c416eecea5f3...61126a8b4bea
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