[Qemu-commits] [qemu/qemu] 17b975: riscv: spike: allow base == 0

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 17b9751e85b9989cc841ed387794d7f1e8aa5e46
      
https://github.com/qemu/qemu/commit/17b9751e85b9989cc841ed387794d7f1e8aa5e46
  Author: KONRAD Frederic <address@hidden>
  Date:   2018-05-09 (Wed, 09 May 2018)

  Changed paths:
    M hw/riscv/riscv_htif.c

  Log Message:
  -----------
  riscv: spike: allow base == 0

The sanity check on base doesn't allow htif to be mapped @0. Check if the
symbol exists instead so we can map it where we want.

Reviewed-by: Michael Clark <address@hidden>
Signed-off-by: KONRAD Frederic <address@hidden>
Signed-off-by: Michael Clark <address@hidden>

Message-Id: <address@hidden>


  Commit: 6fad7d1893f6ea926063067af957009bc320406f
      
https://github.com/qemu/qemu/commit/6fad7d1893f6ea926063067af957009bc320406f
  Author: KONRAD Frederic <address@hidden>
  Date:   2018-05-09 (Wed, 09 May 2018)

  Changed paths:
    M hw/riscv/riscv_htif.c

  Log Message:
  -----------
  riscv: htif: increase the priority of the htif subregion

The htif device is supposed to be mapped over an other subregion. So increase
its priority to one to avoid any conflict.

Here is the output of info mtree:

Before:
(qemu) info mtree
 address-space: memory
   0000000000000000-ffffffffffffffff (prio 0, i/o): system
     0000000000000000-000000000000000f (prio 0, i/o): riscv.htif.uart
     0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
     0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
     0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram

 address-space: I/O
   0000000000000000-000000000000ffff (prio 0, i/o): io

 address-space: cpu-memory-0
   0000000000000000-ffffffffffffffff (prio 0, i/o): system
     0000000000000000-000000000000000f (prio 0, i/o): riscv.htif.uart
     0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
     0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
     0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram

After:
 (qemu) info mtree
 address-space: memory
   0000000000000000-ffffffffffffffff (prio 0, i/o): system
     0000000000000000-000000000000000f (prio 1, i/o): riscv.htif.uart
     0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
     0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
     0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram

 address-space: I/O
   0000000000000000-000000000000ffff (prio 0, i/o): io

 address-space: cpu-memory-0
   0000000000000000-ffffffffffffffff (prio 0, i/o): system
     0000000000000000-000000000000000f (prio 1, i/o): riscv.htif.uart
     0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom
     0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint
     0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram

Reviewed-by: Michael Clark <address@hidden>
Signed-off-by: KONRAD Frederic <address@hidden>
Signed-off-by: Michael Clark <address@hidden>

Message-Id: <address@hidden>


  Commit: a666409f0df5dce113a5bd2c4c144a0792f2a4a3
      
https://github.com/qemu/qemu/commit/a666409f0df5dce113a5bd2c4c144a0792f2a4a3
  Author: KONRAD Frederic <address@hidden>
  Date:   2018-05-09 (Wed, 09 May 2018)

  Changed paths:
    M configure

  Log Message:
  -----------
  riscv: requires libfdt

When compiling on a machine without libfdt installed the configure script
should try to get libfdt from the git or should die because otherwise
CONFIG_LIBFDT is not set and the build process end in an error in the link
phase.. eg:

hw/riscv/virt.o: In function `riscv_virt_board_init':
qemu/src/hw/riscv/virt.c:317: undefined reference to `qemu_fdt_setprop_cell'
qemu/src/hw/riscv/virt.c:319: undefined reference to `qemu_fdt_setprop_cell'
qemu/src/hw/riscv/virt.c:345: undefined reference to `qemu_fdt_dumpdtb'
collect2: error: ld returned 1 exit status
make[1]: *** [qemu-system-riscv64] Error 1
make: *** [subdir-riscv64-softmmu] Error 2

Cc: address@hidden
Reviewed-by: Bastian Koppelmann <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Michael Clark <address@hidden>
Signed-off-by: KONRAD Frederic <address@hidden>
Signed-off-by: Michael Clark <address@hidden>

Message-Id: <address@hidden>


  Commit: a8a94ef72678c56768c1c74dcaf6ee3c92f2af1c
      
https://github.com/qemu/qemu/commit/a8a94ef72678c56768c1c74dcaf6ee3c92f2af1c
  Author: Peter Maydell <address@hidden>
  Date:   2018-05-10 (Thu, 10 May 2018)

  Changed paths:
    M configure
    M hw/riscv/riscv_htif.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/riscv/tags/riscv-qemu-2.13-minor-fixes-3' into staging

RISC-V: QEMU 2.13 Minor Fixes

* Require libfdt when configuring for 'riscv*-softmmu'
* Increase HTIF priority and allow zero base address

# gpg: Signature made Wed 09 May 2018 11:15:33 BST
# gpg:                using DSA key 6BF1D7B357EF3E4F
# gpg: Good signature from "Michael Clark <address@hidden>"
# gpg:                 aka "Michael Clark <address@hidden>"
# gpg:                 aka "Michael Clark <address@hidden>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7C99 930E B17C D8BA 073D  5EFA 6BF1 D7B3 57EF 3E4F

* remotes/riscv/tags/riscv-qemu-2.13-minor-fixes-3:
  riscv: requires libfdt
  riscv: htif: increase the priority of the htif subregion
  riscv: spike: allow base == 0

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/e5cd695266c5...a8a94ef72678
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