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[Qemu-commits] [qemu/qemu] 2a8756: RISC-V: Replace hardcoded constants w


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 2a8756: RISC-V: Replace hardcoded constants with enum valu...
Date: Tue, 08 May 2018 06:22:14 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 2a8756ed7d64f8fed6ad50fb062f7118e47c856c
      
https://github.com/qemu/qemu/commit/2a8756ed7d64f8fed6ad50fb062f7118e47c856c
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M hw/riscv/sifive_clint.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/sifive_clint.h
    M include/hw/riscv/sifive_u.h
    M include/hw/riscv/spike.h
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  RISC-V: Replace hardcoded constants with enum values

The RISC-V device-tree code has a number of hard-coded
constants and this change moves them into header enums.

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>


  Commit: 77ff5bba315d4453ae97ff90ba7698fb1ccc077c
      
https://github.com/qemu/qemu/commit/77ff5bba315d4453ae97ff90ba7698fb1ccc077c
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M hw/riscv/virt.c

  Log Message:
  -----------
  RISC-V: Make virt board description match spike

This makes 'qemu-system-riscv64 -machine help' output more tidy
and consistent.

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>


  Commit: 6b01e3277e0e189a8f064b94c4f761e4efadd758
      
https://github.com/qemu/qemu/commit/6b01e3277e0e189a8f064b94c4f761e4efadd758
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M hw/riscv/virt.c
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  RISC-V: Use ROM base address and size from memmap

Another case of replacing hard coded constants, this time
referring to the definition in the virt machine's memmap.

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>


  Commit: b7938980fbd3209fd94b17c98c54ec044b762417
      
https://github.com/qemu/qemu/commit/b7938980fbd3209fd94b17c98c54ec044b762417
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c

  Log Message:
  -----------
  RISC-V: Remove identity_translate from load_elf

When load_elf is called with NULL as an argument to the
address translate callback, it does an identity translation.
This commit removes the redundant identity_translate callback.

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>


  Commit: 42b3a4b7ccbbf419df926939b273fe3b8a6dca1f
      
https://github.com/qemu/qemu/commit/42b3a4b7ccbbf419df926939b273fe3b8a6dca1f
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M hw/riscv/riscv_hart.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/sifive_e.h
    M include/hw/riscv/sifive_u.h
    M include/hw/riscv/spike.h
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  RISC-V: Remove unused class definitions

Removes a whole lot of unnecessary boilerplate code. Machines
don't need to be objects. The expansion of the SOC object model
for the RISC-V machines will happen in the future as SiFive
plans to add their FE310 and FU540 SOCs to QEMU. However, it
seems that this present boilerplate is complete unnecessary.

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>


  Commit: 6296a799b14142ccb813b678227ae9e6bf0ffa79
      
https://github.com/qemu/qemu/commit/6296a799b14142ccb813b678227ae9e6bf0ffa79
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M disas/riscv.c

  Log Message:
  -----------
  RISC-V: Include instruction hex in disassembly

This was added to help debug issues using -d in_asm. It is
useful to see the instruction bytes, as one can detect if
one is trying to execute ASCII or device-tree magic.

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>


  Commit: 1dc34be1c90b2d3006078d9d331e53a849cdecf3
      
https://github.com/qemu/qemu/commit/1dc34be1c90b2d3006078d9d331e53a849cdecf3
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M disas/riscv.c

  Log Message:
  -----------
  RISC-V: Fix missing break statement in disassembler

This fixes an issue when disassembling rv128 c.sqsp,
where the code erroneously fell through to c.swsp.

Cc: Palmer Dabbelt <address@hidden>
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Alistair Francis <address@hidden>
Cc: Peter Maydell <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 4996b128745d93d859b434ff365d4e418bd9095d
      
https://github.com/qemu/qemu/commit/4996b128745d93d859b434ff365d4e418bd9095d
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M include/hw/riscv/spike.h
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  RISC-V: Make some header guards more specific

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>


  Commit: 5b5583806b16ca9ddc454e2a5892b1fea575e470
      
https://github.com/qemu/qemu/commit/5b5583806b16ca9ddc454e2a5892b1fea575e470
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M include/hw/riscv/virt.h

  Log Message:
  -----------
  RISC-V: Make virt header comment title consistent

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>


  Commit: 89854803ce3efb16fbc94604e652f152f5102569
      
https://github.com/qemu/qemu/commit/89854803ce3efb16fbc94604e652f152f5102569
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  RISC-V: Remove EM_RISCV ELF_MACHINE indirection

Pointless indirection. Other ports use EM_ constants directly.

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>


  Commit: 8d196c43d7e247edbda7be7b1597ea184f6b498e
      
https://github.com/qemu/qemu/commit/8d196c43d7e247edbda7be7b1597ea184f6b498e
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M target/riscv/translate.c

  Log Message:
  -----------
  RISC-V: Remove erroneous comment from translate.c

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>


  Commit: 79f86934267135080e13e02b52c74371220d8e06
      
https://github.com/qemu/qemu/commit/79f86934267135080e13e02b52c74371220d8e06
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/cpu.h

  Log Message:
  -----------
  RISC-V: Update E and I extension order

Section 22.8 Subset Naming Convention of the RISC-V ISA Specification
defines the canonical order for extensions in the ISA string. It is
silent on the position of the E extension however E is a substitute
for I so it must come early in the extension list order. A comment
is added to state E and I are mutually exclusive, as the E extension
will be added to the RISC-V port in the future.

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>


  Commit: 33e3bc8d77b6ce95e622bdc0fce622d35b7ee56c
      
https://github.com/qemu/qemu/commit/33e3bc8d77b6ce95e622bdc0fce622d35b7ee56c
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M target/riscv/op_helper.c

  Log Message:
  -----------
  RISC-V: Hardwire satp to 0 for no-mmu case

satp is WARL so it should not trap on illegal writes, rather
it can be hardwired to zero and silently ignore illegal writes.

It seems the RISC-V WARL behaviour is preferred to having to
trap overhead versus simply reading back the value and checking
if the write took (saves hundreds of cycles and more complex
trap handling code).

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>


  Commit: 67185dad16284467dba9b6159f9ec9ec53689582
      
https://github.com/qemu/qemu/commit/67185dad16284467dba9b6159f9ec9ec53689582
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M target/riscv/helper.c

  Log Message:
  -----------
  RISC-V: Clear mtval/stval on exceptions without info

mtval/stval must be set on all exceptions but zero is
a legal value if there is no exception specific info.
Placing the instruction bytes for illegal instruction
exceptions in mtval/stval is an optional feature and
is currently not supported by QEMU RISC-V.

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>


  Commit: e21659057066f2f4d42fa51a62ff07a23a632e40
      
https://github.com/qemu/qemu/commit/e21659057066f2f4d42fa51a62ff07a23a632e40
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M target/riscv/op_helper.c

  Log Message:
  -----------
  RISC-V: Allow S-mode mxr access when priv ISA >= v1.10

The mstatus.MXR alias in sstatus should only be writable
by S-mode if the privileged ISA version >= v1.10. Also MXR
was masked in sstatus CSR read but not sstatus CSR writes.
Now we correctly mask sstatus.mxr in both read and write.

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>


  Commit: 8c59f5c1b5aabbad92871bf62bb302fef017e322
      
https://github.com/qemu/qemu/commit/8c59f5c1b5aabbad92871bf62bb302fef017e322
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M target/riscv/cpu.h
    M target/riscv/op_helper.c

  Log Message:
  -----------
  RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10

Privileged ISA v1.9.1 defines mscounteren and mucounteren:

* mscounteren contains a mask of counters available to S-mode
* mucounteren contains a mask of counters available to U-mode

Privileged ISA v1.10 defines mcounteren and scounteren:

* mcounteren contains a mask of counters available to S-mode
* scounteren contains a mask of counters available to U-mode

mcounteren and scounteren CSR registers were implemented
however they were not honoured for counter accesses when
the privilege ISA was >= v1.10. This fix solves the issue
by coalescing the counter enable registers. In addition
the code now  generates illegal instruction exceptions
for accesses to the counter enabled registers depending
on the privileged ISA version.

- Coalesce mscounteren and mcounteren into one variable
- Coalesce mucounteren and scounteren into one variable
- Makes mcounteren and scounteren CSR accesses generate
  illegal instructions when the privileged ISA <= v1.9.1
- Makes mscounteren and mucounteren CSR accesses generate
  illegal instructions when the privileged ISA >= v1.10

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: 6fce529c4b3ecbff17bbd930f6beaac9a6067114
      
https://github.com/qemu/qemu/commit/6fce529c4b3ecbff17bbd930f6beaac9a6067114
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M target/riscv/op_helper.c
    M target/riscv/translate.c

  Log Message:
  -----------
  RISC-V: Add mcycle/minstret support for -icount auto

Previously the mycycle/minstret CSRs and rdcycle/rdinstret
psuedo instructions would return the time as a proxy for an
increasing instruction counter in the absence of having a
precise instruction count. If QEMU is invoked with -icount,
the mcycle/minstret CSRs and rdcycle/rdinstret psuedo
instructions will return the instruction count.

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>


  Commit: 1d1ee55274860bfcc511d50d83c84394c2685ba8
      
https://github.com/qemu/qemu/commit/1d1ee55274860bfcc511d50d83c84394c2685ba8
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M target/riscv/op_helper.c

  Log Message:
  -----------
  RISC-V: Make mtvec/stvec ignore vectored traps

Vectored traps for asynchrounous interrupts are optional.
The mtvec/stvec mode field is WARL and hence does not trap
if an illegal value is written. Illegal values are ignored.

Later we can add RISCV_FEATURE_VECTORED_TRAPS however
until then the correct behavior for WARL (Write Any, Read
Legal) fields is to drop writes to unsupported bits.

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: b8643bd6084be1787a6dc8768a7a1983921fc945
      
https://github.com/qemu/qemu/commit/b8643bd6084be1787a6dc8768a7a1983921fc945
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M target/riscv/op_helper.c

  Log Message:
  -----------
  RISC-V: No traps on writes to misa,minstret,mcycle

These fields are marked WARL (Write Any Values, Reads
Legal Values) in the RISC-V Privileged Architecture
Specification so instead of raising exceptions,
illegal writes are silently dropped.

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: 5aec3247c190f10654250203a1742490ae7343a2
      
https://github.com/qemu/qemu/commit/5aec3247c190f10654250203a1742490ae7343a2
  Author: Michael Clark <address@hidden>
  Date:   2018-05-06 (Sun, 06 May 2018)

  Changed paths:
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c

  Log Message:
  -----------
  RISC-V: Mark ROM read-only after copying in code

The sifive_u machine already marks its ROM readonly however
it has the wrong base address for its mask ROM. This patch
fixes the sifive_u mask ROM base address.

This commit makes all other boards consistently use mask_rom
as the variable name for their ROMs. Boards that use device
tree now check that that the device tree fits in the assigned
ROM space using the new qemu_fdt_totalsize(void *fdt)
interface, adding a bounds check and error message. This
can detect truncation.

Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>


  Commit: 3add3f7edccf1526b0a562a294c2749fd7385c15
      
https://github.com/qemu/qemu/commit/3add3f7edccf1526b0a562a294c2749fd7385c15
  Author: Peter Maydell <address@hidden>
  Date:   2018-05-08 (Tue, 08 May 2018)

  Changed paths:
    M disas/riscv.c
    M hw/riscv/riscv_hart.c
    M hw/riscv/sifive_clint.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/sifive_clint.h
    M include/hw/riscv/sifive_e.h
    M include/hw/riscv/sifive_u.h
    M include/hw/riscv/spike.h
    M include/hw/riscv/virt.h
    M target/riscv/cpu.c
    M target/riscv/cpu.h
    M target/riscv/helper.c
    M target/riscv/op_helper.c
    M target/riscv/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/riscv/tags/riscv-qemu-2.13-pull-20180506' into staging

RISC-V: QEMU 2.13 Privileged ISA emulation updates

Several code cleanups, minor specification conformance changes,
fixes to make ROM read-only and add device-tree size checks.

* Honour privileged ISA v1.10 counter enable CSRs.
* Implements WARL behavior for CSRs that don't support writes
  * Past behavior of raising traps was non-conformant
    with the RISC-V Privileged ISA Specification v1.10.
* Allow S-mode access to sstatus.MXR when priv ISA >= v1.10
* Sets mtval/stval to zero on exceptions without addresses
  * Past behavior of leaving the last value was non-conformant
    with the RISC-V Privileged ISA Specition v1.10. mtval/stval
    must be set on all exceptions; to zero if not supported.
* Make ROMs read-only and implement device-tree size checks
  * Uses memory_region_init_rom and rom_add_blob_fixed_as
* Adds hexidecimal instruction bytes to disassembly output.
* Fixes missing break statement for rv128 disassembly.
* Several code cleanups
  * Replacing hard-coded constants with enums
  * Dead-code elimination

This is an incremental pull that contains 20 reviewed changes out
of 38 changes currently queued in the qemu-2.13-for-upstream branch.

# gpg: Signature made Sun 06 May 2018 00:27:37 BST
# gpg:                using DSA key 6BF1D7B357EF3E4F
# gpg: Good signature from "Michael Clark <address@hidden>"
# gpg:                 aka "Michael Clark <address@hidden>"
# gpg:                 aka "Michael Clark <address@hidden>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7C99 930E B17C D8BA 073D  5EFA 6BF1 D7B3 57EF 3E4F

* remotes/riscv/tags/riscv-qemu-2.13-pull-20180506:
  RISC-V: Mark ROM read-only after copying in code
  RISC-V: No traps on writes to misa,minstret,mcycle
  RISC-V: Make mtvec/stvec ignore vectored traps
  RISC-V: Add mcycle/minstret support for -icount auto
  RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10
  RISC-V: Allow S-mode mxr access when priv ISA >= v1.10
  RISC-V: Clear mtval/stval on exceptions without info
  RISC-V: Hardwire satp to 0 for no-mmu case
  RISC-V: Update E and I extension order
  RISC-V: Remove erroneous comment from translate.c
  RISC-V: Remove EM_RISCV ELF_MACHINE indirection
  RISC-V: Make virt header comment title consistent
  RISC-V: Make some header guards more specific
  RISC-V: Fix missing break statement in disassembler
  RISC-V: Include instruction hex in disassembly
  RISC-V: Remove unused class definitions
  RISC-V: Remove identity_translate from load_elf
  RISC-V: Use ROM base address and size from memmap
  RISC-V: Make virt board description match spike
  RISC-V: Replace hardcoded constants with enum values

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/302a84e878e8...3add3f7edccf
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