[Qemu-commits] [qemu/qemu] 6d9c1b: hw/arm/virt: Add linux, pci-domain property

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 6d9c1b8dbb3527258bbc473aa3a9b02c6a86c506
      
https://github.com/qemu/qemu/commit/6d9c1b8dbb3527258bbc473aa3a9b02c6a86c506
  Author: Jan Kiszka <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Add linux,pci-domain property

This allows to pin the host controller in the Linux PCI domain space.
Linux requires that property to be available consistently or not at all,
in which case the domain number becomes unstable on additions/removals.
Adding it here won't make a difference in practice for most setups as we
only expose one controller.

However, enabling Jailhouse on top may introduce another controller, and
that one would like to have stable address as well. So the property is
needed for the first controller as well.

Signed-off-by: Jan Kiszka <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 100061121c1f69a672ce7bb3e9e3781f8018f9f6
      
https://github.com/qemu/qemu/commit/100061121c1f69a672ce7bb3e9e3781f8018f9f6
  Author: Mathew Maidment <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Correct MPUIR privilege level in register_cp_regs_for_features() 
conditional case

The duplication of id_tlbtr_reginfo was unintentionally added within
3281af8114c6b8ead02f08b58e3c36895c1ea047 which should have been
id_mpuir_reginfo.

The effect was that for OMAP and StrongARM CPUs we would
incorrectly UNDEF writes to MPUIR rather than NOPing them.

Signed-off-by: Mathew Maidment <address@hidden>
Message-id: address@hidden
[PMM: tweak commit message]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0c6a108ec1efd8498b281086d44604204196a9d5
      
https://github.com/qemu/qemu/commit/0c6a108ec1efd8498b281086d44604204196a9d5
  Author: Patrick Oppenlander <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M hw/char/cmsdk-apb-uart.c

  Log Message:
  -----------
  hw/char/cmsdk-apb-uart.c: Accept more input after character read

The character frontend needs to be notified that the uart receive buffer
is empty and ready to handle another character.

Previously, the uart only worked correctly when receiving one character
at a time.

Signed-off-by: Patrick Oppenlander <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a22cadbefd2b2ff57f5c06688f7ed06c52d6929a
      
https://github.com/qemu/qemu/commit/a22cadbefd2b2ff57f5c06688f7ed06c52d6929a
  Author: Peter Maydell <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M hw/usb/tusb6010.c

  Log Message:
  -----------
  hw/usb/tusb6010: Convert away from old_mmio

Convert the tusb6010 device away from using the old_mmio field
of MemoryRegionOps. This device is used only in the n800 and n810
boards.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 50a22d0de84955692a5f31134d88c1e8fea80247
      
https://github.com/qemu/qemu/commit/50a22d0de84955692a5f31134d88c1e8fea80247
  Author: Peter Maydell <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M hw/net/smc91c111.c

  Log Message:
  -----------
  hw/net/smc91c111: Convert away from old_mmio

Convert the smc91c111 device away from using the old_mmio field of
MemoryRegionOps. This device is used by several Arm board models.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 0c9492765a56c1547dc7edf56971c97685354fe4
      
https://github.com/qemu/qemu/commit/0c9492765a56c1547dc7edf56971c97685354fe4
  Author: Igor Mammedov <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M hw/arm/boot.c

  Log Message:
  -----------
  arm: boot: set boot_info starting from first_cpu

Even though nothing is currently broken (since all boards
use first_cpu as boot cpu), make sure that boot_info is set
on all CPUs.
If some board would like support heterogenuos setup (i.e.
init boot_info on subset of CPUs) in future, it should add
a reasonable API to do it, instead of starting assigning
boot_info from some CPU and till the end of present CPUs
list.

Ref:
"Message-ID: <address@hidden>"

Signed-off-by: Igor Mammedov <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 8dae46970532afcf93470b00e83ca9921980efc3
      
https://github.com/qemu/qemu/commit/8dae46970532afcf93470b00e83ca9921980efc3
  Author: Richard Henderson <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Tidy conditions in handle_vec_simd_shri

The (size > 3 && !is_q) condition is identical to the preceeding test
of bit 3 in immh; eliminate it.  For the benefit of Coverity, assert
that size is within the bounds we expect.

Fixes: Coverity CID1385846
Fixes: Coverity CID1385849
Fixes: Coverity CID1385852
Fixes: Coverity CID1385857
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a8766e3172c1671cab297c1ef4566a3c5d094822
      
https://github.com/qemu/qemu/commit/a8766e3172c1671cab297c1ef4566a3c5d094822
  Author: Richard Henderson <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Tidy condition in disas_simd_two_reg_misc

Path analysis shows that size == 3 && !is_q has been eliminated.

Fixes: Coverity CID1385853
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a82929a251481af1467569810ec309b57558f7fe
      
https://github.com/qemu/qemu/commit/a82929a251481af1467569810ec309b57558f7fe
  Author: Thomas Huth <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M hw/arm/omap1.c
    M hw/arm/omap2.c
    M hw/arm/pxa2xx.c

  Log Message:
  -----------
  hw/arm: Don't fail qtest due to missing SD card in -nodefaults mode

When running omap1/2 or pxa2xx based ARM machines with -nodefaults,
they bail out immediately complaining about a "missing SecureDigital
device". That's not how the "default" devices in vl.c are meant to
work - it should be possible for a board to also start up without
default devices. So let's turn the error message and exit() into
a warning instead.

Signed-off-by: Thomas Huth <address@hidden>
Message-id: address@hidden
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b1e5336a9899016c53d59eba53ebf6abcc21995c
      
https://github.com/qemu/qemu/commit/b1e5336a9899016c53d59eba53ebf6abcc21995c
  Author: Peter Maydell <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Implement v8M VLLDM and VLSTM

For v8M the instructions VLLDM and VLSTM support lazy saving
and restoring of the secure floating-point registers. Even
if the floating point extension is not implemented, these
instructions must act as NOPs in Secure state, so they can
be used as part of the secure-to-nonsecure call sequence.

Fixes: https://bugs.launchpad.net/qemu/+bug/1768295
Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 527773eeef9f2225370f9c17c35074b2ed0ced92
      
https://github.com/qemu/qemu/commit/527773eeef9f2225370f9c17c35074b2ed0ced92
  Author: Eric Auger <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M default-configs/aarch64-softmmu.mak
    M hw/arm/Makefile.objs
    A hw/arm/smmu-common.c
    A include/hw/arm/smmu-common.h

  Log Message:
  -----------
  hw/arm/smmu-common: smmu base device and datatypes

The patch introduces the smmu base device and class for the ARM
smmu. Devices for specific versions will be derived from this
base device.

We also introduce some important datatypes.

Signed-off-by: Eric Auger <address@hidden>
Signed-off-by: Prem Mallappa <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: cac994ef43b128c80c56b4cd4dd9d8af0f95da3f
      
https://github.com/qemu/qemu/commit/cac994ef43b128c80c56b4cd4dd9d8af0f95da3f
  Author: Eric Auger <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M hw/arm/smmu-common.c
    M hw/arm/trace-events
    M include/hw/arm/smmu-common.h

  Log Message:
  -----------
  hw/arm/smmu-common: IOMMU memory region and address space setup

We set up the infrastructure to enumerate all the PCI devices
attached to the SMMU and create an associated IOMMU memory
region and address space.

Those info are stored in SMMUDevice objects. The devices are
grouped according to the PCIBus they belong to. A hash table
indexed by the PCIBus pointer is used. Also an array indexed by
the bus number allows to find the list of SMMUDevices.

Signed-off-by: Eric Auger <address@hidden>
Signed-off-by: Prem Mallappa <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 93641948d4c85f261be1f25a0bdc2ded3476e7d9
      
https://github.com/qemu/qemu/commit/93641948d4c85f261be1f25a0bdc2ded3476e7d9
  Author: Eric Auger <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M hw/arm/smmu-common.c
    A hw/arm/smmu-internal.h
    M hw/arm/trace-events
    M include/hw/arm/smmu-common.h

  Log Message:
  -----------
  hw/arm/smmu-common: VMSAv8-64 page table walk

This patch implements the page table walk for VMSAv8-64.

Signed-off-by: Eric Auger <address@hidden>
Signed-off-by: Prem Mallappa <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 10a83cb9887eddb1b504ecf3b189159db949178e
      
https://github.com/qemu/qemu/commit/10a83cb9887eddb1b504ecf3b189159db949178e
  Author: Prem Mallappa <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M hw/arm/Makefile.objs
    A hw/arm/smmuv3-internal.h
    A hw/arm/smmuv3.c
    M hw/arm/trace-events
    A include/hw/arm/smmuv3.h

  Log Message:
  -----------
  hw/arm/smmuv3: Skeleton

This patch implements a skeleton for the smmuv3 device.
Datatypes and register definitions are introduced. The MMIO
region, the interrupts and the queue are initialized.

Only the MMIO read operation is implemented here.

Signed-off-by: Prem Mallappa <address@hidden>
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 6a736033d343e0e5774849fa0eef88f2582c364a
      
https://github.com/qemu/qemu/commit/6a736033d343e0e5774849fa0eef88f2582c364a
  Author: Eric Auger <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M hw/arm/smmuv3-internal.h
    M hw/arm/smmuv3.c
    M hw/arm/trace-events

  Log Message:
  -----------
  hw/arm/smmuv3: Wired IRQ and GERROR helpers

We introduce some helpers to handle wired IRQs and especially
GERROR interrupt. SMMU writes GERROR register on GERROR event
and SW acks GERROR interrupts by setting GERRORn.

The Wired interrupts are edge sensitive hence the pulse usage.

Signed-off-by: Eric Auger <address@hidden>
Signed-off-by: Prem Mallappa <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: dadd1a0809b1aff8c4d5364f3714b3e0e039dcb0
      
https://github.com/qemu/qemu/commit/dadd1a0809b1aff8c4d5364f3714b3e0e039dcb0
  Author: Eric Auger <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M hw/arm/smmuv3-internal.h
    M hw/arm/smmuv3.c
    M hw/arm/trace-events

  Log Message:
  -----------
  hw/arm/smmuv3: Queue helpers

We introduce helpers to read/write into the command and event
circular queues.

smmuv3_write_eventq and smmuv3_cmq_consume will become static
in subsequent patches.

Invalidation commands are not yet dealt with. We do not cache
data that need to be invalidated. This will change with vhost
integration.

Signed-off-by: Eric Auger <address@hidden>
Signed-off-by: Prem Mallappa <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fae4be38b35dcfae48494c023454e8988c15b69a
      
https://github.com/qemu/qemu/commit/fae4be38b35dcfae48494c023454e8988c15b69a
  Author: Eric Auger <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M hw/arm/smmuv3-internal.h
    M hw/arm/smmuv3.c
    M hw/arm/trace-events

  Log Message:
  -----------
  hw/arm/smmuv3: Implement MMIO write operations

Now we have relevant helpers for queue and irq
management, let's implement MMIO write operations.

Signed-off-by: Eric Auger <address@hidden>
Signed-off-by: Prem Mallappa <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: bb981004eaf4bab2c8ae4feaaf6ead8be7275044
      
https://github.com/qemu/qemu/commit/bb981004eaf4bab2c8ae4feaaf6ead8be7275044
  Author: Eric Auger <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M hw/arm/smmuv3-internal.h
    M hw/arm/smmuv3.c
    M hw/arm/trace-events

  Log Message:
  -----------
  hw/arm/smmuv3: Event queue recording helper

Let's introduce a helper function aiming at recording an
event in the event queue.

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 9bde7f0674fe0354ab58ccf25fdfd9f2f68f2b5c
      
https://github.com/qemu/qemu/commit/9bde7f0674fe0354ab58ccf25fdfd9f2f68f2b5c
  Author: Eric Auger <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M hw/arm/smmuv3-internal.h
    M hw/arm/smmuv3.c
    M hw/arm/trace-events

  Log Message:
  -----------
  hw/arm/smmuv3: Implement translate callback

This patch implements the IOMMU Memory Region translate()
callback. Most of the code relates to the translation
configuration decoding and check (STE, CD).

Signed-off-by: Eric Auger <address@hidden>
Signed-off-by: Prem Mallappa <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0d1ac82eced6bb641a98cd5d7f3b829635f95fac
      
https://github.com/qemu/qemu/commit/0d1ac82eced6bb641a98cd5d7f3b829635f95fac
  Author: Eric Auger <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M hw/arm/smmuv3.c

  Log Message:
  -----------
  hw/arm/smmuv3: Abort on vfio or vhost case

At the moment, the SMMUv3 does not support notification on
TLB invalidation. So let's log an error as soon as such notifier
gets enabled.

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b05c81d292be96e27bd61ed1f67d313eafbda4d9
      
https://github.com/qemu/qemu/commit/b05c81d292be96e27bd61ed1f67d313eafbda4d9
  Author: Eric Auger <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M target/arm/kvm.c
    M target/arm/trace-events

  Log Message:
  -----------
  target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route

In case the MSI is translated by an IOMMU we need to fixup the
MSI route with the translated address.

Signed-off-by: Eric Auger <address@hidden>
Signed-off-by: Bharat Bhushan <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 584105eab2f49132b00c4d4baa0d94e0a4baed38
      
https://github.com/qemu/qemu/commit/584105eab2f49132b00c4d4baa0d94e0a4baed38
  Author: Prem Mallappa <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M hw/arm/virt.c
    M include/hw/arm/virt.h

  Log Message:
  -----------
  hw/arm/virt: Add SMMUv3 to the virt board

Add code to instantiate an smmuv3 in virt machine. A new iommu
integer member is introduced in VirtMachineState to store the type
of the iommu in use.

Signed-off-by: Prem Mallappa <address@hidden>
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a703b4f6c1ee25090384fe75074f2571d7b69e02
      
https://github.com/qemu/qemu/commit/a703b4f6c1ee25090384fe75074f2571d7b69e02
  Author: Prem Mallappa <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M hw/arm/virt-acpi-build.c
    M include/hw/acpi/acpi-defs.h

  Log Message:
  -----------
  hw/arm/virt-acpi-build: Add smmuv3 node in IORT table

This patch builds the smmuv3 node in the ACPI IORT table.

The RID space of the root complex, which spans 0x0-0x10000
maps to streamid space 0x0-0x10000 in smmuv3, which in turn
maps to deviceid space 0x0-0x10000 in the ITS group.

The guest must feature the IOMMU probe deferral series
(https://lkml.org/lkml/2017/4/10/214) which fixes streamid
multiple lookup. This bug is not related to the SMMU emulation.

Signed-off-by: Prem Mallappa <address@hidden>
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Shannon Zhao <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e24e3454829579eb815ec95d7b3679b0f65845b4
      
https://github.com/qemu/qemu/commit/e24e3454829579eb815ec95d7b3679b0f65845b4
  Author: Eric Auger <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Introduce the iommu option

ARM virt machine now exposes a new "iommu" option.
The SMMUv3 IOMMU is instantiated using -machine virt,iommu=smmuv3.

Signed-off-by: Eric Auger <address@hidden>
Signed-off-by: Prem Mallappa <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 853f8ca13cd6d2566b87ed647f8bb5480cdc5e47
      
https://github.com/qemu/qemu/commit/853f8ca13cd6d2566b87ed647f8bb5480cdc5e47
  Author: Peter Maydell <address@hidden>
  Date:   2018-05-04 (Fri, 04 May 2018)

  Changed paths:
    M default-configs/aarch64-softmmu.mak
    M hw/arm/Makefile.objs
    M hw/arm/boot.c
    M hw/arm/omap1.c
    M hw/arm/omap2.c
    M hw/arm/pxa2xx.c
    A hw/arm/smmu-common.c
    A hw/arm/smmu-internal.h
    A hw/arm/smmuv3-internal.h
    A hw/arm/smmuv3.c
    M hw/arm/trace-events
    M hw/arm/virt-acpi-build.c
    M hw/arm/virt.c
    M hw/char/cmsdk-apb-uart.c
    M hw/net/smc91c111.c
    M hw/usb/tusb6010.c
    M include/hw/acpi/acpi-defs.h
    A include/hw/arm/smmu-common.h
    A include/hw/arm/smmuv3.h
    M include/hw/arm/virt.h
    M target/arm/helper.c
    M target/arm/kvm.c
    M target/arm/trace-events
    M target/arm/translate-a64.c
    M target/arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 
'remotes/pmaydell/tags/pull-target-arm-20180504-1' into staging

target-arm queue:
 * Emulate the SMMUv3 (IOMMU); one will be created in the 'virt' board
   if the commandline includes "-machine iommu=smmuv3"
 * target/arm: Implement v8M VLLDM and VLSTM
 * hw/arm: Don't fail qtest due to missing SD card in -nodefaults mode
 * Some fixes to silence Coverity false-positives
 * arm: boot: set boot_info starting from first_cpu
   (fixes a technical bug not visible in practice)
 * hw/net/smc91c111: Convert away from old_mmio
 * hw/usb/tusb6010: Convert away from old_mmio
 * hw/char/cmsdk-apb-uart.c: Accept more input after character read
 * target/arm: Make MPUIR write-ignored on OMAP, StrongARM
 * hw/arm/virt: Add linux,pci-domain property

# gpg: Signature made Fri 04 May 2018 18:54:49 BST
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180504-1: (24 commits)
  hw/arm/virt: Introduce the iommu option
  hw/arm/virt-acpi-build: Add smmuv3 node in IORT table
  hw/arm/virt: Add SMMUv3 to the virt board
  target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route
  hw/arm/smmuv3: Abort on vfio or vhost case
  hw/arm/smmuv3: Implement translate callback
  hw/arm/smmuv3: Event queue recording helper
  hw/arm/smmuv3: Implement MMIO write operations
  hw/arm/smmuv3: Queue helpers
  hw/arm/smmuv3: Wired IRQ and GERROR helpers
  hw/arm/smmuv3: Skeleton
  hw/arm/smmu-common: VMSAv8-64 page table walk
  hw/arm/smmu-common: IOMMU memory region and address space setup
  hw/arm/smmu-common: smmu base device and datatypes
  target/arm: Implement v8M VLLDM and VLSTM
  hw/arm: Don't fail qtest due to missing SD card in -nodefaults mode
  target/arm: Tidy condition in disas_simd_two_reg_misc
  target/arm: Tidy conditions in handle_vec_simd_shri
  arm: boot: set boot_info starting from first_cpu
  hw/net/smc91c111: Convert away from old_mmio
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/c8b7e627b426...853f8ca13cd6
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