[Qemu-commits] [qemu/qemu] 4dc62b: RISC-V Maintainers

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 4dc62b15323bb6338c4b426f76e92be55f87db8c
      
https://github.com/qemu/qemu/commit/4dc62b15323bb6338c4b426f76e92be55f87db8c
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  RISC-V Maintainers

Add Michael Clark, Palmer Dabbelt, Sagar Karandikar and Bastian
Koppelmann as RISC-V Maintainers.

Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Sagar Karandikar <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: f71a8eaffba3271cf7cdad95572f6996f7523a5b
      
https://github.com/qemu/qemu/commit/f71a8eaffba3271cf7cdad95572f6996f7523a5b
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    M include/elf.h

  Log Message:
  -----------
  RISC-V ELF Machine Definition

Define RISC-V ELF machine EM_RISCV 243

Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Sagar Karandikar <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: dc5bd18fa57254e4b8597747c2100c92a55fc409
      
https://github.com/qemu/qemu/commit/dc5bd18fa57254e4b8597747c2100c92a55fc409
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    A target/riscv/cpu.c
    A target/riscv/cpu.h
    A target/riscv/cpu_bits.h

  Log Message:
  -----------
  RISC-V CPU Core Definition

Add CPU state header, CPU definitions and initialization routines

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Sagar Karandikar <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: ea10325917c8a8f92611025c85950c00f826cb73
      
https://github.com/qemu/qemu/commit/ea10325917c8a8f92611025c85950c00f826cb73
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    M disas.c
    M disas/Makefile.objs
    A disas/riscv.c
    M include/disas/bfd.h

  Log Message:
  -----------
  RISC-V Disassembler

The RISC-V disassembler has no dependencies outside of the 'disas'
directory so it can be applied independently. The majority of the
disassembler is machine-generated from instruction set metadata:

- https://github.com/michaeljclark/riscv-meta

Expected checkpatch errors for consistency and brevity reasons:

ERROR: line over 90 characters
ERROR: trailing statements should be on next line
ERROR: space prohibited between function name and open parenthesis '('

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: 0c3e702aca76ca6ebf2aac4451870efc9d52a7a3
      
https://github.com/qemu/qemu/commit/0c3e702aca76ca6ebf2aac4451870efc9d52a7a3
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    A target/riscv/helper.c
    A target/riscv/helper.h
    A target/riscv/op_helper.c

  Log Message:
  -----------
  RISC-V CPU Helpers

Privileged control and status register helpers and page fault handling.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Sagar Karandikar <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: f798f1e29be6066feafa2a88aa94441695339e0a
      
https://github.com/qemu/qemu/commit/f798f1e29be6066feafa2a88aa94441695339e0a
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    M fpu/softfloat-specialize.h
    A target/riscv/fpu_helper.c

  Log Message:
  -----------
  RISC-V FPU Support

Helper routines for FPU instructions and NaN definitions.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Sagar Karandikar <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: 9438fe7d7c54f6f897d16409d6489ddd4c99bafb
      
https://github.com/qemu/qemu/commit/9438fe7d7c54f6f897d16409d6489ddd4c99bafb
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    A target/riscv/gdbstub.c

  Log Message:
  -----------
  RISC-V GDB Stub

GDB Register read and write routines.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Sagar Karandikar <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: 55c2a12cbcd3d417de39ee82dfe1d26b22a07116
      
https://github.com/qemu/qemu/commit/55c2a12cbcd3d417de39ee82dfe1d26b22a07116
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    A target/riscv/instmap.h
    A target/riscv/translate.c

  Log Message:
  -----------
  RISC-V TCG Code Generation

TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
RISC-V code generator has complete coverage for the Base ISA v2.2,
Privileged ISA v1.9.1 and Privileged ISA v1.10:

- RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
- RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
- RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Sagar Karandikar <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: 65c5b75c38b3e56650fc63674039108697096f75
      
https://github.com/qemu/qemu/commit/65c5b75c38b3e56650fc63674039108697096f75
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    A target/riscv/pmp.c
    A target/riscv/pmp.h

  Log Message:
  -----------
  RISC-V Physical Memory Protection

Implements the physical memory protection extension as specified in
Privileged ISA Version 1.10.

PMP (Physical Memory Protection) is as-of-yet unused and needs testing.
The SiFive verification team have PMP test cases that will be run.

Nothing currently depends on PMP support. It would be preferable to keep
the code in-tree for folk that are interested in RISC-V PMP support.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Daire McNamara <address@hidden>
Signed-off-by: Ivan Griffin <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: 47ae93cdfedc683c56e19113d516d7ce4971c8e6
      
https://github.com/qemu/qemu/commit/47ae93cdfedc683c56e19113d516d7ce4971c8e6
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    M linux-user/elfload.c
    M linux-user/main.c
    A linux-user/riscv/syscall_nr.h
    A linux-user/riscv/target_cpu.h
    A linux-user/riscv/target_elf.h
    A linux-user/riscv/target_signal.h
    A linux-user/riscv/target_structs.h
    A linux-user/riscv/target_syscall.h
    A linux-user/riscv/termbits.h
    M linux-user/signal.c
    M linux-user/syscall.c
    M linux-user/syscall_defs.h
    A target/riscv/cpu_user.h

  Log Message:
  -----------
  RISC-V Linux User Emulation

Implementation of linux user emulation for RISC-V.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Sagar Karandikar <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: a2480ffa88a247acbddcf6bb8c4cf69b1af0f48c
      
https://github.com/qemu/qemu/commit/a2480ffa88a247acbddcf6bb8c4cf69b1af0f48c
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    M hw/core/loader.c
    M include/hw/elf_ops.h
    M include/hw/loader.h

  Log Message:
  -----------
  Add symbol table callback interface to load_elf

The RISC-V HTIF (Host Target Interface) console device requires access
to the symbol table to locate the 'tohost' and 'fromhost' symbols.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: 5033606780b9743921de95adb295bf1a03135d2c
      
https://github.com/qemu/qemu/commit/5033606780b9743921de95adb295bf1a03135d2c
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    A hw/riscv/riscv_htif.c
    A include/hw/riscv/riscv_htif.h

  Log Message:
  -----------
  RISC-V HTIF Console

HTIF (Host Target Interface) provides console emulation for QEMU. HTIF
allows identical copies of BBL (Berkeley Boot Loader) and linux to run
on both Spike and QEMU. BBL provides HTIF console access via the
SBI (Supervisor Binary Interface) and the linux kernel SBI console.

The HTIT chardev implements the pre qom legacy interface consistent
with the 16550a UART in 'hw/char/serial.c'.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Sagar Karandikar <address@hidden>
Signed-off-by: Stefan O'Rear <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: 4b50b8d9f2bdc007d632a6d0781de1126c5d9c76
      
https://github.com/qemu/qemu/commit/4b50b8d9f2bdc007d632a6d0781de1126c5d9c76
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    A hw/riscv/riscv_hart.c
    A include/hw/riscv/riscv_hart.h

  Log Message:
  -----------
  RISC-V HART Array

Holds the state of a heterogenous array of RISC-V hardware threads.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Sagar Karandikar <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: 1c77c410b684e987b8c3cd2e02e0460c7e008778
      
https://github.com/qemu/qemu/commit/1c77c410b684e987b8c3cd2e02e0460c7e008778
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    A hw/riscv/sifive_clint.c
    A include/hw/riscv/sifive_clint.h

  Log Message:
  -----------
  SiFive RISC-V CLINT Block

The CLINT (Core Local Interruptor) device provides real-time clock, timer
and interprocessor interrupts based on SiFive's CLINT specification.

Acked-by: Richard Henderson <address@hidden>
Signed-off-by: Sagar Karandikar <address@hidden>
Signed-off-by: Stefan O'Rear <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: 1e24429e40df81270012538851c75e30c53eec21
      
https://github.com/qemu/qemu/commit/1e24429e40df81270012538851c75e30c53eec21
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    A hw/riscv/sifive_plic.c
    A include/hw/riscv/sifive_plic.h

  Log Message:
  -----------
  SiFive RISC-V PLIC Block

The PLIC (Platform Level Interrupt Controller) device provides a
parameterizable interrupt controller based on SiFive's PLIC specification.

Acked-by: Richard Henderson <address@hidden>
Signed-off-by: Stefan O'Rear <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: 5b4beba1246ff163415bde41cd76935012b16823
      
https://github.com/qemu/qemu/commit/5b4beba1246ff163415bde41cd76935012b16823
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    A hw/riscv/spike.c
    A include/hw/riscv/spike.h

  Log Message:
  -----------
  RISC-V Spike Machines

RISC-V machines compatble with Spike aka riscv-isa-sim, the RISC-V
Instruction Set Simulator. The following machines are implemented:

- 'spike_v1.9.1'; HTIF console, config-string, Privileged ISA Version 1.9.1
- 'spike_v1.10'; HTIF console, device-tree, Privileged ISA Version 1.10

Acked-by: Richard Henderson <address@hidden>
Signed-off-by: Sagar Karandikar <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: 88a07990fa282e4b63845223e90d759ef6811264
      
https://github.com/qemu/qemu/commit/88a07990fa282e4b63845223e90d759ef6811264
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    A hw/riscv/sifive_test.c
    A include/hw/riscv/sifive_test.h

  Log Message:
  -----------
  SiFive RISC-V Test Finisher

Test finisher memory mapped device used to exit simulation.

Acked-by: Richard Henderson <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: 04331d0b56a0cab2e40a39135a92a15266b37c36
      
https://github.com/qemu/qemu/commit/04331d0b56a0cab2e40a39135a92a15266b37c36
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    A hw/riscv/virt.c
    A include/hw/riscv/virt.h

  Log Message:
  -----------
  RISC-V VirtIO Machine

RISC-V machine with device-tree, 16550a UART and VirtIO MMIO.
The following machine is implemented:

- 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree

Acked-by: Richard Henderson <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: bb72692cbdbeeef88f4dd1828c1ad6f92cd57b7e
      
https://github.com/qemu/qemu/commit/bb72692cbdbeeef88f4dd1828c1ad6f92cd57b7e
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    A hw/riscv/sifive_uart.c
    A include/hw/riscv/sifive_uart.h

  Log Message:
  -----------
  SiFive RISC-V UART Device

QEMU model of the UART on the SiFive E300 and U500 series SOCs.
BBL supports the SiFive UART for early console access via the SBI
(Supervisor Binary Interface) and the linux kernel SBI console.

The SiFive UART implements the pre qom legacy interface consistent
with the 16550a UART in 'hw/char/serial.c'.

Acked-by: Richard Henderson <address@hidden>
Signed-off-by: Stefan O'Rear <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: e6b8552c655aad405e7dc28d84b4a6d5324f1b92
      
https://github.com/qemu/qemu/commit/e6b8552c655aad405e7dc28d84b4a6d5324f1b92
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    A hw/riscv/sifive_prci.c
    A include/hw/riscv/sifive_prci.h

  Log Message:
  -----------
  SiFive RISC-V PRCI Block

Simple model of the PRCI  (Power, Reset, Clock, Interrupt) to emulate
register reads made by the SDK BSP.

Acked-by: Richard Henderson <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: eb637edb1241aff1442579475da303ee5b672910
      
https://github.com/qemu/qemu/commit/eb637edb1241aff1442579475da303ee5b672910
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    A hw/riscv/sifive_e.c
    A include/hw/riscv/sifive_e.h

  Log Message:
  -----------
  SiFive Freedom E Series RISC-V Machine

This provides a RISC-V Board compatible with the the SiFive Freedom E SDK.
The following machine is implemented:

- 'sifive_e'; CLINT, PLIC, UART, AON, GPIO, QSPI, PWM

Acked-by: Richard Henderson <address@hidden>
Signed-off-by: Sagar Karandikar <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: a7240d1e4aac4cd4542d68f3cc722939550da6af
      
https://github.com/qemu/qemu/commit/a7240d1e4aac4cd4542d68f3cc722939550da6af
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    A hw/riscv/sifive_u.c
    A include/hw/riscv/sifive_u.h

  Log Message:
  -----------
  SiFive Freedom U Series RISC-V Machine

This provides a RISC-V Board compatible with the the SiFive Freedom U SDK.
The following machine is implemented:

- 'sifive_u'; CLINT, PLIC, UART, device-tree

Acked-by: Richard Henderson <address@hidden>
Signed-off-by: Sagar Karandikar <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: 25fa194b7b11901561532e435beb83d046899f7a
      
https://github.com/qemu/qemu/commit/25fa194b7b11901561532e435beb83d046899f7a
  Author: Michael Clark <address@hidden>
  Date:   2018-03-07 (Wed, 07 Mar 2018)

  Changed paths:
    M arch_init.c
    M configure
    M cpus.c
    A default-configs/riscv32-linux-user.mak
    A default-configs/riscv32-softmmu.mak
    A default-configs/riscv64-linux-user.mak
    A default-configs/riscv64-softmmu.mak
    A hw/riscv/Makefile.objs
    M include/sysemu/arch_init.h
    M qapi/misc.json
    M scripts/qemu-binfmt-conf.sh
    A target/riscv/Makefile.objs

  Log Message:
  -----------
  RISC-V Build Infrastructure

This adds RISC-V into the build system enabling the following targets:

- riscv32-softmmu
- riscv64-softmmu
- riscv32-linux-user
- riscv64-linux-user

This adds defaults configs for RISC-V, enables the build for the RISC-V
CPU core, hardware, and Linux User Emulation. The 'qemu-binfmt-conf.sh'
script is updated to add the RISC-V ELF magic.

Expected checkpatch errors for consistency reasons:

ERROR: line over 90 characters
FILE: scripts/qemu-binfmt-conf.sh

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Sagar Karandikar <address@hidden>
Signed-off-by: Michael Clark <address@hidden>


  Commit: d9bbfea646e86426d549bd612cd9f91e49aa50c2
      
https://github.com/qemu/qemu/commit/d9bbfea646e86426d549bd612cd9f91e49aa50c2
  Author: Peter Maydell <address@hidden>
  Date:   2018-03-09 (Fri, 09 Mar 2018)

  Changed paths:
    M MAINTAINERS
    M arch_init.c
    M configure
    M cpus.c
    A default-configs/riscv32-linux-user.mak
    A default-configs/riscv32-softmmu.mak
    A default-configs/riscv64-linux-user.mak
    A default-configs/riscv64-softmmu.mak
    M disas.c
    M disas/Makefile.objs
    A disas/riscv.c
    M fpu/softfloat-specialize.h
    M hw/core/loader.c
    A hw/riscv/Makefile.objs
    A hw/riscv/riscv_hart.c
    A hw/riscv/riscv_htif.c
    A hw/riscv/sifive_clint.c
    A hw/riscv/sifive_e.c
    A hw/riscv/sifive_plic.c
    A hw/riscv/sifive_prci.c
    A hw/riscv/sifive_test.c
    A hw/riscv/sifive_u.c
    A hw/riscv/sifive_uart.c
    A hw/riscv/spike.c
    A hw/riscv/virt.c
    M include/disas/bfd.h
    M include/elf.h
    M include/hw/elf_ops.h
    M include/hw/loader.h
    A include/hw/riscv/riscv_hart.h
    A include/hw/riscv/riscv_htif.h
    A include/hw/riscv/sifive_clint.h
    A include/hw/riscv/sifive_e.h
    A include/hw/riscv/sifive_plic.h
    A include/hw/riscv/sifive_prci.h
    A include/hw/riscv/sifive_test.h
    A include/hw/riscv/sifive_u.h
    A include/hw/riscv/sifive_uart.h
    A include/hw/riscv/spike.h
    A include/hw/riscv/virt.h
    M include/sysemu/arch_init.h
    M linux-user/elfload.c
    M linux-user/main.c
    A linux-user/riscv/syscall_nr.h
    A linux-user/riscv/target_cpu.h
    A linux-user/riscv/target_elf.h
    A linux-user/riscv/target_signal.h
    A linux-user/riscv/target_structs.h
    A linux-user/riscv/target_syscall.h
    A linux-user/riscv/termbits.h
    M linux-user/signal.c
    M linux-user/syscall.c
    M linux-user/syscall_defs.h
    M qapi/misc.json
    M scripts/qemu-binfmt-conf.sh
    A target/riscv/Makefile.objs
    A target/riscv/cpu.c
    A target/riscv/cpu.h
    A target/riscv/cpu_bits.h
    A target/riscv/cpu_user.h
    A target/riscv/fpu_helper.c
    A target/riscv/gdbstub.c
    A target/riscv/helper.c
    A target/riscv/helper.h
    A target/riscv/instmap.h
    A target/riscv/op_helper.c
    A target/riscv/pmp.c
    A target/riscv/pmp.h
    A target/riscv/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/riscv/tags/riscv-qemu-upstream-v8.2' 
into staging

QEMU RISC-V Emulation Support (RV64GC, RV32GC)

This release renames the SiFive machines to sifive_e and sifive_u
to represent the SiFive Everywhere and SiFive Unleashed platforms.
SiFive has configurable soft-core IP, so it is intended that these
machines will be extended to enable a variety of SiFive IP blocks.
The CPU definition infrastructure has been improved and there are
now vendor CPU modules including the SiFiVe E31, E51, U34 and U54
cores. The emulation accuracy for the E series has been improved
by disabling the MMU for the E series. S mode has been disabled on
cores that only support M mode and U mode. The two Spike machines
that support two privileged ISA versions have been coalesced into
one file. This series has Signed-off-by from the core contributors.

*** Known Issues ***

* Disassembler has some checkpatch warnings for the sake of code brevity
* scripts/qemu-binfmt-conf.sh has checkpatch warnings due to line length
* PMP (Physical Memory Protection) is as-of-yet unused and needs testing

*** Changelog ***

v8.2

* Rebase

v8.1

* Fix missed case of renaming spike_v1.9 to spike_v1.9.1

v8

* Added linux-user/riscv/target_elf.h during rebase
* Make resetvec configurable and clear mpp and mie on reset
* Use SiFive E31, E51, U34 and U54 cores in SiFive machines
* Define SiFive E31, E51, U34 and U54 cores
* Refactor CPU core definition in preparation for vendor cores
* Prevent S or U mode unless S or U extensions are present
* SiFive E Series cores have no MMU
* SiFive E Series cores have U mode
* Make privileged ISA v1.10 implicit in CPU types
* Remove DRAM_BASE and EXT_IO_BASE as they vary by machine
* Correctly handle mtvec and stvec alignment with respect to RVC
* Print more machine mode state in riscv_cpu_dump_state
* Make riscv_isa_string use compact extension order method
* Fix bug introduced in v6 RISCV_CPU_TYPE_NAME macro change
* Parameterize spike v1.9.1 config string
* Coalesce spike_v1.9.1 and spike_v1.10 machines
* Rename sifive_e300 to sifive_e, and sifive_u500 to sifive_u

v7

* Make spike_v1.10 the default machine
* Rename spike_v1.9 to spike_v1.9.1 to match privileged spec version
* Remove empty target/riscv/trace-events file
* Monitor ROM 32-bit reset code needs to be target endian
* Add TARGET_TIOCGPTPEER to linux-user/riscv/termbits.h
* Add -initrd support to the virt board
* Fix naming in spike machine interface header
* Update copyright notice on RISC-V Spike machines
* Update copyright notice on RISC-V HTIF Console device
* Change CPU Core and translator to GPLv2+
* Change RISC-V Disassembler to GPLv2+
* Change SiFive Test Finisher to GPLv2+
* Change SiFive CLINT to GPLv2+
* Change SiFive PRCI to GPLv2+
* Change SiFive PLIC to GPLv2+
* Change RISC-V spike machines to GPLv2+
* Change RISC-V virt machine to GPLv2+
* Change SiFive E300 machine to GPLv2+
* Change SiFive U500 machine to GPLv2+
* Change RISC-V Hart Array to GPLv2+
* Change RISC-V HTIF device to GPLv2+
* Change SiFiveUART device to GPLv2+

v6

* Drop IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax
* Remove some unnecessary commented debug statements
* Change RISCV_CPU_TYPE_NAME to use riscv-cpu suffix
* Define all CPU variants for linux-user
* qemu_log calls require trailing \n
* Replace PLIC printfs with qemu_log
* Tear out unused HTIF code and eliminate shouting debug messages
* Fix illegal instruction when sfence.vma is passed (rs2) arguments
* Make updates to PTE accessed and dirty bits atomic
* Only require atomic PTE updates on MTTCG enabled guests
* Page fault if accessed or dirty bits can't be updated
* Fix get_physical_address PTE reads and writes on riscv32
* Remove erroneous comments from the PLIC
* Default enable MTTCG
* Make WFI less conservative
* Unify local interrupt handling
* Expunge HTIF interrupts
* Always access mstatus.mip under a lock
* Don't implement rdtime/rdtimeh in system mode (bbl emulates them)
* Implement insreth/cycleh for rv32 and always enable user-mode counters
* Add GDB stub support for reading and writing CSRs
* Rename ENABLE_CHARDEV #ifdef from HTIF code
* Replace bad HTIF ELF code with load_elf symbol callback
* Convert chained if else fault handlers to switch statements
* Use RISCV exception codes for linux-user page faults

v5

* Implement NaN-boxing for flw, set high order bits to 1
* Use float_muladd_negate_* flags to floatXX_muladd
* Use IEEE 754-201x minimumNumber/maximumNumber for fmin/fmax
* Fix TARGET_NR_syscalls
* Update linux-user/riscv/syscall_nr.h
* Fix FENCE.I, needs to terminate translation block
* Adjust unusual convention for interruptno >= 0

v4

* Add @riscv: since 2.12 to CpuInfoArch
* Remove misleading little-endian comment from load_kernel
* Rename cpu-model property to cpu-type
* Drop some unnecessary inline function attributes
* Don't allow GDB to set value of x0 register
* Remove unnecessary empty property lists
* Add Test Finisher device to implement poweroff in virt machine
* Implement priv ISA v1.10 trap and sret/mret xPIE/xIE behavior
* Store fflags data in fp_status
* Purge runtime users of helper_raise_exception
* Fix validate_csr
* Tidy gen_jalr
* Tidy immediate shifts
* Add gen_exception_inst_addr_mis
* Add gen_exception_debug
* Add gen_exception_illegal
* Tidy helper_fclass_*
* Split rounding mode setting to a new function
* Enforce MSTATUS_FS via TB flags
* Implement acquire/release barrier semantics
* Use atomic operations as required
* Fix FENCE and FENCE_I
* Remove commented code from spike machines
* PAGE_WRITE permissions can be set on loads if page is already dirty
* The result of format conversion on an NaN must be a quiet NaN
* Add missing process_queued_cpu_work to riscv linux-user
* Remove float(32|64)_classify from cpu.h
* Removed nonsensical unions aliasing the same type
* Use uintN_t instead of uintN_fast_t in fpu_helper.c
* Use macros for FPU exception values in softfloat_flags_to_riscv
* Move code to set round mode into set_fp_round_mode function
* Convert set_fp_exceptions from a macro to an inline function
* Convert round mode helper into an inline function
* Make fpu_helper ieee_rm array static const
* Include cpu_mmu_index in cpu_get_tb_cpu_state flags
* Eliminate MPRV influence on mmu_index
* Remove unrecoverable do_unassigned_access function
* Only update PTE accessed and dirty bits if necessary
* Remove unnecessary tlb_flush in set_mode as mode is in mmu_idx
* Remove buggy support for misa writes. misa writes are optional
  and are not implemented in any known hardware
* Always set PTE read or execute permissions during page walk
* Reorder helper function declarations to match order in helper.c
* Remove redundant variable declaration in get_physical_address
* Remove duplicated code from get_physical_address
* Use mmu_idx instead of mem_idx in riscv_cpu_get_phys_page_debug

v3

* Fix indentation in PMP and HTIF debug macros
* Fix disassembler checkpatch open brace '{' on next line errors
* Fix trailing statements on next line in decode_inst_decompress
* NOTE: the other checkpatch issues have been reviewed previously

v2

* Remove redundant NULL terminators from disassembler register arrays
* Change disassembler register name arrays to const
* Refine disassembler internal function names
* Update dates in disassembler copyright message
* Remove #ifdef CONFIG_USER_ONLY version of cpu_has_work
* Use ULL suffix on 64-bit constants
* Move riscv_cpu_mmu_index from cpu.h to helper.c
* Move riscv_cpu_hw_interrupts_pending from cpu.h to helper.c
* Remove redundant TARGET_HAS_ICE from cpu.h
* Use qemu_irq instead of void* for irq definition in cpu.h
* Remove duplicate typedef from struct CPURISCVState
* Remove redundant g_strdup from cpu_register
* Remove redundant tlb_flush from riscv_cpu_reset
* Remove redundant mode calculation from get_physical_address
* Remove redundant debug mode printf and dcsr comment
* Remove redundant clearing of MSB for bare physical addresses
* Use g_assert_not_reached for invalid mode in get_physical_address
* Use g_assert_not_reached for unreachable checks in get_physical_address
* Use g_assert_not_reached for unreachable type in raise_mmu_exception
* Return exception instead of aborting for misaligned fetches
* Move exception defines from cpu.h to cpu_bits.h
* Remove redundant breakpoint control definitions from cpu_bits.h
* Implement riscv_cpu_unassigned_access exception handling
* Log and raise exceptions for unimplemented CSRs
* Match Spike HTIF exit behavior - don’t print TEST-PASSED
* Make frm,fflags,fcsr writes trap when mstatus.FS is clear
* Use g_assert_not_reached for unreachable invalid mode
* Make hret,uret,dret generate illegal instructions
* Move riscv_cpu_dump_state and int/fpr regnames to cpu.c
* Lift interrupt flag and mask into constants in cpu_bits.h
* Change trap debugging to use qemu_log_mask LOG_TRACE
* Change CSR debugging to use qemu_log_mask LOG_TRACE
* Change PMP debugging to use qemu_log_mask LOG_TRACE
* Remove commented code from pmp.c
* Change CpuInfoRISCV qapi schema docs to Since 2.12
* Change RV feature macro to use target_ulong cast
* Remove riscv_feature and instead use misa extension flags
* Make riscv_flush_icache_syscall a no-op
* Undo checkpatch whitespace fixes in unrelated linux-user code
* Remove redudant constants and tidy up cpu_bits.h
* Make helper_fence_i a no-op
* Move include "exec/cpu-all" to end of cpu.h
* Rename set_privilege to riscv_set_mode
* Move redundant forward declaration for cpu_riscv_translate_address
* Remove TCGV_UNUSED from riscv_translate_init
* Add comment to pmp.c stating the code is untested and currently unused
* Use ctz to simplify decoding of PMP NAPOT address ranges
* Change pmp_is_in_range to use than equal for end addresses
* Fix off by one error in pmp_update_rule
* Rearrange PMP_DEBUG so that formatting is compile-time checked
* Rearrange trap debugging so that formatting is compile-time checked
* Rearrange PLIC debugging so that formatting is compile-time checked
* Use qemu_log/qemu_log_mask for HTIF logging and debugging
* Move exception and interrupt names into cpu.c
* Add Palmer Dabbelt as a RISC-V Maintainer
* Rebase against current qemu master branch

v1

* initial version based on forward port from riscv-qemu repository

*** Background ***

"RISC-V is an open, free ISA enabling a new era of processor innovation
through open standard collaboration. Born in academia and research,
RISC-V ISA delivers a new level of free, extensible software and
hardware freedom on architecture, paving the way for the next 50 years
of computing design and innovation."

The QEMU RISC-V port has been developed and maintained out-of-tree for
several years by Sagar Karandikar and Bastian Koppelmann. The RISC-V
Privileged specification has evolved substantially over this period but
has recently been solidifying. The RISC-V Base ISA has been frozon for
some time and the Privileged ISA, GCC toolchain and Linux ABI are now
quite stable. I have recently joined Sagar and Bastian as a RISC-V QEMU
Maintainer and hope to support upstreaming the port.

There are multiple vendors taping out, preparing to ship, or shipping
silicon that implements the RISC-V Privileged ISA Version 1.10. There
are also several RISC-V Soft-IP cores implementing Privileged ISA
Version 1.10 that run on FPGA such as SiFive's Freedom U500 Platform
and the U54‑MC RISC-V Core IP, among many more implementations from a
variety of vendors. See https://riscv.org/ for more details.

RISC-V support was upstreamed in binutils 2.28 and GCC 7.1 in the first
half of 2016. RISC-V support is now available in LLVM top-of-tree and
the RISC-V Linux port was accepted into Linux 4.15-rc1 late last year
and is available in the Linux 4.15 release. GLIBC 2.27 added support
for the RISC-V ISA running on Linux (requires at least binutils-2.30,
gcc-7.3.0, and linux-4.15). We believe it is timely to submit the
RISC-V QEMU port for upstream review with the goal of incorporating
RISC-V support into the upcoming QEMU 2.12 release.

The RISC-V QEMU port is still under active development, mostly with
respect to device emulation, the addition of Hypervisor support as
specified in the RISC-V Draft Privileged ISA Version 1.11, and Vector
support once the first draft is finalized later this year. We believe
now is the appropriate time for RISC-V QEMU development to be carried
out in the main QEMU repository as the code will benefit from more
rigorous review. The RISC-V QEMU port currently supports all the ISA
extensions that have been finalized and frozen in the Base ISA.

Blog post about recent additions to RISC-V QEMU: https://goo.gl/fJ4zgk

The RISC-V QEMU wiki: https://github.com/riscv/riscv-qemu/wiki

Instructions for building a busybox+dropbear root image, BBL (Berkeley
Boot Loader) and linux kernel image for use with the RISC-V QEMU
'virt' machine: https://github.com/michaeljclark/busybear-linux

*** Overview ***

The RISC-V QEMU port implements the following specifications:

* RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
* RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
* RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10

The RISC-V QEMU port supports the following instruction set extensions:

* RV32GC with Supervisor-mode and User-mode (RV32IMAFDCSU)
* RV64GC with Supervisor-mode and User-mode (RV64IMAFDCSU)

The RISC-V QEMU port adds the following targets to QEMU:

* riscv32-softmmu
* riscv64-softmmu
* riscv32-linux-user
* riscv64-linux-user

The RISC-V QEMU port supports the following hardware:

* HTIF Console (Host Target Interface)
* SiFive CLINT (Core Local Interruptor) for Timer interrupts and IPIs
* SiFive PLIC (Platform Level Interrupt Controller)
* SiFive Test (Test Finisher) for exiting simulation
* SiFive UART, PRCI, AON, PWM, QSPI support is partially implemented
* VirtIO MMIO (GPEX PCI support will be added in a future patch)
* Generic 16550A UART emulation using 'hw/char/serial.c'
* MTTCG and SMP support (PLIC and CLINT) on the 'virt' machine

The RISC-V QEMU full system emulator supports 5 machines:

* 'spike_v1.9.1', CLINT, PLIC, HTIF console, config-string, Priv v1.9.1
* 'spike_v1.10', CLINT, PLIC, HTIF console, device-tree, Priv v1.10
* 'sifive_e', CLINT, PLIC, SiFive UART, HiFive1 compat, Priv v1.10
* 'sifive_u', CLINT, PLIC, SiFive UART, device-tree, Priv v1.10
* 'virt', CLINT, PLIC, 16550A UART, VirtIO, device-tree, Priv v1.10

This is a list of RISC-V QEMU Port Contributors:

* Alex Suykov
* Andreas Schwab
* Antony Pavlov
* Bastian Koppelmann
* Bruce Hoult
* Chih-Min Chao
* Daire McNamara
* Darius Rad
* David Abdurachmanov
* Hesham Almatary
* Ivan Griffin
* Jim Wilson
* Kito Cheng
* Michael Clark
* Palmer Dabbelt
* Richard Henderson
* Sagar Karandikar
* Shea Levy
* Stefan O'Rear

Notes:

* contributor email addresses available off-list on request.
* checkpatch has been run on all 23 patches.
* checkpatch exceptions are noted in patches that have errors.
* passes "make check" on full build for all targets
* tested riscv-linux-4.6.2 on 'spike_v1.9.1' machine
* tested riscv-linux-4.15 on 'spike_v1.10' and 'virt' machines
* tested SiFive HiFive1 binaries in 'sifive_e' machine
* tested RV64 on 32-bit i386

This patch series includes the following patches:

# gpg: Signature made Thu 08 Mar 2018 19:40:20 GMT
# gpg:                using DSA key 6BF1D7B357EF3E4F
# gpg: Good signature from "Michael Clark <address@hidden>"
# gpg:                 aka "Michael Clark <address@hidden>"
# gpg:                 aka "Michael Clark <address@hidden>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7C99 930E B17C D8BA 073D  5EFA 6BF1 D7B3 57EF 3E4F

* remotes/riscv/tags/riscv-qemu-upstream-v8.2: (23 commits)
  RISC-V Build Infrastructure
  SiFive Freedom U Series RISC-V Machine
  SiFive Freedom E Series RISC-V Machine
  SiFive RISC-V PRCI Block
  SiFive RISC-V UART Device
  RISC-V VirtIO Machine
  SiFive RISC-V Test Finisher
  RISC-V Spike Machines
  SiFive RISC-V PLIC Block
  SiFive RISC-V CLINT Block
  RISC-V HART Array
  RISC-V HTIF Console
  Add symbol table callback interface to load_elf
  RISC-V Linux User Emulation
  RISC-V Physical Memory Protection
  RISC-V TCG Code Generation
  RISC-V GDB Stub
  RISC-V FPU Support
  RISC-V CPU Helpers
  RISC-V Disassembler
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/9fa673c3e363...d9bbfea646e8