[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-commits] [qemu/qemu] 022d72: hw/arm/aspeed: directly map the seria
|
From: |
GitHub |
|
Subject: |
[Qemu-commits] [qemu/qemu] 022d72: hw/arm/aspeed: directly map the serial device to t... |
|
Date: |
Thu, 15 Feb 2018 11:40:57 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 022d72d0b10ba16759cad8563b1cf38ff698967e
https://github.com/qemu/qemu/commit/022d72d0b10ba16759cad8563b1cf38ff698967e
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M hw/arm/aspeed_soc.c
Log Message:
-----------
hw/arm/aspeed: directly map the serial device to the system address space
(qemu) info mtree
address-space: cpu-memory-0
0000000000000000-ffffffffffffffff (prio 0, i/o): system
0000000000000000-0000000007ffffff (prio 0, rom): aspeed.boot_rom
000000001e600000-000000001e7fffff (prio -1, i/o): aspeed_soc.io
- 000000001e784000-000000001e78401f (prio 0, i/o): serial
000000001e620000-000000001e6200ff (prio 0, i/o): aspeed.smc.ast2500-fmc
000000001e630000-000000001e6300ff (prio 0, i/o): aspeed.smc.ast2500-spi1
[...]
000000001e720000-000000001e728fff (prio 0, ram): aspeed.sram
000000001e782000-000000001e782fff (prio 0, i/o): aspeed.timer
+ 000000001e784000-000000001e78401f (prio 0, i/o): serial
000000001e785000-000000001e78501f (prio 0, i/o): aspeed.wdt
000000001e785020-000000001e78503f (prio 0, i/o): aspeed.wdt
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: c7c3c9f8d06a219157e0d6ddd61093deb1cf7235
https://github.com/qemu/qemu/commit/c7c3c9f8d06a219157e0d6ddd61093deb1cf7235
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io
(qemu) info mtree
address-space: cpu-memory-0
0000000000000000-ffffffffffffffff (prio 0, i/o): system
0000000000000000-0000000007ffffff (prio 0, rom): aspeed.boot_rom
- 000000001e600000-000000001e7fffff (prio -1, i/o): aspeed_soc.io
+ 000000001e600000-000000001e7fffff (prio -1000, i/o): aspeed_soc.io
000000001e620000-000000001e6200ff (prio 0, i/o): aspeed.smc.ast2500-fmc
000000001e630000-000000001e6300ff (prio 0, i/o): aspeed.smc.ast2500-spi1
000000001e631000-000000001e6310ff (prio 0, i/o): aspeed.smc.ast2500-spi2
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Andrew Jeffery <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 5d1e699988cdb1494ab4ac9a2b67d4c539143654
https://github.com/qemu/qemu/commit/5d1e699988cdb1494ab4ac9a2b67d4c539143654
Author: Richard Henderson <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Remove ARM_CP_64BIT from ZCR_EL registers
Because they are ARM_CP_STATE_AA64, ARM_CP_64BIT is implied.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: fe03d45f9e9baa89e8c4da50de771767d5d48990
https://github.com/qemu/qemu/commit/fe03d45f9e9baa89e8c4da50de771767d5d48990
Author: Richard Henderson <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Enforce FP access to FPCR/FPSR
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: b916c9c35ce8158bf7f9ed5514eb279e52875de2
https://github.com/qemu/qemu/commit/b916c9c35ce8158bf7f9ed5514eb279e52875de2
Author: Richard Henderson <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Suppress TB end for FPCR/FPSR
Nothing in either register affects the TB.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 490aa7f13a2ad31f92205879c4dc2387b602ef14
https://github.com/qemu/qemu/commit/490aa7f13a2ad31f92205879c4dc2387b602ef14
Author: Richard Henderson <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Enforce access to ZCR_EL at translation
This also makes sure that we get the correct ordering of
SVE vs FP exceptions.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 4ff55bcb0ee6452b768835f86d94bd727185f812
https://github.com/qemu/qemu/commit/4ff55bcb0ee6452b768835f86d94bd727185f812
Author: Richard Henderson <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Handle SVE registers when using clear_vec_high
When storing to an AdvSIMD FP register, all of the high
bits of the SVE register are zeroed. Therefore, call it
more often with is_q as a parameter.
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 5a53e2c1dc939fea1af92cc126ee546d8211d412
https://github.com/qemu/qemu/commit/5a53e2c1dc939fea1af92cc126ee546d8211d412
Author: Peter Maydell <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.c
Log Message:
-----------
hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC
Instead of hardcoding the values of M profile ID registers in the
NVIC, use the fields in the CPU struct. This will allow us to
give different M profile CPU types different ID register values.
This commit includes the addition of the missing ID_ISAR5,
which exists as RES0 in both v7M and v8M.
(The values of the ID registers might be wrong for the M4 --
this commit leaves the behaviour there unchanged.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 4f2eff36ad2d8f19a63544ff77b572d307c7f5c9
https://github.com/qemu/qemu/commit/4f2eff36ad2d8f19a63544ff77b572d307c7f5c9
Author: Peter Maydell <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M hw/intc/armv7m_nvic.c
Log Message:
-----------
hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling
The PENDNMISET/CLR bits in the ICSR should be RAZ/WI from
NonSecure state if the AIRCR.BFHFNMINS bit is zero. We had
misimplemented this as making the bits RAZ/WI from both
Secure and NonSecure states. Fix this bug by checking
attrs.secure so that Secure code can pend and unpend NMIs.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: e8ab26c48475e746d0aa0c4da2128c626dc00c0a
https://github.com/qemu/qemu/commit/e8ab26c48475e746d0aa0c4da2128c626dc00c0a
Author: Peter Maydell <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M hw/intc/armv7m_nvic.c
Log Message:
-----------
hw/intc/armv7m_nvic: Implement M profile cache maintenance ops
For M profile cores, cache maintenance operations are done by
writing to special registers in the system register space.
For QEMU, cache operations are always NOPs, since we don't
implement the cache. Implementing these explicitly avoids
a spurious LOG_GUEST_ERROR when the guest uses them.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: ae7c5c855b71f2de23dbad3b97bbe1c0375d6fd3
https://github.com/qemu/qemu/commit/ae7c5c855b71f2de23dbad3b97bbe1c0375d6fd3
Author: Peter Maydell <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M hw/intc/armv7m_nvic.c
Log Message:
-----------
hw/intc/armv7m_nvic: Implement v8M CPPWR register
The Coprocessor Power Control Register (CPPWR) is new in v8M.
It allows software to control whether coprocessors are allowed
to power down and lose their state. QEMU doesn't have any
notion of power control, so we choose the IMPDEF option of
making the whole register RAZ/WI (indicating that no coprocessors
can ever power down and lose state).
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 43bbce7fbef22adf687dd84934fd0b2f8df807a8
https://github.com/qemu/qemu/commit/43bbce7fbef22adf687dd84934fd0b2f8df807a8
Author: Peter Maydell <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.h
M target/arm/machine.c
Log Message:
-----------
hw/intc/armv7m_nvic: Implement cache ID registers
M profile cores have a similar setup for cache ID registers
to A profile:
* Cache Level ID Register (CLIDR) is a fixed value
* Cache Type Register (CTR) is a fixed value
* Cache Size ID Registers (CCSIDR) are a bank of registers;
which one you see is selected by the Cache Size Selection
Register (CSSELR)
The only difference is that they're in the NVIC memory mapped
register space rather than being coprocessor registers.
Implement the M profile view of them.
Since neither Cortex-M3 nor Cortex-M4 implement caches,
we don't need to update their init functions and can leave
the ctr/clidr/ccsidr[] fields in their ARMCPU structs at zero.
Newer cores (like the Cortex-M33) will want to be able to
set these ID registers to non-zero values, though.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 24ac0fb129f9ce9dd96901b2377fc6271dc55b2b
https://github.com/qemu/qemu/commit/24ac0fb129f9ce9dd96901b2377fc6271dc55b2b
Author: Peter Maydell <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.h
M target/arm/machine.c
Log Message:
-----------
hw/intc/armv7m_nvic: Implement SCR
We were previously making the system control register (SCR)
just RAZ/WI. Although we don't implement the functionality
this register controls, we should at least provide the state,
including the banked state for v8M.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 6eb3a64e2a96f5ced1f7896042b01f002bf0a91f
https://github.com/qemu/qemu/commit/6eb3a64e2a96f5ced1f7896042b01f002bf0a91f
Author: Peter Maydell <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement writing to CONTROL_NS for v8M
In commit 50f11062d4c896 we added support for MSR/MRS access
to the NS banked special registers, but we forgot to implement
the support for writing to CONTROL_NS. Correct the omission.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 12fbf1a1639ed916fda948718dac0d30b82b954e
https://github.com/qemu/qemu/commit/12fbf1a1639ed916fda948718dac0d30b82b954e
Author: Peter Maydell <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M hw/intc/armv7m_nvic.c
Log Message:
-----------
hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions
In many of the NVIC registers relating to interrupts, we
have to convert from a byte offset within a register set
into the number of the first interrupt which is affected.
We were getting this wrong for:
* reads of NVIC_ISPR<n>, NVIC_ISER<n>, NVIC_ICPR<n>, NVIC_ICER<n>,
NVIC_IABR<n> -- in all these cases we were missing the "* 8"
needed to convert from the byte offset to the interrupt number
(since all these registers use one bit per interrupt)
* writes of NVIC_IPR<n> had the opposite problem of a spurious
"* 8" (since these registers use one byte per interrupt)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Commit: 478257709a052f94bbe504ef295c876bbec174a7
https://github.com/qemu/qemu/commit/478257709a052f94bbe504ef295c876bbec174a7
Author: Peter Maydell <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M target/arm/machine.c
Log Message:
-----------
target/arm: Add AIRCR to vmstate struct
In commit commit 3b2e934463121 we added support for the AIRCR
register holding state, but forgot to add it to the vmstate
structs. Since it only holds r/w state if the security extension
is implemented, we can just add it to vmstate_m_security.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: e1e7cbc9046c776dc63c37b9b682f8179bc8e898
https://github.com/qemu/qemu/commit/e1e7cbc9046c776dc63c37b9b682f8179bc8e898
Author: Peter Maydell <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M target/arm/machine.c
Log Message:
-----------
target/arm: Migrate v7m.other_sp
In commit abc24d86cc0364f we accidentally broke migration of
the stack pointer value for the mode (process, handler) the CPU
is not currently running as. (The commit correctly removed the
no-longer-used v7m.current_sp flag from the VMState but also
deleted the still very much in use v7m.other_sp SP value field.)
Add a subsection to migrate it again. (We don't need to care
about trying to retain compatibility with pre-abc24d86cc0364f
versions of QEMU, because that commit bumped the version_id
and we've since bumped it again a couple of times.)
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 57bb31568114023f67680d6fe478ceb13c51aa7d
https://github.com/qemu/qemu/commit/57bb31568114023f67680d6fe478ceb13c51aa7d
Author: Peter Maydell <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/machine.c
Log Message:
-----------
target/arm: Implement v8M MSPLIM and PSPLIM registers
The v8M architecture includes hardware support for enforcing
stack pointer limits. We don't implement this behaviour yet,
but provide the MSPLIM and PSPLIM stack pointer limit registers
as reads-as-written, so that when we do implement the checks
in future this won't break guest migration.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: d9f8bbd8eb4e95db97cf02bd03af86a3d606f4f1
https://github.com/qemu/qemu/commit/d9f8bbd8eb4e95db97cf02bd03af86a3d606f4f1
Author: Pekka Enberg <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M hw/arm/bcm2836.c
M hw/arm/raspi.c
M include/hw/arm/bcm2836.h
Log Message:
-----------
bcm2836: Make CPU type configurable
This patch adds a "cpu-type" property to BCM2836 SoC in preparation for
reusing the code for the Raspberry Pi 3, which has a different processor
model.
Signed-off-by: Pekka Enberg <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: bade58166f4466546600d824a2695a00269d10eb
https://github.com/qemu/qemu/commit/bade58166f4466546600d824a2695a00269d10eb
Author: Pekka Enberg <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M hw/arm/raspi.c
Log Message:
-----------
raspi: Raspberry Pi 3 support
This patch adds Raspberry Pi 3 support to hw/arm/raspi.c. The
differences to Pi 2 are:
- Firmware address
- Board ID
- Board revision
The CPU is different too, but that's going to be configured as part of
the machine default CPU when we introduce a new machine type.
The patch was written from scratch by me but the logic is similar to
Zoltán Baldaszti's previous work, which I used as a reference (with
permission from the author):
https://github.com/bztsrc/qemu-raspi3
Signed-off-by: Pekka Enberg <address@hidden>
[PMM: fixed trailing whitespace on one line]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: cc5a0ae03e0d011521ca5b32d3995a299b6b3ad3
https://github.com/qemu/qemu/commit/cc5a0ae03e0d011521ca5b32d3995a299b6b3ad3
Author: Peter Maydell <address@hidden>
Date: 2018-02-15 (Thu, 15 Feb 2018)
Changed paths:
M hw/arm/aspeed_soc.c
M hw/arm/bcm2836.c
M hw/arm/raspi.c
M hw/intc/armv7m_nvic.c
M include/hw/arm/aspeed_soc.h
M include/hw/arm/bcm2836.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/machine.c
M target/arm/translate-a64.c
Log Message:
-----------
Merge remote-tracking branch
'remotes/pmaydell/tags/pull-target-arm-20180215-1' into staging
target-arm queue:
* aspeed: code cleanup to use unimplemented_device
* preparatory work for 'raspi3' RaspberryPi 3 machine model
* more SVE prep work
* v8M: add minor missing registers
* v7M: fix bug where we weren't migrating v7m.other_sp
* v7M: fix bugs in handling of interrupt registers for
external interrupts beyond 32
# gpg: Signature made Thu 15 Feb 2018 18:34:40 GMT
# gpg: using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20180215-1:
raspi: Raspberry Pi 3 support
bcm2836: Make CPU type configurable
target/arm: Implement v8M MSPLIM and PSPLIM registers
target/arm: Migrate v7m.other_sp
target/arm: Add AIRCR to vmstate struct
hw/intc/armv7m_nvic: Fix byte-to-interrupt number conversions
target/arm: Implement writing to CONTROL_NS for v8M
hw/intc/armv7m_nvic: Implement SCR
hw/intc/armv7m_nvic: Implement cache ID registers
hw/intc/armv7m_nvic: Implement v8M CPPWR register
hw/intc/armv7m_nvic: Implement M profile cache maintenance ops
hw/intc/armv7m_nvic: Fix ICSR PENDNMISET/CLR handling
hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVIC
target/arm: Handle SVE registers when using clear_vec_high
target/arm: Enforce access to ZCR_EL at translation
target/arm: Suppress TB end for FPCR/FPSR
target/arm: Enforce FP access to FPCR/FPSR
target/arm: Remove ARM_CP_64BIT from ZCR_EL registers
hw/arm/aspeed: simplify using the 'unimplemented device' for aspeed_soc.io
hw/arm/aspeed: directly map the serial device to the system address space
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/f003d07337a6...cc5a0ae03e0d
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Qemu-commits] [qemu/qemu] 022d72: hw/arm/aspeed: directly map the serial device to t...,
GitHub <=