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[Qemu-commits] [qemu/qemu] da73a4: tcg: Allow multiple word entries into

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] da73a4: tcg: Allow multiple word entries into the constant...
Date: Fri, 09 Feb 2018 01:46:43 -0800 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: da73a4abca6acefc4bb55d30bd0242bdaddb6045
      
https://github.com/qemu/qemu/commit/da73a4abca6acefc4bb55d30bd0242bdaddb6045
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M tcg/tcg-pool.inc.c

  Log Message:
  -----------
  tcg: Allow multiple word entries into the constant pool

This will be required for storing vector constants.

Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: d2fd745fe8b9ac574d28b7ac63c39f6529749bd2
      
https://github.com/qemu/qemu/commit/d2fd745fe8b9ac574d28b7ac63c39f6529749bd2
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M Makefile.target
    M tcg/README
    A tcg/tcg-op-vec.c
    M tcg/tcg-op.h
    M tcg/tcg-opc.h
    M tcg/tcg.c
    M tcg/tcg.h

  Log Message:
  -----------
  tcg: Add types and basic operations for host vectors

Nothing uses or enables them yet.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 474b2e8f0f765515515b495e6872b5e18a660baf
      
https://github.com/qemu/qemu/commit/474b2e8f0f765515515b495e6872b5e18a660baf
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M tcg/tcg-op.c
    M tcg/tcg-op.h

  Log Message:
  -----------
  tcg: Standardize integral arguments to expanders

Some functions use intN_t arguments, some use uintN_t, some just
used "unsigned".  To aid putting function pointers in tables, we
need consistency.

Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: db432672dc50ed86dda17ac821b7eb07411a90af
      
https://github.com/qemu/qemu/commit/db432672dc50ed86dda17ac821b7eb07411a90af
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M Makefile.target
    M accel/tcg/Makefile.objs
    A accel/tcg/tcg-runtime-gvec.c
    M accel/tcg/tcg-runtime.h
    M configure
    A tcg/tcg-gvec-desc.h
    A tcg/tcg-op-gvec.c
    A tcg/tcg-op-gvec.h
    M tcg/tcg-op-vec.c
    M tcg/tcg-op.h
    M tcg/tcg-opc.h
    M tcg/tcg.c
    M tcg/tcg.h

  Log Message:
  -----------
  tcg: Add generic vector expanders

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: d0ec97967f940bbc11dced83422b39c224127f1e
      
https://github.com/qemu/qemu/commit/d0ec97967f940bbc11dced83422b39c224127f1e
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M accel/tcg/tcg-runtime-gvec.c
    M accel/tcg/tcg-runtime.h
    M tcg/README
    M tcg/tcg-op-gvec.c
    M tcg/tcg-op-gvec.h
    M tcg/tcg-op-vec.c
    M tcg/tcg-op.h
    M tcg/tcg-opc.h
    M tcg/tcg.c
    M tcg/tcg.h

  Log Message:
  -----------
  tcg: Add generic vector ops for constant shifts

Opcodes are added for scalar and vector shifts, but considering the
varied semantics of these do not expose them to the front ends.  Do
go ahead and provide them in case they are needed for backend expansion.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 212be173f01e85e6589fd76676827953a84a732b
      
https://github.com/qemu/qemu/commit/212be173f01e85e6589fd76676827953a84a732b
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M accel/tcg/tcg-runtime-gvec.c
    M accel/tcg/tcg-runtime.h
    M tcg/README
    M tcg/tcg-op-gvec.c
    M tcg/tcg-op-gvec.h
    M tcg/tcg-op-vec.c
    M tcg/tcg-op.h
    M tcg/tcg-opc.h
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Add generic vector ops for comparisons

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 3774030a3e523689df24a7ed22854ce7a06b0116
      
https://github.com/qemu/qemu/commit/3774030a3e523689df24a7ed22854ce7a06b0116
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M accel/tcg/tcg-runtime-gvec.c
    M accel/tcg/tcg-runtime.h
    M tcg/README
    M tcg/tcg-op-gvec.c
    M tcg/tcg-op-gvec.h
    M tcg/tcg-op-vec.c
    M tcg/tcg-op.h
    M tcg/tcg-opc.h
    M tcg/tcg.c
    M tcg/tcg.h

  Log Message:
  -----------
  tcg: Add generic vector ops for multiplication

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: f49b12c6e6a75a5bd109bcbbda072b24e5fb8dfd
      
https://github.com/qemu/qemu/commit/f49b12c6e6a75a5bd109bcbbda072b24e5fb8dfd
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M accel/tcg/tcg-runtime-gvec.c
    M accel/tcg/tcg-runtime.h
    M tcg/tcg-op-gvec.c
    M tcg/tcg-op-gvec.h

  Log Message:
  -----------
  tcg: Add generic helpers for saturating arithmetic

No vector ops as yet.  SSE only has direct support for 8- and 16-bit
saturation; handling 32- and 64-bit saturation is much more expensive.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 22fc3527034678489ec554e82fd52f8a7f05418e
      
https://github.com/qemu/qemu/commit/22fc3527034678489ec554e82fd52f8a7f05418e
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M accel/tcg/tcg-runtime-gvec.c
    M accel/tcg/tcg-runtime.h
    M tcg/tcg-op-gvec.c
    M tcg/tcg-op-gvec.h

  Log Message:
  -----------
  tcg: Add generic vector helpers with a scalar operand

Use dup to convert a non-constant scalar to a third vector.

Add addition, multiplication, and logical operations with an immediate.
Add addition, subtraction, multiplication, and logical operations with
a non-constant scalar.  Allow for the front-end to build operations in
which the scalar operand comes first.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 170ba88f45bd7b1c5593021ed8e174f663b0bd1a
      
https://github.com/qemu/qemu/commit/170ba88f45bd7b1c5593021ed8e174f663b0bd1a
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M tcg/optimize.c

  Log Message:
  -----------
  tcg/optimize: Handle vector opcodes during optimize

Trivial move and constant propagation.  Some identity and constant
function folding, but nothing that requires knowledge of the size
of the vector element.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 8b3495ea195503922c1e00253495cb6887b99dd5
      
https://github.com/qemu/qemu/commit/8b3495ea195503922c1e00253495cb6887b99dd5
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Align vector registers

Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: bc48092f5865c20893bb19200a7a320feac99eeb
      
https://github.com/qemu/qemu/commit/bc48092f5865c20893bb19200a7a320feac99eeb
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Use vector infrastructure for aa64 add/sub/logic

Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 377ef731a85773788ae328e638698d27691bd77d
      
https://github.com/qemu/qemu/commit/377ef731a85773788ae328e638698d27691bd77d
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Use vector infrastructure for aa64 mov/not/neg

Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 861a1ded24917843b9a5a99ea0a6b37c2c9a1930
      
https://github.com/qemu/qemu/commit/861a1ded24917843b9a5a99ea0a6b37c2c9a1930
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Use vector infrastructure for aa64 dup/movi

Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: cdb45a6063feb5efbb5896795e791dd3db006fbb
      
https://github.com/qemu/qemu/commit/cdb45a6063feb5efbb5896795e791dd3db006fbb
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Use vector infrastructure for aa64 constant shifts

Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 79d61de6bdc3980f0efef85f7539e129ab8a4a40
      
https://github.com/qemu/qemu/commit/79d61de6bdc3980f0efef85f7539e129ab8a4a40
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Use vector infrastructure for aa64 compares

Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 0c7c55c492c918b6275baa3fee8b176c31465e3c
      
https://github.com/qemu/qemu/commit/0c7c55c492c918b6275baa3fee8b176c31465e3c
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Use vector infrastructure for aa64 multiplies

Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 064e265d5680e5c605d6ee8370fc1e8da094e66d
      
https://github.com/qemu/qemu/commit/064e265d5680e5c605d6ee8370fc1e8da094e66d
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Use vector infrastructure for aa64 orr/bic immediate

Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 770c2fc7bb70804ae9869995fd02dadd6d7656ac
      
https://github.com/qemu/qemu/commit/770c2fc7bb70804ae9869995fd02dadd6d7656ac
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M tcg/i386/tcg-target.h
    M tcg/i386/tcg-target.inc.c
    A tcg/i386/tcg-target.opc.h

  Log Message:
  -----------
  tcg/i386: Add vector operations

The x86 vector instruction set is extremely irregular.  With newer
editions, Intel has filled in some of the blanks.  However, we don't
get many 64-bit operations until SSE4.2, introduced in 2009.

The subsequent edition was for AVX1, introduced in 2011, which added
three-operand addressing, and adjusts how all instructions should be
encoded.

Given the relatively narrow 2 year window between possible to support
and desirable to support, and to vastly simplify code maintainence,
I am only planning to support AVX1 and later cpus.

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 14e4c1e2355473ccb2939afc69ac8f25de103b92
      
https://github.com/qemu/qemu/commit/14e4c1e2355473ccb2939afc69ac8f25de103b92
  Author: Richard Henderson <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M tcg/aarch64/tcg-target.h
    M tcg/aarch64/tcg-target.inc.c
    A tcg/aarch64/tcg-target.opc.h

  Log Message:
  -----------
  tcg/aarch64: Add vector operations

Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 04bb7fe2bf55bdf66d5b7a5a719b40bbb4048178
      
https://github.com/qemu/qemu/commit/04bb7fe2bf55bdf66d5b7a5a719b40bbb4048178
  Author: Peter Maydell <address@hidden>
  Date:   2018-02-08 (Thu, 08 Feb 2018)

  Changed paths:
    M Makefile.target
    M accel/tcg/Makefile.objs
    A accel/tcg/tcg-runtime-gvec.c
    M accel/tcg/tcg-runtime.h
    M configure
    M target/arm/cpu.h
    M target/arm/translate-a64.c
    M tcg/README
    M tcg/aarch64/tcg-target.h
    M tcg/aarch64/tcg-target.inc.c
    A tcg/aarch64/tcg-target.opc.h
    M tcg/i386/tcg-target.h
    M tcg/i386/tcg-target.inc.c
    A tcg/i386/tcg-target.opc.h
    M tcg/optimize.c
    A tcg/tcg-gvec-desc.h
    A tcg/tcg-op-gvec.c
    A tcg/tcg-op-gvec.h
    A tcg/tcg-op-vec.c
    M tcg/tcg-op.c
    M tcg/tcg-op.h
    M tcg/tcg-opc.h
    M tcg/tcg-pool.inc.c
    M tcg/tcg.c
    M tcg/tcg.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180208' into staging

tcg generic vectors

# gpg: Signature made Thu 08 Feb 2018 16:47:16 GMT
# gpg:                using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <address@hidden>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-tcg-20180208:
  tcg/aarch64: Add vector operations
  tcg/i386: Add vector operations
  target/arm: Use vector infrastructure for aa64 orr/bic immediate
  target/arm: Use vector infrastructure for aa64 multiplies
  target/arm: Use vector infrastructure for aa64 compares
  target/arm: Use vector infrastructure for aa64 constant shifts
  target/arm: Use vector infrastructure for aa64 dup/movi
  target/arm: Use vector infrastructure for aa64 mov/not/neg
  target/arm: Use vector infrastructure for aa64 add/sub/logic
  target/arm: Align vector registers
  tcg/optimize: Handle vector opcodes during optimize
  tcg: Add generic vector helpers with a scalar operand
  tcg: Add generic helpers for saturating arithmetic
  tcg: Add generic vector ops for multiplication
  tcg: Add generic vector ops for comparisons
  tcg: Add generic vector ops for constant shifts
  tcg: Add generic vector expanders
  tcg: Standardize integral arguments to expanders
  tcg: Add types and basic operations for host vectors
  tcg: Allow multiple word entries into the constant pool

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/008a51bbb343...04bb7fe2bf55
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