[Qemu-commits] [qemu/qemu] 21d642: default-configs/ppc64-softmmu: Include 32-bit conf...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 21d64275adbc5655214659cb454f5476cb3c363b
      
https://github.com/qemu/qemu/commit/21d64275adbc5655214659cb454f5476cb3c363b
  Author: Thomas Huth <address@hidden>
  Date:   2018-01-20 (Sat, 20 Jan 2018)

  Changed paths:
    M default-configs/ppc64-softmmu.mak

  Log Message:
  -----------
  default-configs/ppc64-softmmu: Include 32-bit configs instead of copying them

qemu-softmmu-ppc64 is supposed to be a superset of qemu-softmmu-ppc.
However, instead of simply including the 32-bit config file, we've
duplicated all CONFIG_xxx settings there instead. This way, we've missed
some CONFIG switches in ppc64-softmmu.mak which were only added to the
32-bit config file (e.g. CONFIG_SUNGEM). Let's fix this problem by
including the 32-bit config file into the 64-bit config file instead
of duplicating all the CONFIG switches there.

Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 70218555a334c2ec2aedf0ae8dc8a6f83dc82714
      
https://github.com/qemu/qemu/commit/70218555a334c2ec2aedf0ae8dc8a6f83dc82714
  Author: Thomas Huth <address@hidden>
  Date:   2018-01-20 (Sat, 20 Jan 2018)

  Changed paths:
    M default-configs/ppc-softmmu.mak

  Log Message:
  -----------
  default-configs/ppc-softmmu: Restructure the switches according to the 
machines

Order the CONFIG switches in ppc-softmmu.mak according to the machine
classes where they are used (embedded, Mac or PReP), so that it is
easier for the users to disable a set of switches completely if they
are not needed.

Also add the missing CONFIG_IDE_SII3112 switch to the embedded section
which was previously only added to ppcemb-softmmu.mak.

And while we're at it, also remove the CONFIG_IDE_CMD646 switch since
this controller does not seem to be used by any ppc machine in QEMU.

Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: f8567a11fb63d62644dfdf1e8ca34a5b3235046f
      
https://github.com/qemu/qemu/commit/f8567a11fb63d62644dfdf1e8ca34a5b3235046f
  Author: Thomas Huth <address@hidden>
  Date:   2018-01-20 (Sat, 20 Jan 2018)

  Changed paths:
    M hw/ppc/Makefile.objs

  Log Message:
  -----------
  hw/ppc/Makefile: Add a way to disable the PPC4xx boards

We've got the config switch CONFIG_PPC4XX, so we should use it
in the Makefile accordingly and only include the PPC4xx boards
if this switch has been enabled. (Note: Unfortunately, the files
ppc4xx_devs.c and ppc405_uc.c still have to be included in the
build anyway to fulfil some complicated linker dependencies ...
so these are subject to a more thourough clean-up later)

Signed-off-by: Thomas Huth <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 1414c75d54e0e8769129beb92bc784338090afda
      
https://github.com/qemu/qemu/commit/1414c75d54e0e8769129beb92bc784338090afda
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-01-20 (Sat, 20 Jan 2018)

  Changed paths:
    M target/ppc/cpu.h

  Log Message:
  -----------
  target/ppc: fix doorbell and hypervisor doorbell definitions

commit f03a1af581b9 ("ppc: Fix POWER7 and POWER8 exception definitions")
introduced definitions for the server doorbell exceptions by reusing
the embedded definitions but this adds complexity in the powerpc_excp()
routine. Let's introduce specific definitions for the Server doorbells
exception.

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: ebca5e6d5ec2f1cf6c886a114e161261af28dc0a
      
https://github.com/qemu/qemu/commit/ebca5e6d5ec2f1cf6c886a114e161261af28dc0a
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-01-20 (Sat, 20 Jan 2018)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target/ppc: msgsnd and msgclr instructions need hypervisor privilege

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: bc8772835f7ac72b075803e4c0e00e1af87eba77
      
https://github.com/qemu/qemu/commit/bc8772835f7ac72b075803e4c0e00e1af87eba77
  Author: Greg Kurz <address@hidden>
  Date:   2018-01-20 (Sat, 20 Jan 2018)

  Changed paths:
    M hw/ppc/spapr.c

  Log Message:
  -----------
  spapr: drop duplicate variable in spapr_core_plug()

A variable is already defined at the begining of the function to
hold a pointer to the CPU core object:

    sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));

No need to define it again in the pre-2.10 compatibility code snipplet.

Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 9012a53f067a78022947e18050b145c34a3dc599
      
https://github.com/qemu/qemu/commit/9012a53f067a78022947e18050b145c34a3dc599
  Author: Greg Kurz <address@hidden>
  Date:   2018-01-20 (Sat, 20 Jan 2018)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_cpu_core.c
    M hw/ppc/spapr_rtas.c

  Log Message:
  -----------
  spapr: fix device tree properties when using compatibility mode

Commit 51f84465dd98 changed the compatility mode setting logic:
- machine reset only sets compatibility mode for the boot CPU
- compatibility mode is set for other CPUs when they are put online
  by the guest with the "start-cpu" RTAS call

This causes a regression for machines started with max-compat-cpu:
the device tree nodes related to secondary CPU cores contain wrong
"cpu-version" and "ibm,pa-features" values, as shown below.

Guest started on a POWER8 host with:
     -smp cores=2 -machine pseries,max-cpu-compat=compat7
                   ibm,pa-features = [18 00 f6 3f c7 c0 80 f0 80 00
 00 00 00 00 00 00 00 00 80 00 80 00 80 00 00 00];
                  cpu-version = <0x4d0200>;
                          ^^^
                  second CPU core
                   ibm,pa-features = <0x600f63f 0xc70080c0>;
                  cpu-version = <0xf000003>;
                          ^^^
                    boot CPU core

The second core is advertised in raw POWER8 mode. This happens because
CAS assumes all CPUs to have the same compatibility mode. Since the
boot CPU already has the requested compatibility mode, the CAS code
does not set it for the secondary one, and exposes the bogus device
tree properties in in the CAS response to the guest.

A similar situation is observed when hot-plugging a CPU core. The
related device tree properties are generated and exposed to guest
with the "ibm,configure-connector" RTAS before "start-cpu" is called.
The CPU core is advertised to the guest in raw mode as well.

It both cases, it boils down to the fact that "start-cpu" happens too
late. This can be fixed globally by propagating the compatibility mode
of the boot CPU to the other CPUs during reset.  For this to work, the
compatibility mode of the boot CPU must be set before the machine code
actually resets all CPUs.

It is not needed to set the compatibility mode in "start-cpu" anymore,
so the code is dropped.

Fixes: 51f84465dd98
Signed-off-by: Greg Kurz <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: b62b368627ea160d2bfd7886aa690047480036a0
      
https://github.com/qemu/qemu/commit/b62b368627ea160d2bfd7886aa690047480036a0
  Author: address@hidden <address@hidden>
  Date:   2018-01-20 (Sat, 20 Jan 2018)

  Changed paths:
    M target/ppc/translate.c

  Log Message:
  -----------
  target-ppc: optimize cmp translation

We know that only one bit (in addition to SO) is going to be set in
the condition register, so do two movconds instead of three setconds,
three shifts and two ORs.

For ppc64-linux-user, the code size reduction is around 5% and the
performance improvement slightly less than 10%.  For softmmu, the
improvement is around 5%.

Signed-off-by: Paolo Bonzini <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: cf4969ec35c3502cfe2ffe5a229504607f4a2589
      
https://github.com/qemu/qemu/commit/cf4969ec35c3502cfe2ffe5a229504607f4a2589
  Author: BALATON Zoltan <address@hidden>
  Date:   2018-01-20 (Sat, 20 Jan 2018)

  Changed paths:
    M hw/display/sm501.c

  Log Message:
  -----------
  sm501: Add missing break to case

Noticed by Coverity, forgotten in 5690d9ece

Reported-by: Peter Maydell <address@hidden>
Signed-off-by: BALATON Zoltan <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 3a14ba466488fc717dccd4429487295d79fe0775
      
https://github.com/qemu/qemu/commit/3a14ba466488fc717dccd4429487295d79fe0775
  Author: BALATON Zoltan <address@hidden>
  Date:   2018-01-20 (Sat, 20 Jan 2018)

  Changed paths:
    M hw/ide/sii3112.c

  Log Message:
  -----------
  sii3112: Add explicit type casts to avoid unintended sign extension

Noticed by Coverity

Reported-by: Peter Maydell <address@hidden>
Signed-off-by: BALATON Zoltan <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 7af1e7b022641e4cc330a75ab50fa64683fe4847
      
https://github.com/qemu/qemu/commit/7af1e7b022641e4cc330a75ab50fa64683fe4847
  Author: Cédric Le Goater <address@hidden>
  Date:   2018-01-20 (Sat, 20 Jan 2018)

  Changed paths:
    M target/ppc/cpu.h
    M target/ppc/excp_helper.c
    M target/ppc/helper.h
    M target/ppc/translate.c
    M target/ppc/translate_init.c

  Log Message:
  -----------
  target/ppc: add support for hypervisor doorbells on book3s CPUs

The hypervisor doorbells are used by skiboot and Linux on POWER9
processors to wake up secondaries.

This adds processor control support to the Server architecture by
reusing the Embedded support. They are very similar, only the bits
definition of the CPU identifier differ.

Still to be done is message broadcast to all threads of the same
processor.

Signed-off-by: Cédric Le Goater <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: 1f63ebaa91f73f469c8f107dbd266cabdbea3a40
      
https://github.com/qemu/qemu/commit/1f63ebaa91f73f469c8f107dbd266cabdbea3a40
  Author: Suraj Jitindar Singh <address@hidden>
  Date:   2018-01-20 (Sat, 20 Jan 2018)

  Changed paths:
    M hw/ppc/spapr_caps.c

  Log Message:
  -----------
  target/ppc/spapr_caps: Add macro to generate spapr_caps migration vmstate

The vmstate description and the contained needed function for migration
of spapr_caps is the same for each cap, with the name of the cap
substituted. As such introduce a macro to allow for easier generation of
these.

Convert the three existing spapr_caps (htm, vsx, and dfp) to use this
macro.

Signed-off-by: Suraj Jitindar Singh <address@hidden>
Signed-off-by: David Gibson <address@hidden>


  Commit: ee264eb32c14f076c964fc34ee66f6f95cce2080
      
https://github.com/qemu/qemu/commit/ee264eb32c14f076c964fc34ee66f6f95cce2080
  Author: Peter Maydell <address@hidden>
  Date:   2018-01-22 (Mon, 22 Jan 2018)

  Changed paths:
    M default-configs/ppc-softmmu.mak
    M default-configs/ppc64-softmmu.mak
    M hw/display/sm501.c
    M hw/ide/sii3112.c
    M hw/ppc/Makefile.objs
    M hw/ppc/spapr.c
    M hw/ppc/spapr_caps.c
    M hw/ppc/spapr_cpu_core.c
    M hw/ppc/spapr_rtas.c
    M target/ppc/cpu.h
    M target/ppc/excp_helper.c
    M target/ppc/helper.h
    M target/ppc/translate.c
    M target/ppc/translate_init.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.12-20180121' 
into staging

ppc patch queue 2018-01-21

This request supersedes the one from 2018-01-19.  The only difference
is that the patch deprecating ppcemb-softmmu, and thereby creating
many annying warnings from make check has been removed.

Highlights are:
  * Significant TCG speedup by optimizing cmp generation
  * Fix a regression caused by recent change to set compat mode on
    hotplugged cpus
  * Cleanup of default configs
  * Some implementation of msgsnd/msgrcv instructions for server chips

# gpg: Signature made Sun 21 Jan 2018 05:30:54 GMT
# gpg:                using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <address@hidden>"
# gpg:                 aka "David Gibson (Red Hat) <address@hidden>"
# gpg:                 aka "David Gibson (ozlabs.org) <address@hidden>"
# gpg:                 aka "David Gibson (kernel.org) <address@hidden>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.12-20180121:
  target/ppc/spapr_caps: Add macro to generate spapr_caps migration vmstate
  target/ppc: add support for hypervisor doorbells on book3s CPUs
  sii3112: Add explicit type casts to avoid unintended sign extension
  sm501: Add missing break to case
  target-ppc: optimize cmp translation
  spapr: fix device tree properties when using compatibility mode
  spapr: drop duplicate variable in spapr_core_plug()
  target/ppc: msgsnd and msgclr instructions need hypervisor privilege
  target/ppc: fix doorbell and hypervisor doorbell definitions
  hw/ppc/Makefile: Add a way to disable the PPC4xx boards
  default-configs/ppc-softmmu: Restructure the switches according to the 
machines
  default-configs/ppc64-softmmu: Include 32-bit configs instead of copying them

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/6df555170437...ee264eb32c14