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[Qemu-commits] [qemu/qemu] 0add92: m25p80: Add support for continuous re

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] 0add92: m25p80: Add support for continuous read out of RDS...
Date: Thu, 14 Dec 2017 07:30:30 -0800 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 0add925f7c3188a5e020e223dbb45fb24e093a24
      
https://github.com/qemu/qemu/commit/0add925f7c3188a5e020e223dbb45fb24e093a24
  Author: Francisco Iglesias <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  m25p80: Add support for continuous read out of RDSR and READ_FSR

Add support for continuous read out of the RDSR and READ_FSR status
registers until the chip select is deasserted. This feature is supported
by amongst others 1 or more flashtypes manufactured by Numonyx (Micron),
Windbond, SST, Gigadevice, Eon and Macronix.

Signed-off-by: Francisco Iglesias <address@hidden>
Acked-by: Marcin Krzemiński<address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: a87fc364f937f1d054fa3457662eb5ffe0491303
      
https://github.com/qemu/qemu/commit/a87fc364f937f1d054fa3457662eb5ffe0491303
  Author: Francisco Iglesias <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  m25p80: Add support for SST READ ID 0x90/0xAB commands

Add support for SST READ ID 0x90/0xAB commands for reading out the flash
manufacturer ID and device ID.

Signed-off-by: Francisco Iglesias <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0f5897821d3cf8ec6f198dc415d58591c47ce334
      
https://github.com/qemu/qemu/commit/0f5897821d3cf8ec6f198dc415d58591c47ce334
  Author: Francisco Iglesias <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60)

Add support for the bank address register access commands (BRRD/BRWR) and
the BULK_ERASE (0x60) command.

Signed-off-by: Francisco Iglesias <address@hidden>
Acked-by: Marcin Krzemiński <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 53dc9c79d93ca8bd246870735becd117054a12ef
      
https://github.com/qemu/qemu/commit/53dc9c79d93ca8bd246870735becd117054a12ef
  Author: Francisco Iglesias <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/block/m25p80.c

  Log Message:
  -----------
  m25p80: Add support for n25q512a11 and n25q512a13

Add support for Micron (Numonyx) n25q512a11 and n25q512a13 flashes.

Signed-off-by: Francisco Iglesias <address@hidden>
Acked-by: Marcin Krzemiński <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5394dbcca8839bfb87bc65594170ba80f45054ec
      
https://github.com/qemu/qemu/commit/5394dbcca8839bfb87bc65594170ba80f45054ec
  Author: Francisco Iglesias <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/ssi/xilinx_spips.c
    M include/hw/ssi/xilinx_spips.h

  Log Message:
  -----------
  xilinx_spips: Move FlashCMD, XilinxQSPIPS and XilinxSPIPSClass

Move the FlashCMD enum, XilinxQSPIPS and XilinxSPIPSClass structures to the
header for consistency (struct XilinxSPIPS is found there). Also move out
a define and remove two double included headers (while touching the code).
Finally, add 4 byte address commands to the FlashCMD enum.

Signed-off-by: Francisco Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c3725b8549dba4b47d17672654ca5a19a8281dfb
      
https://github.com/qemu/qemu/commit/c3725b8549dba4b47d17672654ca5a19a8281dfb
  Author: Francisco Iglesias <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Update striping to be big-endian bit order

Update striping functionality to be big-endian bit order (as according to
the Zynq-7000 Technical Reference Manual). Output thereafter the even bits
into the flash memory connected to the lower QSPI bus and the odd bits into
the flash memory connected to the upper QSPI bus.

Signed-off-by: Francisco Iglesias <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ef06ca3946e284cb86fa712ba00f1c961e9456db
      
https://github.com/qemu/qemu/commit/ef06ca3946e284cb86fa712ba00f1c961e9456db
  Author: Francisco Iglesias <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/ssi/xilinx_spips.c
    M include/hw/ssi/xilinx_spips.h

  Log Message:
  -----------
  xilinx_spips: Add support for RX discard and RX drain

Add support for the RX discard and RX drain functionality. Also transmit
one byte per dummy cycle (to the flash memories) with commands that require
these.

Signed-off-by: Francisco Iglesias <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2fdd171edf5661b10ade16f33c2c0b0ed13afdf5
      
https://github.com/qemu/qemu/commit/2fdd171edf5661b10ade16f33c2c0b0ed13afdf5
  Author: Francisco Iglesias <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Make tx/rx_data_bytes more generic and reusable

Make tx/rx_data_bytes more generic so they can be reused (when adding
support for the Zynqmp Generic QSPI).

Signed-off-by: Francisco Iglesias <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 275e28cccc1a915cc1ac6bdf367aa71555593bb4
      
https://github.com/qemu/qemu/commit/275e28cccc1a915cc1ac6bdf367aa71555593bb4
  Author: Francisco Iglesias <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/ssi/xilinx_spips.c
    M include/hw/ssi/xilinx_spips.h

  Log Message:
  -----------
  xilinx_spips: Add support for zero pumping

Add support for zero pumping according to the transfer size register.

Signed-off-by: Francisco Iglesias <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: fbfaa5074c455c5d61c9242128e7789595d2327d
      
https://github.com/qemu/qemu/commit/fbfaa5074c455c5d61c9242128e7789595d2327d
  Author: Francisco Iglesias <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Add support for 4 byte addresses in the LQSPI

Add support for 4 byte addresses in the LQSPI and correct LQSPI_CFG_SEP_BUS.

Signed-off-by: Francisco Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2e1cf2c9685978193ef429cdb711bf50debea9d8
      
https://github.com/qemu/qemu/commit/2e1cf2c9685978193ef429cdb711bf50debea9d8
  Author: Francisco Iglesias <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done

Don't set TX FIFO UNDERFLOW interrupt after transmitting the commands.
Also update interrupts after reading out the interrupt status.

Signed-off-by: Francisco Iglesias <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c95997a39de679a1ae29c2f0637ec07f0291fedc
      
https://github.com/qemu/qemu/commit/c95997a39de679a1ae29c2f0637ec07f0291fedc
  Author: Francisco Iglesias <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/ssi/xilinx_spips.c
    M include/hw/ssi/xilinx_spips.h

  Log Message:
  -----------
  xilinx_spips: Add support for the ZynqMP Generic QSPI

Add support for the Zynq Ultrascale MPSoc Generic QSPI.

Signed-off-by: Francisco Iglesias <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: babc1f30090b8541c9669d4ba74eedf0ee2894d8
      
https://github.com/qemu/qemu/commit/babc1f30090b8541c9669d4ba74eedf0ee2894d8
  Author: Francisco Iglesias <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/arm/xlnx-zcu102.c
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  xlnx-zcu102: Add support for the ZynqMP QSPI

Add support for the ZynqMP QSPI (consisting of the Generic QSPI and Legacy
QSPI) and connect Numonyx n25q512a11 flashes to it.

Signed-off-by: Francisco Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 7e7244796bc8d69a277669bb4137980fd2527b13
      
https://github.com/qemu/qemu/commit/7e7244796bc8d69a277669bb4137980fd2527b13
  Author: Eric Auger <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/intc/arm_gicv3_its_common.c
    M hw/intc/arm_gicv3_its_kvm.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Don't call post_load on reset

>From the very beginning, post_load() was called from common
reset. This is not standard and obliged to discriminate the
reset case from the restore case using the iidr value.

Let's get rid of that call.

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c9aedf8ca4b4c16641812c018770f5da3ebf640c
      
https://github.com/qemu/qemu/commit/c9aedf8ca4b4c16641812c018770f5da3ebf640c
  Author: Eric Auger <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/intc/arm_gicv3_its_kvm.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Implement a minimalist reset

At the moment the ITS is not properly reset and this causes
various bugs on save/restore. We implement a minimalist reset
through individual register writes but for kernel versions
before v4.15 this fails voiding the vITS cache. We cannot
claim we have a comprehensive reset (hence the error message)
but that's better than nothing.

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: dd8739669f95b30653a3a05cb2e21da3f52894fa
      
https://github.com/qemu/qemu/commit/dd8739669f95b30653a3a05cb2e21da3f52894fa
  Author: Eric Auger <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M include/standard-headers/asm-s390/virtio-ccw.h
    M include/standard-headers/asm-x86/hyperv.h
    M include/standard-headers/linux/input-event-codes.h
    M include/standard-headers/linux/input.h
    M include/standard-headers/linux/pci_regs.h
    M linux-headers/asm-arm/kvm.h
    M linux-headers/asm-arm/kvm_para.h
    M linux-headers/asm-arm/unistd.h
    M linux-headers/asm-arm64/kvm.h
    M linux-headers/asm-arm64/unistd.h
    M linux-headers/asm-powerpc/epapr_hcalls.h
    M linux-headers/asm-powerpc/kvm.h
    M linux-headers/asm-powerpc/kvm_para.h
    M linux-headers/asm-powerpc/unistd.h
    M linux-headers/asm-s390/kvm.h
    M linux-headers/asm-s390/kvm_para.h
    M linux-headers/asm-s390/unistd.h
    M linux-headers/asm-x86/kvm.h
    M linux-headers/asm-x86/kvm_para.h
    M linux-headers/asm-x86/unistd.h
    M linux-headers/linux/kvm.h
    M linux-headers/linux/kvm_para.h
    M linux-headers/linux/psci.h
    M linux-headers/linux/userfaultfd.h
    M linux-headers/linux/vfio.h
    M linux-headers/linux/vfio_ccw.h
    M linux-headers/linux/vhost.h

  Log Message:
  -----------
  linux-headers: update to 4.15-rc1

Update headers against v4.15-rc1.

Signed-off-by: Eric Auger <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ba2aecabefc5c06a91c12dd421564afd63f083ff
      
https://github.com/qemu/qemu/commit/ba2aecabefc5c06a91c12dd421564afd63f083ff
  Author: Eric Auger <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/intc/arm_gicv3_its_kvm.c

  Log Message:
  -----------
  hw/intc/arm_gicv3_its: Implement full reset

Voiding the ITS caches is not supposed to happen via
individual register writes. So we introduced a dedicated
ITS KVM device ioctl to perform a cold reset of the ITS:
KVM_DEV_ARM_VGIC_GRP_CTRL/KVM_DEV_ARM_ITS_CTRL_RESET. Let's
use this latter if the kernel supports it.

Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1169d3aa5b19adca9384d954d80e1f48da388284
      
https://github.com/qemu/qemu/commit/1169d3aa5b19adca9384d954d80e1f48da388284
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Handle SPSEL and current stack being out of sync in MSP/PSP reads

For v8M it is possible for the CONTROL.SPSEL bit value and the
current stack to be out of sync. This means we need to update
the checks used in reads and writes of the PSP and MSP special
registers to use v7m_using_psp() rather than directly checking
the SPSEL bit in the control register.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 83d7f86d3d27473c0aac79c1baaa5c2ab01b02d9
      
https://github.com/qemu/qemu/commit/83d7f86d3d27473c0aac79c1baaa5c2ab01b02d9
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Allow explicit writes to CONTROL.SPSEL in Handler mode

In ARMv7M the CPU ignores explicit writes to CONTROL.SPSEL
in Handler mode. In v8M the behaviour is slightly different:
writes to the bit are permitted but will have no effect.

We've already done the hard work to handle the value in
CONTROL.SPSEL being out of sync with what stack pointer is
actually in use, so all we need to do to fix this last loose
end is to update the condition we use to guard whether we
call write_v7m_control_spsel() on the register write.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 871bec7c44a453d9cab972ce1b5d12e1af0545ab
      
https://github.com/qemu/qemu/commit/871bec7c44a453d9cab972ce1b5d12e1af0545ab
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Add missing M profile case to regime_is_user()

When we added the ARMMMUIdx_MSUser MMU index we forgot to
add it to the case statement in regime_is_user(), so we
weren't treating it as unprivileged when doing MPU lookups.
Correct the omission.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 62593718d77c06ad2b5e942727cead40775d2395
      
https://github.com/qemu/qemu/commit/62593718d77c06ad2b5e942727cead40775d2395
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Split M profile MNegPri mmu index into user and priv

For M profile, we currently have an mmu index MNegPri for
"requested execution priority negative". This fails to
distinguish "requested execution priority negative, privileged"
from "requested execution priority negative, usermode", but
the two can return different results for MPU lookups. Fix this
by splitting MNegPri into MNegPriPriv and MNegPriUser, and
similarly for the Secure equivalent MSNegPri.

This takes us from 6 M profile MMU modes to 8, which means
we need to bump NB_MMU_MODES; this is OK since the point
where we are forced to reduce TLB sizes is 9 MMU modes.

(It would in theory be possible to stick with 6 MMU indexes:
{mpu-disabled,user,privileged} x {secure,nonsecure} since
in the MPU-disabled case the result of an MPU lookup is
always the same for both user and privileged code. However
we would then need to rework the TB flags handling to put
user/priv into the TB flags separately from the mmuidx.
Adding an extra couple of mmu indexes is simpler.)

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: ec8e3340286a87d3924c223d60ba5c994549f796
      
https://github.com/qemu/qemu/commit/ec8e3340286a87d3924c223d60ba5c994549f796
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Create new arm_v7m_mmu_idx_for_secstate_and_priv()

The TT instruction is going to need to look up the MMU index
for a specified security and privilege state. Refactor the
existing arm_v7m_mmu_idx_for_secstate() into a version that
lets you specify the privilege state and one that uses the
current state of the CPU.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 54317c0ff3a3c0f6b2c3a1d3c8b5d93686a86d24
      
https://github.com/qemu/qemu/commit/54317c0ff3a3c0f6b2c3a1d3c8b5d93686a86d24
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Factor MPU lookup code out of get_phys_addr_pmsav8()

For the TT instruction we're going to need to do an MPU lookup that
also tells us which MPU region the access hit. This requires us
to do the MPU lookup without first doing the SAU security access
check, so pull the MPU lookup parts of get_phys_addr_pmsav8()
out into their own function.

The TT instruction also needs to know the MPU region number which
the lookup hit, so provide this information to the caller of the
MPU lookup code, even though get_phys_addr_pmsav8() doesn't
need to know it.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 5158de241b0fb344a6c948dfcbc4e611ab5fafbe
      
https://github.com/qemu/qemu/commit/5158de241b0fb344a6c948dfcbc4e611ab5fafbe
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: Implement TT instruction

Implement the TT instruction which queries the security
state and access permissions of a memory location.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 1fa498fe0de979030bd1f481046e9f1c5574a584
      
https://github.com/qemu/qemu/commit/1fa498fe0de979030bd1f481046e9f1c5574a584
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Provide fault type enum and FSR conversion functions

Currently get_phys_addr() and its various subfunctions return
a hard-coded fault status register value for translation
failures. This is awkward because FSR values these days may
be either long-descriptor format or short-descriptor format.
Worse, the right FSR type to use doesn't depend only on the
translation table being walked -- some cases, like fault
info reported to AArch32 EL2 for some kinds of ATS operation,
must be in long-descriptor format even if the translation
table being walked was short format. We can't get those cases
right with our current approach.

Provide fields in the ARMMMUFaultInfo struct which allow
get_phys_addr() to provide sufficient information for a caller to
construct an FSR value themselves, and utility functions which do
this for both long and short format FSR values, as a first step in
switching get_phys_addr() and its children to only returning the
failure cause in the ARMMMUFaultInfo struct.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Stefano Stabellini <address@hidden>
Message-id: address@hidden


  Commit: 3795a6de9f7ec4a7e3dcb8bf02a88a014147b0b0
      
https://github.com/qemu/qemu/commit/3795a6de9f7ec4a7e3dcb8bf02a88a014147b0b0
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Remove fsr argument from arm_ld*_ptw()

All the callers of arm_ldq_ptw() and arm_ldl_ptw() ignore the value
that those functions store in the fsr argument on failure: if they
return failure to their callers they will always overwrite the fsr
value with something else.

Remove the argument from these functions and S1_ptw_translate().
This will simplify removing fsr from the calling functions.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Stefano Stabellini <address@hidden>
Message-id: address@hidden


  Commit: f989983e8dc9be6bc3468c6dbe46fcb1501a740c
      
https://github.com/qemu/qemu/commit/f989983e8dc9be6bc3468c6dbe46fcb1501a740c
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Convert get_phys_addr_v5() to not return FSC values

Make get_phys_addr_v5() return a fault type in the ARMMMUFaultInfo
structure, which we convert to the FSC at the callsite.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Stefano Stabellini <address@hidden>
Message-id: address@hidden


  Commit: f06cf243945ccb24cb9578304306ae7fcb4cf3fd
      
https://github.com/qemu/qemu/commit/f06cf243945ccb24cb9578304306ae7fcb4cf3fd
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Convert get_phys_addr_v6() to not return FSC values

Make get_phys_addr_v6() return a fault type in the ARMMMUFaultInfo
structure, which we convert to the FSC at the callsite.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Stefano Stabellini <address@hidden>
Message-id: address@hidden


  Commit: da909b2c23a68e57bbcb6be98229e40df606f0c8
      
https://github.com/qemu/qemu/commit/da909b2c23a68e57bbcb6be98229e40df606f0c8
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Convert get_phys_addr_lpae() to not return FSC values

Make get_phys_addr_v6() return a fault type in the ARMMMUFaultInfo
structure, which we convert to the FSC at the callsite.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Stefano Stabellini <address@hidden>
Message-id: address@hidden


  Commit: 53a4e5c5b07b2f50c538511b74b0d3d4964695ea
      
https://github.com/qemu/qemu/commit/53a4e5c5b07b2f50c538511b74b0d3d4964695ea
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Convert get_phys_addr_pmsav5() to not return FSC values

Make get_phys_addr_pmsav5() return a fault type in the ARMMMUFaultInfo
structure, which we convert to the FSC at the callsite.

Note that PMSAv5 does not define any guest-visible fault status
register, so the different "fsr" values we were previously
returning are entirely arbitrary. So we can just switch to using
the most appropriae fi->type values without worrying that we
need to special-case FaultInfo->FSC conversion for PMSAv5.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Stefano Stabellini <address@hidden>
Message-id: address@hidden


  Commit: 9375ad15338b24e06109071ac3a85df48a2cc2e6
      
https://github.com/qemu/qemu/commit/9375ad15338b24e06109071ac3a85df48a2cc2e6
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Convert get_phys_addr_pmsav7() to not return FSC values

Make get_phys_addr_pmsav7() return a fault type in the ARMMMUFaultInfo
structure, which we convert to the FSC at the callsite.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Stefano Stabellini <address@hidden>
Message-id: address@hidden


  Commit: 3f551b5b7380ff131fe22944aa6f5b166aa13caf
      
https://github.com/qemu/qemu/commit/3f551b5b7380ff131fe22944aa6f5b166aa13caf
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Convert get_phys_addr_pmsav8() to not return FSC values

Make get_phys_addr_pmsav8() return a fault type in the ARMMMUFaultInfo
structure, which we convert to the FSC at the callsite.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Stefano Stabellini <address@hidden>
Message-id: address@hidden


  Commit: 681f9a89d201d7891e2c60dff5e5415d8f618518
      
https://github.com/qemu/qemu/commit/681f9a89d201d7891e2c60dff5e5415d8f618518
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M target/arm/op_helper.c

  Log Message:
  -----------
  target/arm: Use ARMMMUFaultInfo in deliver_fault()

Now that ARMMMUFaultInfo is guaranteed to have enough information
to construct a fault status code, we can pass it in to the
deliver_fault() function and let it generate the correct type
of FSR for the destination, rather than relying on the value
provided by get_phys_addr().

I don't think there are any cases the old code was getting
wrong, but this is more obviously correct.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Stefano Stabellini <address@hidden>
Message-id: address@hidden


  Commit: 5efe9ed45dec775ebe91ce72bd805ee780d16064
      
https://github.com/qemu/qemu/commit/5efe9ed45dec775ebe91ce72bd805ee780d16064
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Ignore fsr from get_phys_addr() in do_ats_write()

In do_ats_write(), rather than using the FSR value from get_phys_addr(),
construct the PAR values using the information in the ARMMMUFaultInfo
struct. This allows us to create a PAR of the correct format regardless
of what the translation table format is.

For the moment we leave the condition for "when should this be a
64 bit PAR" as it was previously; this will need to be fixed to
properly support AArch32 Hyp mode.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Stefano Stabellini <address@hidden>
Message-id: address@hidden


  Commit: bc52bfeb3be2052942b7dac8ba284f342ac9605b
      
https://github.com/qemu/qemu/commit/bc52bfeb3be2052942b7dac8ba284f342ac9605b
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/op_helper.c

  Log Message:
  -----------
  target/arm: Remove fsr argument from get_phys_addr() and arm_tlb_fill()

All of the callers of get_phys_addr() and arm_tlb_fill() now ignore
the FSR values they return, so we can just remove the argument
entirely.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Stefano Stabellini <address@hidden>
Message-id: address@hidden


  Commit: 1313e2d7e2cd8b21741e0cf542eb09dfc4188f79
      
https://github.com/qemu/qemu/commit/1313e2d7e2cd8b21741e0cf542eb09dfc4188f79
  Author: Edgar E. Iglesias <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Extend PAR format determination

Now that do_ats_write() is entirely in control of whether to
generate a 32-bit PAR or a 64-bit PAR, we can make it use the
correct (complicated) condition for doing so.

Signed-off-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Stefano Stabellini <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
[PMM: Rebased Edgar's patch on top of get_phys_addr() refactoring;
 use arm_s1_regime_using_lpae_format() rather than
 regime_using_lpae_format() because the latter will assert
 if passed ARMMMUIdx_S12NSE0 or ARMMMUIdx_S12NSE1;
 updated commit message appropriately]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 62f018482c18c2f1a70f000a0bb361dd6d89aef4
      
https://github.com/qemu/qemu/commit/62f018482c18c2f1a70f000a0bb361dd6d89aef4
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  nvic: Make nvic_sysreg_ns_ops work with any MemoryRegion

Generalize nvic_sysreg_ns_ops so that we can pass it an
arbitrary MemoryRegion which it will use as the underlying
register implementation to apply the NS-alias behaviour
to. We'll want this so we can do the same with systick.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: 27f26bfed923e4c68a1acb61fdafcd0bc63abf71
      
https://github.com/qemu/qemu/commit/27f26bfed923e4c68a1acb61fdafcd0bc63abf71
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c
    M include/hw/intc/armv7m_nvic.h

  Log Message:
  -----------
  nvic: Make systick banked

For the v8M security extension, there should be two systick
devices, which use separate banked systick exceptions. The
register interface is banked in the same way as for other
banked registers, including the existence of an NS alias
region for secure code to access the nonsecure timer.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: d6c3768b32277559cf6424bdf1edfee1fbf9a970
      
https://github.com/qemu/qemu/commit/d6c3768b32277559cf6424bdf1edfee1fbf9a970
  Author: Prasad J Pandit <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/display/tc6393xb.c

  Log Message:
  -----------
  hw/display/tc6393xb: limit irq handler index to TC6393XB_GPIOS

The ctz32() routine could return a value greater than
TC6393XB_GPIOS=16, because the device has 24 GPIO level
bits but we only implement 16 outgoing lines. This could
lead to an OOB array access. Mask 'level' to avoid it.

Reported-by: Moguofang <address@hidden>
Signed-off-by: Prasad J Pandit <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e59f13d76bb0bb7498e49ba83f95a7445bed2b1d
      
https://github.com/qemu/qemu/commit/e59f13d76bb0bb7498e49ba83f95a7445bed2b1d
  Author: Zhaoshenglong <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: replace the unavailable email address

Since I'm not working as an assignee in Linaro, replace the Linaro email
address with my personal one.

Signed-off-by: Zhaoshenglong <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: cbf8b991f8a3ea293a6b43c6f4738cc0e19c722c
      
https://github.com/qemu/qemu/commit/cbf8b991f8a3ea293a6b43c6f4738cc0e19c722c
  Author: Alistair Francis <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Update the QSPI Mod ID reset value

Update the reset value to match the latest ZynqMP register spec.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: KONRAD Frederic <address@hidden>
Reviewed-by: Francisco Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4f0da466ca209c670c010e7aad0ed041e0bf2461
      
https://github.com/qemu/qemu/commit/4f0da466ca209c670c010e7aad0ed041e0bf2461
  Author: Alistair Francis <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/ssi/xilinx_spips.c
    M include/hw/ssi/xilinx_spips.h

  Log Message:
  -----------
  xilinx_spips: Set all of the reset values

Following the ZynqMP register spec let's ensure that all reset values
are set.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Francisco Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d3c348b6e3af3598bfcb755d59f8f4de80a2228a
      
https://github.com/qemu/qemu/commit/d3c348b6e3af3598bfcb755d59f8f4de80a2228a
  Author: Alistair Francis <address@hidden>
  Date:   2017-12-13 (Wed, 13 Dec 2017)

  Changed paths:
    M hw/ssi/xilinx_spips.c

  Log Message:
  -----------
  xilinx_spips: Use memset instead of a for loop to zero registers

Use memset() instead of a for loop to zero all of the registers.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: KONRAD Frederic <address@hidden>
Reviewed-by: Francisco Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5705b536b597de00d82807bf14bb38f542aa4491
      
https://github.com/qemu/qemu/commit/5705b536b597de00d82807bf14bb38f542aa4491
  Author: Peter Maydell <address@hidden>
  Date:   2017-12-14 (Thu, 14 Dec 2017)

  Changed paths:
    M MAINTAINERS
    M default-configs/arm-softmmu.mak
    M hw/arm/xlnx-zcu102.c
    M hw/arm/xlnx-zynqmp.c
    M hw/block/m25p80.c
    M hw/display/tc6393xb.c
    M hw/intc/arm_gicv3_its_common.c
    M hw/intc/arm_gicv3_its_kvm.c
    M hw/intc/armv7m_nvic.c
    M hw/ssi/xilinx_spips.c
    M include/hw/arm/xlnx-zynqmp.h
    M include/hw/intc/armv7m_nvic.h
    M include/hw/ssi/xilinx_spips.h
    M include/standard-headers/asm-s390/virtio-ccw.h
    M include/standard-headers/asm-x86/hyperv.h
    M include/standard-headers/linux/input-event-codes.h
    M include/standard-headers/linux/input.h
    M include/standard-headers/linux/pci_regs.h
    M linux-headers/asm-arm/kvm.h
    M linux-headers/asm-arm/kvm_para.h
    M linux-headers/asm-arm/unistd.h
    M linux-headers/asm-arm64/kvm.h
    M linux-headers/asm-arm64/unistd.h
    M linux-headers/asm-powerpc/epapr_hcalls.h
    M linux-headers/asm-powerpc/kvm.h
    M linux-headers/asm-powerpc/kvm_para.h
    M linux-headers/asm-powerpc/unistd.h
    M linux-headers/asm-s390/kvm.h
    M linux-headers/asm-s390/kvm_para.h
    M linux-headers/asm-s390/unistd.h
    M linux-headers/asm-x86/kvm.h
    M linux-headers/asm-x86/kvm_para.h
    M linux-headers/asm-x86/unistd.h
    M linux-headers/linux/kvm.h
    M linux-headers/linux/kvm_para.h
    M linux-headers/linux/psci.h
    M linux-headers/linux/userfaultfd.h
    M linux-headers/linux/vfio.h
    M linux-headers/linux/vfio_ccw.h
    M linux-headers/linux/vhost.h
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/helper.h
    M target/arm/internals.h
    M target/arm/op_helper.c
    M target/arm/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20171213' 
into staging

target-arm queue:
 * xilinx_spips: set reset values correctly
 * MAINTAINERS: fix an email address
 * hw/display/tc6393xb: limit irq handler index to TC6393XB_GPIOS
 * nvic: Make systick banked for v8M
 * refactor get_phys_addr() so we can return the right format PAR
   for ATS operations
 * implement v8M TT instruction
 * fix some minor v8M bugs
 * Implement reset for GICv3 ITS
 * xlnx-zcu102: Add support for the ZynqMP QSPI

# gpg: Signature made Wed 13 Dec 2017 18:01:31 GMT
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20171213: (43 commits)
  xilinx_spips: Use memset instead of a for loop to zero registers
  xilinx_spips: Set all of the reset values
  xilinx_spips: Update the QSPI Mod ID reset value
  MAINTAINERS: replace the unavailable email address
  hw/display/tc6393xb: limit irq handler index to TC6393XB_GPIOS
  nvic: Make systick banked
  nvic: Make nvic_sysreg_ns_ops work with any MemoryRegion
  target/arm: Extend PAR format determination
  target/arm: Remove fsr argument from get_phys_addr() and arm_tlb_fill()
  target/arm: Ignore fsr from get_phys_addr() in do_ats_write()
  target/arm: Use ARMMMUFaultInfo in deliver_fault()
  target/arm: Convert get_phys_addr_pmsav8() to not return FSC values
  target/arm: Convert get_phys_addr_pmsav7() to not return FSC values
  target/arm: Convert get_phys_addr_pmsav5() to not return FSC values
  target/arm: Convert get_phys_addr_lpae() to not return FSC values
  target/arm: Convert get_phys_addr_v6() to not return FSC values
  target/arm: Convert get_phys_addr_v5() to not return FSC values
  target/arm: Remove fsr argument from arm_ld*_ptw()
  target/arm: Provide fault type enum and FSR conversion functions
  target/arm: Implement TT instruction
  ...

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/f44cedc9166d...5705b536b597
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