[Qemu-commits] [qemu/qemu] 96a8b9: target/arm: Report GICv3 sysregs present in ID reg...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 96a8b92ed8f02d5e86ad380d3299d9f41f99b072
      
https://github.com/qemu/qemu/commit/96a8b92ed8f02d5e86ad380d3299d9f41f99b072
  Author: Peter Maydell <address@hidden>
  Date:   2017-11-20 (Mon, 20 Nov 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Report GICv3 sysregs present in ID registers if needed

The CPU ID registers ID_AA64PFR0_EL1, ID_PFR1_EL1 and ID_PFR1
have a field for reporting presence of GICv3 system registers.
We need to report this field correctly in order for Xen to
work as a guest inside QEMU emulation. We mustn't incorrectly
claim the sysregs exist when they don't, though, or Linux will
crash.

Unfortunately the way we've designed the GICv3 emulation in QEMU
puts the system registers as part of the GICv3 device, which
may be created after the CPU proper has been realized. This
means that we don't know at the point when we define the ID
registers what the correct value is. Handle this by switching
them to calling a function at runtime to read the value, where
we can fill in the GIC field appropriately.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Tested-by: Stefano Stabellini <address@hidden>
Message-id: address@hidden


  Commit: 2b75ef01caf74be5af964f97e37f07ff9034fe0b
      
https://github.com/qemu/qemu/commit/2b75ef01caf74be5af964f97e37f07ff9034fe0b
  Author: Peter Maydell <address@hidden>
  Date:   2017-11-20 (Mon, 20 Nov 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  nvic: Fix ARMv7M MPU_RBAR reads

Fix an incorrect mask expression in the handling of v7M MPU_RBAR
reads that meant that we would always report the ADDR field as zero.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Message-id: address@hidden


  Commit: 50cd71b0d347c74517dcb7da447fe657fca57d9c
      
https://github.com/qemu/qemu/commit/50cd71b0d347c74517dcb7da447fe657fca57d9c
  Author: Peter Maydell <address@hidden>
  Date:   2017-11-20 (Mon, 20 Nov 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  arm: check regime, not current state, for ATS write PAR format

In do_ats_write(), rather than using extended_addresses_enabled() to
decide whether the value we get back from get_phys_addr() is a 64-bit
format PAR or a 32-bit one, use arm_s1_regime_using_lpae_format().

This is not really the correct answer, because the PAR format
depends on the AT instruction being used, not just on the
translation regime. However getting this correct requires a
significant refactoring, so that get_phys_addr() returns raw
information about the fault which the caller can then assemble
into a suitable FSR/PAR/syndrome for its purposes, rather than
get_phys_addr() returning a pre-formatted FSR.

However this change at least improves the situation by making
the PAR work correctly for address translation operations done
at AArch64 EL2 on the EL2 translation regime. In particular,
this is necessary for Xen to be able to run in our emulation,
so this seems like a safer interim fix given that we are in freeze.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Stefano Stabellini <address@hidden>
Message-id: address@hidden


  Commit: b6e70d1d7fea681306a3c8e74934b66dc9524969
      
https://github.com/qemu/qemu/commit/b6e70d1d7fea681306a3c8e74934b66dc9524969
  Author: Joel Stanley <address@hidden>
  Date:   2017-11-20 (Mon, 20 Nov 2017)

  Changed paths:
    M hw/arm/aspeed.c
    M hw/arm/aspeed_soc.c
    M hw/misc/aspeed_scu.c
    M include/hw/misc/aspeed_scu.h

  Log Message:
  -----------
  hw/arm/aspeed: Unlock SCU when running kernel

The ASPEED hardware contains a lock register for the SCU that disables
any writes to the SCU when it is locked. The machine comes up with the
lock enabled, but on all known hardware u-boot will unlock it and leave
it unlocked when loading the kernel.

This means the kernel expects the SCU to be unlocked. When booting from
an emulated ROM the normal u-boot unlock path is executed. Things don't
go well when booting using the -kernel command line, as u-boot does not
run first.

Change behaviour so that when a kernel is passed to the machine, set the
reset value of the SCU to be unlocked.

Signed-off-by: Joel Stanley <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b350ae138fcb062f49904f5115cc5fe188a02906
      
https://github.com/qemu/qemu/commit/b350ae138fcb062f49904f5115cc5fe188a02906
  Author: Thomas Huth <address@hidden>
  Date:   2017-11-20 (Mon, 20 Nov 2017)

  Changed paths:
    M hw/arm/xlnx-zcu102.c

  Log Message:
  -----------
  hw/arm: Silence xlnx-ep108 deprecation warning during tests

The new deprecation warning for the xlnx-ep108 machine also pops up
during "make check" which is kind of confusing. Silence it if testing
mode is enabled.

Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Acked-by: Wei Huang <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 5f49d73cb3c571e1503b86a9014d2908b2036d03
      
https://github.com/qemu/qemu/commit/5f49d73cb3c571e1503b86a9014d2908b2036d03
  Author: Peter Maydell <address@hidden>
  Date:   2017-11-21 (Tue, 21 Nov 2017)

  Changed paths:
    M hw/arm/aspeed.c
    M hw/arm/aspeed_soc.c
    M hw/arm/xlnx-zcu102.c
    M hw/intc/armv7m_nvic.c
    M hw/misc/aspeed_scu.c
    M include/hw/misc/aspeed_scu.h
    M target/arm/helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20171120' 
into staging

target-arm queue:
 * hw/arm: Silence xlnx-ep108 deprecation warning during tests
 * hw/arm/aspeed: Unlock SCU when running kernel
 * arm: check regime, not current state, for ATS write PAR format
 * nvic: Fix ARMv7M MPU_RBAR reads
 * target/arm: Report GICv3 sysregs present in ID registers if needed

# gpg: Signature made Mon 20 Nov 2017 17:35:25 GMT
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20171120:
  hw/arm: Silence xlnx-ep108 deprecation warning during tests
  hw/arm/aspeed: Unlock SCU when running kernel
  arm: check regime, not current state, for ATS write PAR format
  nvic: Fix ARMv7M MPU_RBAR reads
  target/arm: Report GICv3 sysregs present in ID registers if needed

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/3da87f771311...5f49d73cb3c5