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[Qemu-commits] [qemu/qemu] 588033: fix WFI/WFE length in syndrome regist
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[Qemu-commits] [qemu/qemu] 588033: fix WFI/WFE length in syndrome register |
Date: |
Tue, 31 Oct 2017 08:32:55 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 58803318e5a546b2eb0efd7a053ed36b6c29ae6f
https://github.com/qemu/qemu/commit/58803318e5a546b2eb0efd7a053ed36b6c29ae6f
Author: Stefano Stabellini <address@hidden>
Date: 2017-10-31 (Tue, 31 Oct 2017)
Changed paths:
M target/arm/helper.h
M target/arm/internals.h
M target/arm/op_helper.c
M target/arm/psci.c
M target/arm/translate-a64.c
M target/arm/translate.c
Log Message:
-----------
fix WFI/WFE length in syndrome register
WFI/E are often, but not always, 4 bytes long. When they are, we need to
set ARM_EL_IL_SHIFT in the syndrome register.
Pass the instruction length to HELPER(wfi), use it to decrement pc
appropriately and to pass an is_16bit flag to syn_wfx, which sets
ARM_EL_IL_SHIFT if needed.
Set dc->insn in both arm_tr_translate_insn and thumb_tr_translate_insn.
Signed-off-by: Stefano Stabellini <address@hidden>
Message-id: address@hidden
[PMM: move setting of dc->insn for Thumb so it is correct for 32 bit insns]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 0f2bf05ce7b2b64f2a3ecb98de10a8100228c9a6
https://github.com/qemu/qemu/commit/0f2bf05ce7b2b64f2a3ecb98de10a8100228c9a6
Author: Alistair Francis <address@hidden>
Date: 2017-10-31 (Tue, 31 Oct 2017)
Changed paths:
M hw/arm/xlnx-zcu102.c
Log Message:
-----------
xlnx-zcu102: Specify the max number of CPUs
Specify the number of CPUs that can run on ZynqMP.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: cda607d5e0178d0268066d94dd06b89614304a7d
https://github.com/qemu/qemu/commit/cda607d5e0178d0268066d94dd06b89614304a7d
Author: Subbaraya Sundeep <address@hidden>
Date: 2017-10-31 (Tue, 31 Oct 2017)
Changed paths:
M hw/ssi/mss-spi.c
Log Message:
-----------
msf2: Remove dead code reported by Coverity
Fixed incorrect frame size mask, validated maximum frame
size in spi_write and removed dead code.
Signed-off-by: Subbaraya Sundeep <address@hidden>
Reviewed-by: Darren Kenny <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: db7b98c6bb57312a49d9c47ee890e5e50a1db86d
https://github.com/qemu/qemu/commit/db7b98c6bb57312a49d9c47ee890e5e50a1db86d
Author: Subbaraya Sundeep <address@hidden>
Date: 2017-10-31 (Tue, 31 Oct 2017)
Changed paths:
M hw/arm/msf2-soc.c
Log Message:
-----------
msf2: Wire up SYSRESETREQ in SoC for system reset
Implemented system reset by creating SYSRESETREQ gpio
out from nvic.
Signed-off-by: Subbaraya Sundeep <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 168df2dea701bbf3118bdfea7794369dfa694d3d
https://github.com/qemu/qemu/commit/168df2dea701bbf3118bdfea7794369dfa694d3d
Author: Eric Auger <address@hidden>
Date: 2017-10-31 (Tue, 31 Oct 2017)
Changed paths:
M hw/pci-host/gpex.c
Log Message:
-----------
hw/pci-host/gpex: Improve INTX to gsi routing error checking
We exposed gpex_set_irq_num() for machines to set the INTx to
GSI routing. However if the machine forgets to call that
function we currently do not check the association was properly
done. Let's initialize gsi values to -1 and if this value is
found in gpex_route_intx_pin_to_irq, set the routing mode as
disabled.
Signed-off-by: Eric Auger <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7fa00e204902cee0b33a0c60de87e87319d1809f
https://github.com/qemu/qemu/commit/7fa00e204902cee0b33a0c60de87e87319d1809f
Author: Peter Maydell <address@hidden>
Date: 2017-10-31 (Tue, 31 Oct 2017)
Changed paths:
M hw/arm/msf2-soc.c
M hw/arm/xlnx-zcu102.c
M hw/pci-host/gpex.c
M hw/ssi/mss-spi.c
M target/arm/helper.h
M target/arm/internals.h
M target/arm/op_helper.c
M target/arm/psci.c
M target/arm/translate-a64.c
M target/arm/translate.c
Log Message:
-----------
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20171031'
into staging
target-arm queue:
* fix instruction-length bit in syndrome for WFI/WFE traps
* xlnx-zcu102: Specify the max number of CPUs
* msf2: Remove dead code reported by Coverity
* msf2: Wire up SYSRESETREQ in SoC for system reset
* hw/pci-host/gpex: Improve INTX to gsi routing error checking
# gpg: Signature made Tue 31 Oct 2017 13:10:02 GMT
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20171031:
hw/pci-host/gpex: Improve INTX to gsi routing error checking
msf2: Wire up SYSRESETREQ in SoC for system reset
msf2: Remove dead code reported by Coverity
xlnx-zcu102: Specify the max number of CPUs
fix WFI/WFE length in syndrome register
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/92c7ec5cd4d1...7fa00e204902
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