[Qemu-commits] [qemu/qemu] 0ca9fa: openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC)

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 0ca9fa2e3c2d072ef7546190976e326ff2673a33
      
https://github.com/qemu/qemu/commit/0ca9fa2e3c2d072ef7546190976e326ff2673a33
  Author: Stafford Horne <address@hidden>
  Date:   2017-10-21 (Sat, 21 Oct 2017)

  Changed paths:
    M default-configs/or1k-softmmu.mak
    M hw/intc/Makefile.objs
    A hw/intc/ompic.c

  Log Message:
  -----------
  openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC)

Add OpenRISC Multicore PIC which handles inter processor interrupts
(IPI) between cores.  In OpenRISC all device interrupts are routed to
each core enabling this device to be simple.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: 8c949951ed257567303c3d3b83bcd876b53d79e5
      
https://github.com/qemu/qemu/commit/8c949951ed257567303c3d3b83bcd876b53d79e5
  Author: Stafford Horne <address@hidden>
  Date:   2017-10-21 (Sat, 21 Oct 2017)

  Changed paths:
    M target/openrisc/sys_helper.c

  Log Message:
  -----------
  target/openrisc: Make coreid and numcores variable

Previously coreid and numcores were hard coded as 0 and 1 respectively
as OpenRISC QEMU did not have multicore support.

Multicore support is now being added so these registers need to have
configured values.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: 6b4bbd6aeb8e187c0e3be58c8f77a484f82e6f87
      
https://github.com/qemu/qemu/commit/6b4bbd6aeb8e187c0e3be58c8f77a484f82e6f87
  Author: Stafford Horne <address@hidden>
  Date:   2017-10-21 (Sat, 21 Oct 2017)

  Changed paths:
    M hw/openrisc/cputimer.c
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h
    M target/openrisc/machine.c
    M target/openrisc/sys_helper.c

  Log Message:
  -----------
  openrisc/cputimer: Perparation for Multicore

In order to support multicore system we move some of the previously
static state variables into the state of each core.

On the other hand in order to allow timers to be synced between each
code the ttcr (tick timer count register) is moved out of the core.
This is not as per real hardware spec which has a separate timer counter
per core, but it seems the most simple way to keep each clock in sync.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: 13f1c773640171efa8175b1ba6dcd624c1ad68c1
      
https://github.com/qemu/qemu/commit/13f1c773640171efa8175b1ba6dcd624c1ad68c1
  Author: Stafford Horne <address@hidden>
  Date:   2017-10-21 (Sat, 21 Oct 2017)

  Changed paths:
    M hw/openrisc/openrisc_sim.c

  Log Message:
  -----------
  openrisc: Initial SMP support

Wire in ompic and add basic support for SMP.  The OpenRISC is special in
that interrupts for devices are routed to each core's PIC.  This is
achieved using the qemu_irq_split utility, but this currently limits
OpenRISC to 2 cores.

This models the reference architecture described in the OpenRISC spec
1.2 proposal.

  
https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf

The changes to the intialization of the sim include:

CPU Reset
 o Reset each cpu to the bootstrap PC rather than only a single cpu as
   done before.
 o During Kernel loading the bootstrap PC is saved in a static global.

Network Initialization
 o Connect the interrupt to each CPU
 o Use more simple sysbus_mmio_map() rather than memory_region_add_subregion()

Sim Initialization
 o Initialize the pic and tick timer per cpu
 o Wire in the OMPIC if SMP is enabled
 o Wire the serial irq to each CPU using qemu_irq_split()

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: 373b259b660a8ff0960a979481c19b78d51e023a
      
https://github.com/qemu/qemu/commit/373b259b660a8ff0960a979481c19b78d51e023a
  Author: Stafford Horne <address@hidden>
  Date:   2017-10-21 (Sat, 21 Oct 2017)

  Changed paths:
    M hw/openrisc/cputimer.c

  Log Message:
  -----------
  openrisc: Only kick cpu on timeout, not on update

Previously we were kicking the cpu on every update.  This caused
problems noticeable in SMP configurations where one CPU got pinned
continuously servicing timer exceptions.

Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>


  Commit: a61837da0f2122e01685f6b7aad3226c9a6fc289
      
https://github.com/qemu/qemu/commit/a61837da0f2122e01685f6b7aad3226c9a6fc289
  Author: Peter Maydell <address@hidden>
  Date:   2017-10-24 (Tue, 24 Oct 2017)

  Changed paths:
    M default-configs/or1k-softmmu.mak
    M hw/intc/Makefile.objs
    A hw/intc/ompic.c
    M hw/openrisc/cputimer.c
    M hw/openrisc/openrisc_sim.c
    M target/openrisc/cpu.c
    M target/openrisc/cpu.h
    M target/openrisc/machine.c
    M target/openrisc/sys_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/shorne/tags/openrisc-20171021-smp-pr' 
into staging

OpenRISC SMP patchset 20171021

# gpg: Signature made Fri 20 Oct 2017 22:51:16 BST
# gpg:                using RSA key 0xC3B31C2D5E6627E4
# gpg: Good signature from "Stafford Horne <address@hidden>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25  EFF1 C3B3 1C2D 5E66 27E4

* remotes/shorne/tags/openrisc-20171021-smp-pr:
  openrisc: Only kick cpu on timeout, not on update
  openrisc: Initial SMP support
  openrisc/cputimer: Perparation for Multicore
  target/openrisc: Make coreid and numcores variable
  openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC)

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/e822e81e3508...a61837da0f21