[Qemu-commits] [qemu/qemu] 4a1672: target/arm: Use M_REG_NUM_BANKS rather than hardco...

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 4a16724f06ead684a5962477a557c26c677c2729
      
https://github.com/qemu/qemu/commit/4a16724f06ead684a5962477a557c26c677c2729
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-14 (Thu, 14 Sep 2017)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2

Use a symbolic constant M_REG_NUM_BANKS for the array size for
registers which are banked by M profile security state, rather
than hardcoding lots of 2s.

Suggested-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden


  Commit: dc3c4c14f0f12854dbd967be3486f4db4e66d25b
      
https://github.com/qemu/qemu/commit/dc3c4c14f0f12854dbd967be3486f4db4e66d25b
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-14 (Thu, 14 Sep 2017)

  Changed paths:
    M target/arm/cpu.c
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/op_helper.c

  Log Message:
  -----------
  target/arm: Clear exclusive monitor on v7M reset, exception entry/exit

For M profile we must clear the exclusive monitor on reset, exception
entry and exception exit.  We weren't doing any of these things; fix
this bug.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: c6158878650c01b2c753b2ea7d0967c8fe5ca59e
      
https://github.com/qemu/qemu/commit/c6158878650c01b2c753b2ea7d0967c8fe5ca59e
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-14 (Thu, 14 Sep 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Get PRECISERR and IBUSERR the right way round

For a bus fault, the M profile BFSR bit PRECISERR means a bus
fault on a data access, and IBUSERR means a bus fault on an
instruction access. We had these the wrong way around; fix this.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 22a9c26af62f9772b7c0512e88f97d0d1f2e0872
      
https://github.com/qemu/qemu/commit/22a9c26af62f9772b7c0512e88f97d0d1f2e0872
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-14 (Thu, 14 Sep 2017)

  Changed paths:
    M hw/intc/armv7m_nvic.c

  Log Message:
  -----------
  nvic: Don't apply group priority mask to negative priorities

In several places we were unconditionally applying the
nvic_gprio_mask() to a priority value. This is incorrect
if the priority is one of the fixed negative priority
values (for NMI and HardFault), so don't do it.

This bug would have caused both NMI and HardFault to be
considered as the same priority and so NMI wouldn't
correctly preempt HardFault.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: 7115cdf5782922611bcc44c89eec5990db7f6466
      
https://github.com/qemu/qemu/commit/7115cdf5782922611bcc44c89eec5990db7f6466
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-14 (Thu, 14 Sep 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit()

In do_v7m_exception_exit(), there's no need to force the high 4
bits of 'type' to 1 when calling v7m_exception_taken(), because
we know that they're always 1 or we could not have got to this
"handle return to magic exception return address" code. Remove
the unnecessary ORs.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Message-id: address@hidden


  Commit: 4d1e7a4745c050f7ccac49a1c01437526b5130b5
      
https://github.com/qemu/qemu/commit/4d1e7a4745c050f7ccac49a1c01437526b5130b5
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-14 (Thu, 14 Sep 2017)

  Changed paths:
    M target/arm/helper.c
    M target/arm/internals.h

  Log Message:
  -----------
  target/arm: Add and use defines for EXCRET constants

The exception-return magic values get some new bits in v8M, which
makes some bit definitions for them worthwhile.

We don't use the bit definitions for the switch on the low bits
which checks the return type for v7M, because this is defined
in the v7M ARM ARM as a set of valid values rather than via
per-bit checks.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden


  Commit: 351e527a613147aa2a2e6910f92923deef27ee48
      
https://github.com/qemu/qemu/commit/351e527a613147aa2a2e6910f92923deef27ee48
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-14 (Thu, 14 Sep 2017)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit()

In the v7M and v8M ARM ARM, the magic exception return values are
referred to as EXC_RETURN values, and in QEMU we use V7M_EXCRET_*
constants to define bits within them. Rename the 'type' variable
which holds the exception return value in do_v7m_exception_exit()
to excret, making it clearer that it does hold an EXC_RETURN value.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden


  Commit: aff3f0f150769ec4f97c6e2cefe91c4a0377b548
      
https://github.com/qemu/qemu/commit/aff3f0f150769ec4f97c6e2cefe91c4a0377b548
  Author: Alistair Francis <address@hidden>
  Date:   2017-09-14 (Thu, 14 Sep 2017)

  Changed paths:
    M hw/arm/Makefile.objs
    R hw/arm/xlnx-ep108.c
    A hw/arm/xlnx-zcu102.c

  Log Message:
  -----------
  xlnx-ep108: Rename to ZCU102

The EP108 is a early access development board. Now that silicon is in
production people have access to the ZCU102. Let's rename the internal
QEMU files and variables to use the ZCU102.

There is no functional change here as the EP108 is still a valid board
option.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b70cf33f030e0fc965b3a02d91c2195e0572ea46
      
https://github.com/qemu/qemu/commit/b70cf33f030e0fc965b3a02d91c2195e0572ea46
  Author: Alistair Francis <address@hidden>
  Date:   2017-09-14 (Thu, 14 Sep 2017)

  Changed paths:
    M hw/arm/xlnx-zcu102.c

  Log Message:
  -----------
  xlnx-zcu102: Manually create the machines

In preperation for future work let's manually create the Xilnx machines.
This will allow us to set properties for the machines in the future.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b7436e94ded250b92aaa03bd72eab2279aba197b
      
https://github.com/qemu/qemu/commit/b7436e94ded250b92aaa03bd72eab2279aba197b
  Author: Alistair Francis <address@hidden>
  Date:   2017-09-14 (Thu, 14 Sep 2017)

  Changed paths:
    M hw/arm/xlnx-zcu102.c

  Log Message:
  -----------
  xlnx-zcu102: Add a machine level secure property

Add a machine level secure property. This defaults to false and can be
set to true using this machine command line argument:
    -machine xlnx-zcu102,secure=on

This follows what the ARM virt machine does.

This property only applies to the ZCU102 machine. The EP108 machine does
not have this property.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 1946809ece906d517e96fdcb0b39c5e63916fb5a
      
https://github.com/qemu/qemu/commit/1946809ece906d517e96fdcb0b39c5e63916fb5a
  Author: Alistair Francis <address@hidden>
  Date:   2017-09-14 (Thu, 14 Sep 2017)

  Changed paths:
    M hw/arm/xlnx-zcu102.c
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  xlnx-zcu102: Add a machine level virtualization property

Add a machine level virtualization property. This defaults to false and can be
set to true using this machine command line argument:
    -machine xlnx-zcu102,virtualization=on

This follows what the ARM virt machine does.

This property only applies to the ZCU102 machine. The EP108 machine does
not have this property.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: da69de00763c1bc221149f6618ef2c8f81e9f49a
      
https://github.com/qemu/qemu/commit/da69de00763c1bc221149f6618ef2c8f81e9f49a
  Author: Alistair Francis <address@hidden>
  Date:   2017-09-14 (Thu, 14 Sep 2017)

  Changed paths:
    M hw/arm/xlnx-zcu102.c

  Log Message:
  -----------
  xlnx-zcu102: Mark the EP108 machine as deprecated

The EP108 is the same as the ZCU102, mark it as deprecated as we don't
need two machines.

Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: dddbba9943ef6a81c8702e4a50cb0a8b1a4201fe
      
https://github.com/qemu/qemu/commit/dddbba9943ef6a81c8702e4a50cb0a8b1a4201fe
  Author: Jaroslaw Pelczar <address@hidden>
  Date:   2017-09-14 (Thu, 14 Sep 2017)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  AArch64: Fix single stepping of ERET instruction

Previously when single stepping through ERET instruction via GDB
would result in debugger entering the "next" PC after ERET instruction.
When debugging in kernel mode, this will also cause unintended behavior,
because debugger will try to access memory from EL0 point of view.

Signed-off-by: Jaroslaw Pelczar <address@hidden>
Message-id: address@hidden
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 37e29a64254bf82a1901784fcca17c25f8164c2f
      
https://github.com/qemu/qemu/commit/37e29a64254bf82a1901784fcca17c25f8164c2f
  Author: Richard Henderson <address@hidden>
  Date:   2017-09-14 (Thu, 14 Sep 2017)

  Changed paths:
    M target/arm/translate-a64.c

  Log Message:
  -----------
  target/arm: Avoid an extra temporary for store_exclusive

Instead of copying addr to a local temp, reuse the value (which we
have just compared as equal) already saved in cpu_exclusive_addr.

Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 70bfdce6a1263fd06144ecc1c3727c44e562d89b
      
https://github.com/qemu/qemu/commit/70bfdce6a1263fd06144ecc1c3727c44e562d89b
  Author: Pranavkumar Sawargaonkar <address@hidden>
  Date:   2017-09-14 (Thu, 14 Sep 2017)

  Changed paths:
    M hw/pci-host/gpex.c
    M include/hw/pci-host/gpex.h

  Log Message:
  -----------
  hw/pci-host/gpex: Set INTx index/gsi mapping

To implement INTx to gsi routing we need to pass the gpex host
bridge the gsi associated to each INTx index. Let's introduce
irq_num array and gpex_set_irq_num setter function.

Signed-off-by: Pranavkumar Sawargaonkar <address@hidden>
Signed-off-by: Tushar Jagad <address@hidden>
Signed-off-by: Eric Auger <address@hidden>
Tested-by: Feng Kan <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: c9bb8e16080d189a0c393a1061b427993516ae2b
      
https://github.com/qemu/qemu/commit/c9bb8e16080d189a0c393a1061b427993516ae2b
  Author: Pranavkumar Sawargaonkar <address@hidden>
  Date:   2017-09-14 (Thu, 14 Sep 2017)

  Changed paths:
    M hw/arm/virt.c

  Log Message:
  -----------
  hw/arm/virt: Set INTx/gsi mapping

Let's provide the GPEX host bridge with the INTx/gsi mapping. This is
needed for INTx/gsi routing.

Signed-off-by: Pranavkumar Sawargaonkar <address@hidden>
Signed-off-by: Tushar Jagad <address@hidden>
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Tested-by: Feng Kan <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: d464814ae729f3200234ff74d5f050ddad4f1f20
      
https://github.com/qemu/qemu/commit/d464814ae729f3200234ff74d5f050ddad4f1f20
  Author: Pranavkumar Sawargaonkar <address@hidden>
  Date:   2017-09-14 (Thu, 14 Sep 2017)

  Changed paths:
    M hw/pci-host/gpex.c

  Log Message:
  -----------
  hw/pci-host/gpex: Implement PCI INTx routing

Now we are able to retrieve the gsi from the INTx pin, let's
enable intx_to_irq routing. From that point on, irqfd becomes
usable along with INTx when assigning a PCIe device.

Signed-off-by: Pranavkumar Sawargaonkar <address@hidden>
Signed-off-by: Tushar Jagad <address@hidden>
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Tested-by: Feng Kan <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: ce3bc112cdb1d462e2d52eaa17a7314e7f3af504
      
https://github.com/qemu/qemu/commit/ce3bc112cdb1d462e2d52eaa17a7314e7f3af504
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-14 (Thu, 14 Sep 2017)

  Changed paths:
    M hw/arm/mps2.c

  Log Message:
  -----------
  mps2-an511: Fix wiring of UART overflow interrupt lines

Fix an error that meant we were wiring every UART's overflow
interrupts into the same inputs 0 and 1 of the OR gate,
rather than giving each its own input.

Cc: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden


  Commit: d28e29a92585e94264628b1b27262fe2d7573f51
      
https://github.com/qemu/qemu/commit/d28e29a92585e94264628b1b27262fe2d7573f51
  Author: Peter Maydell <address@hidden>
  Date:   2017-09-14 (Thu, 14 Sep 2017)

  Changed paths:
    M hw/arm/Makefile.objs
    M hw/arm/mps2.c
    M hw/arm/virt.c
    R hw/arm/xlnx-ep108.c
    A hw/arm/xlnx-zcu102.c
    M hw/arm/xlnx-zynqmp.c
    M hw/intc/armv7m_nvic.c
    M hw/pci-host/gpex.c
    M include/hw/arm/xlnx-zynqmp.h
    M include/hw/pci-host/gpex.h
    M target/arm/cpu.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/op_helper.c
    M target/arm/translate-a64.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170914' 
into staging

target-arm queue:
 * v7M: various code cleanups
 * v7M: set correct BFSR bits on bus fault
 * v7M: clear exclusive monitor on reset and exception entry/exit
 * v7M: don't apply priority mask to negative priorities
 * zcu102: support 'secure' and 'virtualization' machine properties
 * aarch64: fix ERET single stepping
 * gpex: implement PCI INTx routing
 * mps2-an511: fix UART overflow interrupt line wiring

# gpg: Signature made Thu 14 Sep 2017 18:50:48 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170914:
  mps2-an511: Fix wiring of UART overflow interrupt lines
  hw/pci-host/gpex: Implement PCI INTx routing
  hw/arm/virt: Set INTx/gsi mapping
  hw/pci-host/gpex: Set INTx index/gsi mapping
  target/arm: Avoid an extra temporary for store_exclusive
  AArch64: Fix single stepping of ERET instruction
  xlnx-zcu102: Mark the EP108 machine as deprecated
  xlnx-zcu102: Add a machine level virtualization property
  xlnx-zcu102: Add a machine level secure property
  xlnx-zcu102: Manually create the machines
  xlnx-ep108: Rename to ZCU102
  target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit()
  target/arm: Add and use defines for EXCRET constants
  target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit()
  nvic: Don't apply group priority mask to negative priorities
  target/arm: Get PRECISERR and IBUSERR the right way round
  target/arm: Clear exclusive monitor on v7M reset, exception entry/exit
  target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/3dabde1128b6...d28e29a92585