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[Qemu-commits] [qemu/qemu] 03ae85: target/arm: Use MMUAccessType enum ra
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[Qemu-commits] [qemu/qemu] 03ae85: target/arm: Use MMUAccessType enum rather than int |
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Date: |
Mon, 04 Sep 2017 10:27:39 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 03ae85f858fc46495258a5dd4551fff2c34bd495
https://github.com/qemu/qemu/commit/03ae85f858fc46495258a5dd4551fff2c34bd495
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Use MMUAccessType enum rather than int
In the ARM get_phys_addr() code, switch to using the MMUAccessType
enum and its MMU_* values rather than int and literal 0/1/2.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 0e2845689ebdb4ea7174f96f6797e2d8942bd114
https://github.com/qemu/qemu/commit/0e2845689ebdb4ea7174f96f6797e2d8942bd114
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M target/arm/op_helper.c
Log Message:
-----------
target/arm: Don't trap WFI/WFE for M profile
M profile cores can never trap on WFI or WFE instructions. Check for
M profile in check_wfx_trap() to ensure this.
The existing code will do the right thing for v7M cores because
the hcr_el2 and scr_el3 registers will be all-zeroes and so we
won't attempt to trap, but when we start setting ARM_FEATURE_V8
for v8M cores the v8A handling of SCTLR.nTWE and .nTWI will not
give the right results.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 3279adb95e34dd3d67c66d729458f7784747cf8d
https://github.com/qemu/qemu/commit/3279adb95e34dd3d67c66d729458f7784747cf8d
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Consolidate PMSA handling in get_phys_addr()
Currently get_phys_addr() has PMSAv7 handling before the
"is translation disabled?" check, and then PMSAv5 after it.
Tidy this up by making the PMSAv5 code handle the "MPU disabled"
case itself, so that we have all the PMSA code in one place.
This will make adding the PMSAv8 code slightly cleaner, and
also means that pre-v7 PMSA cores benefit from the MPU lookup
logging that the PMSAv7 codepath had.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: ebfe27c593e5b222aa2a1fc545b447be3d995faa
https://github.com/qemu/qemu/commit/ebfe27c593e5b222aa2a1fc545b447be3d995faa
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Tighten up Thumb decode where new v8M insns will be
Tighten up the T32 decoder in the places where new v8M instructions
will be:
* TT/TTT/TTA/TTAT are in what was nominally LDREX/STREX r15, ...
which is UNPREDICTABLE:
make the UNPREDICTABLE behaviour be to UNDEF
* BXNS/BLXNS are distinguished from BX/BLX via the low 3 bits,
which in previous architectural versions are SBZ:
enforce the SBZ via UNDEF rather than ignoring it, and move
the "ARCH(5)" UNDEF case up so we don't leak a TCG temporary
* SG is in the encoding which would be LDRD/STRD with rn = r15;
this is UNPREDICTABLE and we currently UNDEF:
move this check further up the code so that we don't leak
TCG temporaries in the UNDEF case and have a better place
to put the SG decode.
This means that if a v8M binary is accidentally run on v7M
or if a test case hits something that we haven't implemented
yet the behaviour will be obvious (UNDEF) rather than obscure
(plough on treating it as a different instruction).
In the process, add some comments about the instruction patterns
at these points in the decode. Our Thumb and ARM decoders are
very difficult to understand currently, but gradually adding
comments like this should help to clarify what exactly has
been decoded when.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 79c857a35f3e829d0baac23a355a1365714d2a1a
https://github.com/qemu/qemu/commit/79c857a35f3e829d0baac23a355a1365714d2a1a
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
Log Message:
-----------
hw/intc/armv7m_nvic.c: Remove out of date comment
Remove an out of date comment which says there's only one
item in the NVIC container region -- we put systick into its
own device object a while back and so now there are two
things in the container.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 59e4972c3fc63d981e8b613ebb3bb01a05848075
https://github.com/qemu/qemu/commit/59e4972c3fc63d981e8b613ebb3bb01a05848075
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M target/arm/cpu.h
Log Message:
-----------
target/arm: Remove incorrect comment about MPU_CTRL
Remove the comment that claims that some MPU_CTRL bits are stored
in sctlr_el[1]. This has never been true since MPU_CTRL was added
in commit 29c483a50607 -- the comment is a leftover from
Michael Davidsaver's original implementation, which I modified
not to use sctlr_el[1]; I forgot to delete the comment then.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 9d17da4b68a05fc78daa47f0f3d914eea5d802ea
https://github.com/qemu/qemu/commit/9d17da4b68a05fc78daa47f0f3d914eea5d802ea
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Fix outdated comment about exception exit
When we switched our handling of exception exit to detect
the magic addresses at translate time rather than via
a do_unassigned_access hook, we forgot to update a
comment; correct the omission.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 987ab45e108953c1c98126c338c2119c243c372b
https://github.com/qemu/qemu/commit/987ab45e108953c1c98126c338c2119c243c372b
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Define and use XPSR bit masks
The M profile XPSR is almost the same format as the A profile CPSR,
but not quite. Define some XPSR_* macros and use them where we
definitely dealing with an XPSR rather than reusing the CPSR ones.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: e6ae5981ea4b0f6feb223009a5108582e7644f8f
https://github.com/qemu/qemu/commit/e6ae5981ea4b0f6feb223009a5108582e7644f8f
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/machine.c
Log Message:
-----------
target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
We currently store the M profile CPU register state PRIMASK and
FAULTMASK in the daif field of the CPU state in its I and F
bits. This is a legacy from the original implementation, which
tried to share the cpu_exec_interrupt code between A profile
and M profile. We've since separated out the two cases because
they are significantly different, so now there is no common
code between M and A profile which looks at env->daif: all the
uses are either in A-only or M-only code paths. Sharing the state
fields now is just confusing, and will make things awkward
when we implement v8M, where the PRIMASK and FAULTMASK
registers are banked between security states.
Switch M profile over to using v7m.faultmask and v7m.primask
fields for these registers.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: eeade0017698ada9d3049ec9021d094d96304f58
https://github.com/qemu/qemu/commit/eeade0017698ada9d3049ec9021d094d96304f58
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M target/arm/machine.c
Log Message:
-----------
target/arm: Don't use cpsr_write/cpsr_read to transfer M profile XPSR
For M profile the XPSR is a similar but not identical format to the
A profile CPSR/SPSR. (For instance the Thumb bit is in a different
place.) For guest accesses we make the M profile code go through
xpsr_read() and xpsr_write() which handle the different layout.
However for migration we use cpsr_read() and cpsr_write() to
marshal state into and out of the migration data stream. This
is pretty confusing and works more by luck than anything else.
Make M profile migration use xpsr_read() and xpsr_write() instead.
The most complicated part of this is handling the possibility
that the migration source is an older QEMU which hands us a
CPSR format value; helpfully we can always tell the two apart.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 5b906f3589443a3c69d8feeaac37263843ecfb8d
https://github.com/qemu/qemu/commit/5b906f3589443a3c69d8feeaac37263843ecfb8d
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M target/arm/translate.c
Log Message:
-----------
target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR
Make the arm_cpu_dump_state() debug logging handle the M-profile XPSR
rather than assuming it's an A-profile CPSR. On M profile the PSR
line of a register dump will now look like this:
XPSR=41000000 -Z-- T priv-thread
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: bd70b29ba92e4446f9e4eb8b9acc19ef6ff4a4d5
https://github.com/qemu/qemu/commit/bd70b29ba92e4446f9e4eb8b9acc19ef6ff4a4d5
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed
Move the code in arm_v7m_cpu_do_interrupt() that calculates the
magic LR value down to when we're actually going to use it.
Having the calculation and use so far apart makes the code
a little harder to understand than it needs to be.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: 15b3f556bab4f961bf92141eb8521c8da3df5eb2
https://github.com/qemu/qemu/commit/15b3f556bab4f961bf92141eb8521c8da3df5eb2
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Create and use new function arm_v7m_is_handler_mode()
Add a utility function for testing whether the CPU is in Handler
mode; this is just a check whether v7m.exception is non-zero, but
we do it in several places and it makes the code a bit easier
to read to not have to mentally figure out what the test is testing.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: d2db1de6ff15aad4c8898a416c6d8f2d93ff0282
https://github.com/qemu/qemu/commit/d2db1de6ff15aad4c8898a416c6d8f2d93ff0282
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
M include/hw/arm/armv7m.h
R include/hw/arm/armv7m_nvic.h
A include/hw/intc/armv7m_nvic.h
Log Message:
-----------
armv7m_nvic.h: Move from include/hw/arm to include/hw/intc
The armv7m_nvic.h header file was accidentally placed in
include/hw/arm; move it to include/hw/intc to match where
its corresponding .c file lives.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: eb578a2394c55f7d598f60796c8318e40b1c0241
https://github.com/qemu/qemu/commit/eb578a2394c55f7d598f60796c8318e40b1c0241
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hw/intc/armv7m_nvic.c
Log Message:
-----------
nvic: Implement "user accesses BusFault" SCS region behaviour
The ARMv7M architecture specifies that most of the addresses in the
PPB region (which includes the NVIC, systick and system registers)
are not accessible to unprivileged accesses, which should
BusFault with a few exceptions:
* the STIR is configurably user-accessible
* the ITM (which we don't implement at all) is always
user-accessible
Implement this by switching the register access functions
to the _with_attrs scheme that lets us distinguish user
mode accesses.
This allows us to pull the handling of the CCR.USERSETMPEND
flag up to the level where we can make it generate a BusFault
as it should for non-permitted accesses.
Note that until the core ARM CPU code implements turning
MEMTX_ERROR into a BusFault the registers will continue to
act as RAZ/WI to user accesses.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: bf1733392ca22f593cac77534f88ee6d6810837e
https://github.com/qemu/qemu/commit/bf1733392ca22f593cac77534f88ee6d6810837e
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M include/hw/elf_ops.h
Log Message:
-----------
loader: Handle ELF files with overlapping zero-initialized data
For embedded systems, notably ARM, one common use of ELF
file segments is that the 'physical addresses' represent load addresses
and the 'virtual addresses' execution addresses, such that
the load addresses are packed into ROM or flash, and the
relocation and zero-initialization of data is done at runtime.
This means that the 'memsz' in the segment header represents
the runtime size of the segment, but the size that needs to
be loaded is only the 'filesz'. In particular, paddr+memsz
may overlap with the next segment to be loaded, as in this
example:
0x70000001 off 0x00007f68 vaddr 0x00008150 paddr 0x00008150 align 2**2
filesz 0x00000008 memsz 0x00000008 flags r--
LOAD off 0x000000f4 vaddr 0x00000000 paddr 0x00000000 align 2**2
filesz 0x00000124 memsz 0x00000124 flags r--
LOAD off 0x00000218 vaddr 0x00000400 paddr 0x00000400 align 2**3
filesz 0x00007d58 memsz 0x00007d58 flags r-x
LOAD off 0x00007f70 vaddr 0x20000140 paddr 0x00008158 align 2**3
filesz 0x00000a80 memsz 0x000022f8 flags rw-
LOAD off 0x000089f0 vaddr 0x20002438 paddr 0x00008bd8 align 2**0
filesz 0x00000000 memsz 0x00004000 flags rw-
LOAD off 0x000089f0 vaddr 0x20000000 paddr 0x20000000 align 2**0
filesz 0x00000000 memsz 0x00000140 flags rw-
where the segment at paddr 0x8158 has a memsz of 0x2258 and
would overlap with the segment at paddr 0x8bd8 if QEMU's loader
tried to honour it. (At runtime the segments will not overlap
since their vaddrs are more widely spaced than their paddrs.)
Currently if you try to load an ELF file like this with QEMU then
it will fail with an error "rom: requested regions overlap",
because we create a ROM image for each segment using the memsz
as the size.
Support ELF files using this scheme, by truncating the
zero-initialized part of the segment if it would overlap another
segment. This will retain the existing loader behaviour for
all ELF files we currently accept, and also accept ELF files
which only need 'filesz' bytes to be loaded.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Commit: f33e5e6299288c945380e3ce3ea9d2406277c289
https://github.com/qemu/qemu/commit/f33e5e6299288c945380e3ce3ea9d2406277c289
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M include/hw/elf_ops.h
Log Message:
-----------
loader: Ignore zero-sized ELF segments
Some ELF files have program headers that specify segments that
are of zero size. Ignore them, rather than trying to create
zero-length ROM blobs for them, because the zero-length blob
can falsely trigger the overlapping-ROM-blobs check.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Tested-by: Hua Yanghao <address@hidden>
Message-id: address@hidden
Commit: c2de81e2b24dd62876b919da2dd4714cadad34d5
https://github.com/qemu/qemu/commit/c2de81e2b24dd62876b919da2dd4714cadad34d5
Author: Philippe Mathieu-Daudé <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hw/arm/armv7m.c
M hw/arm/exynos4210.c
M hw/arm/highbank.c
M hw/arm/realview.c
M hw/arm/vexpress.c
M hw/arm/xilinx_zynq.c
Log Message:
-----------
hw/arm: use defined type name instead of hard-coded string
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 07f48730bc4ec99f128901705336eb455f674694
https://github.com/qemu/qemu/commit/07f48730bc4ec99f128901705336eb455f674694
Author: Andrew Jones <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hw/arm/virt.c
M target/arm/cpu.c
M target/arm/cpu.h
Log Message:
-----------
hw/arm/virt: add pmu interrupt state
Mimicking gicv3-maintenance-interrupt, add the PMU's interrupt to
CPU state.
Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: 3f07cb2aabdfcc27ee30cf85c39619a82d364f83
https://github.com/qemu/qemu/commit/3f07cb2aabdfcc27ee30cf85c39619a82d364f83
Author: Andrew Jones <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hw/arm/virt.c
M target/arm/kvm32.c
M target/arm/kvm64.c
M target/arm/kvm_arm.h
Log Message:
-----------
target/arm/kvm: pmu: split init and set-irq stages
When adding a PMU with a userspace irqchip we skip the set-irq
stage of device creation. Split the 'create' function into two
functions 'init' and 'set-irq' so they may be called separately.
Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Christoffer Dall <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
Commit: b16595275bc9b9ce6a36bfb0344d514ab77e6b98
https://github.com/qemu/qemu/commit/b16595275bc9b9ce6a36bfb0344d514ab77e6b98
Author: Andrew Jones <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hw/arm/virt.c
M target/arm/kvm.c
M target/arm/kvm64.c
Log Message:
-----------
hw/arm/virt: allow pmu instantiation with userspace irqchip
Move the in-kernel-irqchip test to only guard the set-irq
stage, not the init stage of the PMU. Also add the PMU to
the KVM device irq line synchronization to enable its use.
Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Christoffer Dall <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: b2bfe9f7f1f7e3aa5edf9c3c4c7408082778ae17
https://github.com/qemu/qemu/commit/b2bfe9f7f1f7e3aa5edf9c3c4c7408082778ae17
Author: Andrew Jones <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hw/arm/virt.c
M target/arm/kvm32.c
M target/arm/kvm64.c
M target/arm/kvm_arm.h
Log Message:
-----------
target/arm/kvm: pmu: improve error handling
If a KVM PMU init or set-irq attr call fails we just silently stop
the PMU DT node generation. The only way they could fail, though,
is if the attr's respective KVM has-attr call fails. But that should
never happen if KVM advertises the PMU capability, because both
attrs have been available since the capability was introduced. Let's
just abort if this should-never-happen stuff does happen, because,
if it does, then something is obviously horribly wrong.
Signed-off-by: Andrew Jones <address@hidden>
Reviewed-by: Christoffer Dall <address@hidden>
Message-id: address@hidden
[PMM: change kvm32.c kvm_arm_pmu_init() to the new API too]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: f55d613bc97cd8d08487eddec313c3298a906a91
https://github.com/qemu/qemu/commit/f55d613bc97cd8d08487eddec313c3298a906a91
Author: Andrew Jeffery <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hw/watchdog/wdt_aspeed.c
M include/hw/watchdog/wdt_aspeed.h
Log Message:
-----------
watchdog: wdt_aspeed: Add support for the reset width register
The reset width register controls how the pulse on the SoC's WDTRST{1,2}
pins behaves. A pulse is emitted if the external reset bit is set in
WDT_CTRL. On the AST2500 WDT_RESET_WIDTH can consume magic bit patterns
to configure push-pull/open-drain and active-high/active-low
behaviours and thus needs some special handling in the write path.
As some of the capabilities depend on the SoC version a silicon-rev
property is introduced, which is used to guard version-specific
behaviour.
Signed-off-by: Andrew Jeffery <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 429789cc772514971e3d1190d1553f514054dd5c
https://github.com/qemu/qemu/commit/429789cc772514971e3d1190d1553f514054dd5c
Author: Andrew Jeffery <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hw/arm/aspeed_soc.c
Log Message:
-----------
aspeed_soc: Propagate silicon-rev to watchdog
This is required to configure differences in behaviour between the
AST2400 and AST2500 watchdog IPs.
Signed-off-by: Andrew Jeffery <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 3114d092b1740f9db9aa559aeb48ee387011e1da
https://github.com/qemu/qemu/commit/3114d092b1740f9db9aa559aeb48ee387011e1da
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M include/exec/memattrs.h
M include/exec/memory.h
Log Message:
-----------
memory.h: Move MemTxResult type to memattrs.h
Move the MemTxResult type to memattrs.h. We're going to want to
use it in cpu/qom.h, which doesn't want to include all of
memory.h. In practice MemTxResult and MemTxAttrs are pretty
closely linked since both are used for the new-style
read_with_attrs and write_with_attrs callbacks, so memattrs.h
is a reasonable home for this rather than creating a whole
new header file for it.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Commit: 0dff0939f6fc6a7abd966d4295f06a06d7a01df9
https://github.com/qemu/qemu/commit/0dff0939f6fc6a7abd966d4295f06a06d7a01df9
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M include/qom/cpu.h
Log Message:
-----------
cpu: Define new cpu_transaction_failed() hook
Currently we have a rather half-baked setup for allowing CPUs to
generate exceptions on accesses to invalid memory: the CPU has a
cpu_unassigned_access() hook which the memory system calls in
unassigned_mem_write() and unassigned_mem_read() if the current_cpu
pointer is non-NULL. This was originally designed before we
implemented the MemTxResult type that allows memory operations to
report a success or failure code, which is why the hook is called
right at the bottom of the memory system. The major problem with
this is that it means that the hook can be called even when the
access was not actually done by the CPU: for instance if the CPU
writes to a DMA engine register which causes the DMA engine to begin
a transaction which has been set up by the guest to operate on
invalid memory then this will casue the CPU to take an exception
incorrectly. Another minor problem is that currently if a device
returns a transaction error then this won't turn into a CPU exception
at all.
The right way to do this is to have allow the CPU to respond
to memory system transaction failures at the point where the
CPU specific code calls into the memory system.
Define a new QOM CPU method and utility function
cpu_transaction_failed() which is called in these cases.
The functionality here overlaps with the existing
cpu_unassigned_access() because individual target CPUs will
need some work to convert them to the new system. When this
transition is complete we can remove the old cpu_unassigned_access()
code.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Commit: 04e3aabde397e7abc78ba1ce6cbd144d5fbb1722
https://github.com/qemu/qemu/commit/04e3aabde397e7abc78ba1ce6cbd144d5fbb1722
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M accel/tcg/cputlb.c
M softmmu_template.h
Log Message:
-----------
cputlb: Support generating CPU exceptions on memory transaction failures
Call the new cpu_transaction_failed() hook at the places where
CPU generated code interacts with the memory system:
io_readx()
io_writex()
get_page_addr_code()
Any access from C code (eg via cpu_physical_memory_rw(),
address_space_rw(), ld/st_*_phys()) will *not* trigger CPU exceptions
via cpu_transaction_failed(). Handling for transactions failures for
this kind of call should be done by using a function which returns a
MemTxResult and treating the failure case appropriately in the
calling code.
In an ideal world we would not generate CPU exceptions for
instruction fetch failures in get_page_addr_code() but instead wait
until the code translation process tried a load and it failed;
however that change would require too great a restructuring and
redesign to attempt at this point.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Commit: aac43da1d772a50778ab1252c13c08c2eb31fb39
https://github.com/qemu/qemu/commit/aac43da1d772a50778ab1252c13c08c2eb31fb39
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M target/arm/op_helper.c
Log Message:
-----------
target/arm: Factor out fault delivery code
We currently have some similar code in tlb_fill() and in
arm_cpu_do_unaligned_access() for delivering a data abort or prefetch
abort. We're also going to want to do the same thing to handle
external aborts. Factor out the common code into a new function
deliver_fault().
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Acked-by: Edgar E. Iglesias <address@hidden>
Commit: c528af7aa64f159eb30b46e567b650c5440fc117
https://github.com/qemu/qemu/commit/c528af7aa64f159eb30b46e567b650c5440fc117
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M target/arm/internals.h
M target/arm/op_helper.c
Log Message:
-----------
target/arm: Allow deliver_fault() caller to specify EA bit
For external aborts, we will want to be able to specify the EA
(external abort type) bit in the syndrome field. Allow callers of
deliver_fault() to do that by adding a field to ARMMMUFaultInfo which
we use when constructing the syndrome values.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Commit: 469f3da42ef4af347fa7831e1cc0bd35d17f5b83
https://github.com/qemu/qemu/commit/469f3da42ef4af347fa7831e1cc0bd35d17f5b83
Author: Thomas Huth <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hw/arm/aspeed_soc.c
Log Message:
-----------
hw/arm/aspeed_soc: Mark devices as user_creatable = false
QEMU currently aborts if the user is accidentially trying to
do something like this:
$ aarch64-softmmu/qemu-system-aarch64 -S -M integratorcp -nographic
QEMU 2.9.93 monitor - type 'help' for more information
(qemu) device_add ast2400
Unexpected error in error_set_from_qdev_prop_error()
at hw/core/qdev-properties.c:1032:
Aborted (core dumped)
The ast2400 SoC devices are clearly not creatable by the user since
they are using the serial_hds and nd_table arrays directly in their
realize function, so mark them with user_creatable = false.
Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: f58f25599b72c7479e6a1ff67c7f671823aa14da
https://github.com/qemu/qemu/commit/f58f25599b72c7479e6a1ff67c7f671823aa14da
Author: Thomas Huth <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hw/arm/digic.c
Log Message:
-----------
hw/arm/digic: Mark device with user_creatable = false
QEMU currently shows some unexpected behavior when the user trys to
do a "device_add digic" on an unrelated ARM machine like integratorcp
in "-nographic" mode (the device_add command does not immediately
return to the monitor prompt), and trying to "device_del" the device
later results in a "qemu/qdev-monitor.c:872:qdev_unplug: assertion
failed: (hotplug_ctrl)" error condition.
Looking at the realize function of the device, it uses serial_hds
directly and this means that the device can not be added a second
time, so let's simply mark it with "user_creatable = false" now.
Signed-off-by: Thomas Huth <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 3e4d91b94ce400326fae0850578d9e9f30a71adb
https://github.com/qemu/qemu/commit/3e4d91b94ce400326fae0850578d9e9f30a71adb
Author: Richard Henderson <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Fix aa64 ldp register writeback
For "ldp x0, x1, [x0]", if the second load is on a second page and
the second page is unmapped, the exception would be raised with x0
already modified. This means the instruction couldn't be restarted.
Cc: address@hidden
Cc: address@hidden
Reported-by: Andrew <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Fixes: https://bugs.launchpad.net/qemu/+bug/1713066
Signed-off-by: Richard Henderson <address@hidden>
[PMM: tweaked comment format]
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 7229ec5825df6b933f150b54a8a2bedd2de1864c
https://github.com/qemu/qemu/commit/7229ec5825df6b933f150b54a8a2bedd2de1864c
Author: Pranith Kumar <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M hw/intc/arm_gicv3_kvm.c
Log Message:
-----------
arm_gicv3_kvm: Fix compile warning
Fix the following warning:
/home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: warning: logical not is only
applied to the left hand side of this bitwise operator
[-Wlogical-not-parentheses]
if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
^ ~
/home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: note: add parentheses after
the '!' to evaluate the bitwise operator first
if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
^
/home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: note: add parentheses around
left hand side expression to silence this warning
if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
^
This logic error meant we were not setting the PTZ
bit when we should -- luckily as the comment suggests
this wouldn't have had any effects beyond making GIC
initialization take a little longer.
Signed-off-by: Pranith Kumar <address@hidden>
Message-id: address@hidden
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Commit: 2b483739791b33c46e6084b51edcf62107058ae1
https://github.com/qemu/qemu/commit/2b483739791b33c46e6084b51edcf62107058ae1
Author: Peter Maydell <address@hidden>
Date: 2017-09-04 (Mon, 04 Sep 2017)
Changed paths:
M accel/tcg/cputlb.c
M hw/arm/armv7m.c
M hw/arm/aspeed_soc.c
M hw/arm/digic.c
M hw/arm/exynos4210.c
M hw/arm/highbank.c
M hw/arm/realview.c
M hw/arm/vexpress.c
M hw/arm/virt.c
M hw/arm/xilinx_zynq.c
M hw/intc/arm_gicv3_kvm.c
M hw/intc/armv7m_nvic.c
M hw/watchdog/wdt_aspeed.c
M include/exec/memattrs.h
M include/exec/memory.h
M include/hw/arm/armv7m.h
R include/hw/arm/armv7m_nvic.h
M include/hw/elf_ops.h
A include/hw/intc/armv7m_nvic.h
M include/hw/watchdog/wdt_aspeed.h
M include/qom/cpu.h
M softmmu_template.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/kvm.c
M target/arm/kvm32.c
M target/arm/kvm64.c
M target/arm/kvm_arm.h
M target/arm/machine.c
M target/arm/op_helper.c
M target/arm/translate-a64.c
M target/arm/translate.c
Log Message:
-----------
Merge remote-tracking branch
'remotes/pmaydell/tags/pull-target-arm-20170904-2' into staging
target-arm:
* collection of M profile cleanups and minor bugfixes
* loader: handle ELF files with overlapping zero-init data
* virt: allow PMU instantiation with userspace irqchip
* wdt_aspeed: Add support for the reset width register
* cpu: Define new cpu_transaction_failed() hook
* Mark some SoC devices as not user-creatable
* arm: Fix aa64 ldp register writeback
* arm_gicv3_kvm: Fix compile warning
# gpg: Signature made Mon 04 Sep 2017 17:20:40 BST
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# gpg: aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20170904-2: (33 commits)
arm_gicv3_kvm: Fix compile warning
target/arm: Fix aa64 ldp register writeback
hw/arm/digic: Mark device with user_creatable = false
hw/arm/aspeed_soc: Mark devices as user_creatable = false
target/arm: Allow deliver_fault() caller to specify EA bit
target/arm: Factor out fault delivery code
cputlb: Support generating CPU exceptions on memory transaction failures
cpu: Define new cpu_transaction_failed() hook
memory.h: Move MemTxResult type to memattrs.h
aspeed_soc: Propagate silicon-rev to watchdog
watchdog: wdt_aspeed: Add support for the reset width register
target/arm/kvm: pmu: improve error handling
hw/arm/virt: allow pmu instantiation with userspace irqchip
target/arm/kvm: pmu: split init and set-irq stages
hw/arm/virt: add pmu interrupt state
hw/arm: use defined type name instead of hard-coded string
loader: Ignore zero-sized ELF segments
loader: Handle ELF files with overlapping zero-initialized data
nvic: Implement "user accesses BusFault" SCS region behaviour
armv7m_nvic.h: Move from include/hw/arm to include/hw/intc
...
Signed-off-by: Peter Maydell <address@hidden>
Compare: https://github.com/qemu/qemu/compare/98bfaac788be...2b483739791b
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