[Qemu-commits] [qemu/qemu] 031631: target/s390x: fix pgm irq ilen for stsi

[GitHub]

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: 031631c3cf976861c34decabbffb705c0540e148
      
https://github.com/qemu/qemu/commit/031631c3cf976861c34decabbffb705c0540e148
  Author: David Hildenbrand <address@hidden>
  Date:   2017-07-28 (Fri, 28 Jul 2017)

  Changed paths:
    M target/s390x/misc_helper.c

  Log Message:
  -----------
  target/s390x: fix pgm irq ilen for stsi

The instruction is 4 bytes long.

Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>


  Commit: 98987d30b636b1d066eae73178cce71638c20c74
      
https://github.com/qemu/qemu/commit/98987d30b636b1d066eae73178cce71638c20c74
  Author: David Hildenbrand <address@hidden>
  Date:   2017-07-28 (Fri, 28 Jul 2017)

  Changed paths:
    M target/s390x/mmu_helper.c

  Log Message:
  -----------
  target/s390x: fix pgm irq ilen in translate_pages()

0 is certainly wrong. Let's use ILEN_AUTO.

Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>


  Commit: 198c0d1f9df8c429502cb744fc26b6ba6e71db74
      
https://github.com/qemu/qemu/commit/198c0d1f9df8c429502cb744fc26b6ba6e71db74
  Author: Halil Pasic <address@hidden>
  Date:   2017-07-28 (Fri, 28 Jul 2017)

  Changed paths:
    M hw/s390x/css.c

  Log Message:
  -----------
  s390x/css: check ccw address validity

According to the PoP channel command words (CCW) must be doubleword
aligned and 31 bit addressable for format 1 and 24 bit addressable for
format 0 CCWs.

If the channel subsystem encounters a ccw address which does not satisfy
this alignment requirement a program-check condition is recognised.

The situation with 31 bit addressable is a bit more complicated: both the
ORB and a format 1 CCW TIC hold the address of (the rest of) the channel
program, that is the address of the next CCW in a word, and the PoP
mandates that bit 0 of that word shall be zero -- or a program-check
condition is to be recognized -- and does not belong to the field holding
the ccw address.

Since in code the corresponding fields span across the whole word (unlike
in PoP where these are defined as 31 bit wide) we can check this by
applying a mask. The 24 addressable case isn't affecting TIC because the
address is composed of a halfword and a byte portion (no additional zero
bit requirements) and just slightly complicates the ORB case where also
bits 1-7 need to be zero.

The same requirements (especially n-bit addressability) apply to the
ccw addresses generated while chaining.

Let's make our CSS implementation follow the AR more closely.

Signed-off-by: Halil Pasic <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Dong Jia Shi <address@hidden>
Signed-off-by: Cornelia Huck <address@hidden>


  Commit: 4add0da64942d83e0564147c0876b01074bde9cb
      
https://github.com/qemu/qemu/commit/4add0da64942d83e0564147c0876b01074bde9cb
  Author: Halil Pasic <address@hidden>
  Date:   2017-07-28 (Fri, 28 Jul 2017)

  Changed paths:
    M hw/s390x/css.c

  Log Message:
  -----------
  s390x/css: fix bits must be zero check for TIC

According to the PoP bit positions 0-3 and 8-32 of the format-1 CCW must
contain zeros.  Bits 0-3 are already covered by cmd_code validity
checking, and bit 32 is covered by the CCW address checking.

Bits 8-31 correspond to CCW1.flags and CCW1.count.  Currently we only
check for the absence of certain flags.  Let's fix this.

Signed-off-by: Halil Pasic <address@hidden>
Message-Id: <address@hidden>
Reviewed-by: Dong Jia Shi <address@hidden>
[CH: tweaked comment]
Signed-off-by: Cornelia Huck <address@hidden>


  Commit: 871a0f7ad2b9560c5f7d640125c5be95ca23ca7f
      
https://github.com/qemu/qemu/commit/871a0f7ad2b9560c5f7d640125c5be95ca23ca7f
  Author: Peter Maydell <address@hidden>
  Date:   2017-07-28 (Fri, 28 Jul 2017)

  Changed paths:
    M hw/s390x/css.c
    M target/s390x/misc_helper.c
    M target/s390x/mmu_helper.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20170728' into staging

More s390x fixes: Correct ilen, and ccw checking.

# gpg: Signature made Fri 28 Jul 2017 10:13:42 BST
# gpg:                using RSA key 0xDECF6B93C6F02FAF
# gpg: Good signature from "Cornelia Huck <address@hidden>"
# gpg:                 aka "Cornelia Huck <address@hidden>"
# gpg:                 aka "Cornelia Huck <address@hidden>"
# gpg:                 aka "Cornelia Huck <address@hidden>"
# Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0  18CE DECF 6B93 C6F0 2FAF

* remotes/cohuck/tags/s390x-20170728:
  s390x/css: fix bits must be zero check for TIC
  s390x/css: check ccw address validity
  target/s390x: fix pgm irq ilen in translate_pages()
  target/s390x: fix pgm irq ilen for stsi

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/e01151de1650...871a0f7ad2b9