qemu-commits
[Top][All Lists]
Advanced
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-commits] [qemu/qemu] c67ba3: target/s390x: Implement CSST

From: GitHub
Subject: [Qemu-commits] [qemu/qemu] c67ba3: target/s390x: Implement CSST
Date: Tue, 18 Jul 2017 10:28:26 -0700 
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: c67ba3030719ab9cb16bfe9bcd1365a262fd308f
      
https://github.com/qemu/qemu/commit/c67ba3030719ab9cb16bfe9bcd1365a262fd308f
  Author: Richard Henderson <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M target/s390x/cpu_models.c
    M target/s390x/helper.h
    M target/s390x/insn-data.def
    M target/s390x/mem_helper.c
    M target/s390x/translate.c

  Log Message:
  -----------
  target/s390x: Implement CSST

Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 941ef3db03fe40cec04fbf0102d1aa14711c708d
      
https://github.com/qemu/qemu/commit/941ef3db03fe40cec04fbf0102d1aa14711c708d
  Author: Richard Henderson <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M target/s390x/helper.h
    M target/s390x/insn-data.def
    M target/s390x/mem_helper.c
    M target/s390x/translate.c

  Log Message:
  -----------
  target/s390x: Implement CONVERT UNICODE insns

Reviewed-by: Aurelien Jarno <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 7591db780d9e464232e7ae692302ebe1dbb76141
      
https://github.com/qemu/qemu/commit/7591db780d9e464232e7ae692302ebe1dbb76141
  Author: Richard Henderson <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M target/s390x/helper.h
    M target/s390x/insn-data.def
    M target/s390x/mem_helper.c
    M target/s390x/translate.c

  Log Message:
  -----------
  target/s390x: Tidy SRST

Since we require all registers saved on input, read R0 from ENV instead
of passing it manually.  Recognize the specification exception when R0
contains incorrect data.  Keep high bits of result registers unmodified
when in 31 or 24-bit mode.

Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: be7acb58390c0107cedf355c38197963abfa9682
      
https://github.com/qemu/qemu/commit/be7acb58390c0107cedf355c38197963abfa9682
  Author: Richard Henderson <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M target/s390x/helper.h
    M target/s390x/insn-data.def
    M target/s390x/mem_helper.c
    M target/s390x/translate.c

  Log Message:
  -----------
  target/s390x: Implement SRSTU

Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: b213c9f58ec37d7d1363561a099a9745da6e4620
      
https://github.com/qemu/qemu/commit/b213c9f58ec37d7d1363561a099a9745da6e4620
  Author: Richard Henderson <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M target/s390x/helper.h
    M target/s390x/insn-data.def
    M target/s390x/mem_helper.c
    M target/s390x/translate.c

  Log Message:
  -----------
  target/s390x: Implement TRTR

Drop TRT from the set of insns handled internally by EXECUTE.
It's more important to adjust the existing helper to handle
both TRT and TRTR.

Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: e89ea6aa9d8e86351259fb33c0e6d2ee36c12eb1
      
https://github.com/qemu/qemu/commit/e89ea6aa9d8e86351259fb33c0e6d2ee36c12eb1
  Author: Richard Henderson <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M target/s390x/cpu_models.c

  Log Message:
  -----------
  target/s390x: Mark ETF3 and ETF3_ENH facilities as available

Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: 19d70587b59f7879a0315a6d98c2409957154351
      
https://github.com/qemu/qemu/commit/19d70587b59f7879a0315a6d98c2409957154351
  Author: David Hildenbrand <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M target/s390x/cpu_models.c

  Log Message:
  -----------
  target/s390x: Allow to enable "idtes" feature for TCG

STFL bit 4 and 5 are just indications to the guest, which TLB entries an
IDTE call will clear. These are performance indicators for the guest.

STFL bit 4:
    INVALIDATE DAT TABLE ENTRY (IDTE) performs
    the invalidation-and-clearing operation by
    selectively clearing TLB segment-table entries
    when a segment-table entry or entries are
    invalidated. IDTE also performs the clearing-by-
    ASCE operation. Unless bit 4 is one, IDTE simply
    purges all TLBs. Bit 3 is one if bit 4 is one.

We can simply set STFL bit 4 ("idtes") and still purge the complete TLB.
Purging more than advertised is never bad. E.g. Linux doesn't even care
about this bit. We can optimized this later.
This is helpful, as the z9 base model contains this facility.

STFL bit 5 (clearing TLB region-table-entries) was never implemented on
real HW, therefore we can simply ignore it for now.

Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: dbdaaff43adc49f1debd935b1fd58e2b47ba7676
      
https://github.com/qemu/qemu/commit/dbdaaff43adc49f1debd935b1fd58e2b47ba7676
  Author: Richard Henderson <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M target/s390x/translate.c

  Log Message:
  -----------
  target/s390x: Fix risbg handling

The rotation is to the left, but extract shifts to the right.
The computation of the extract parameters needs adjusting.

For the entry condition, simplify

        64 - rot + len <= 64
        -rot + len <= 0
        len <= rot

Reviewed-by: Aurelien Jarno <address@hidden>
Reported-by: David Hildenbrand <address@hidden>
Suggested-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>


  Commit: ff3351d4495c07501aa75e46aec3f494f51d29e1
      
https://github.com/qemu/qemu/commit/ff3351d4495c07501aa75e46aec3f494f51d29e1
  Author: Peter Maydell <address@hidden>
  Date:   2017-07-18 (Tue, 18 Jul 2017)

  Changed paths:
    M target/s390x/cpu_models.c
    M target/s390x/helper.h
    M target/s390x/insn-data.def
    M target/s390x/mem_helper.c
    M target/s390x/translate.c

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/rth/tags/pull-s390-20170717' into 
staging

Queued s390x tcg patches, v2

# gpg: Signature made Mon 17 Jul 2017 22:22:23 BST
# gpg:                using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <address@hidden>"
# gpg:                 aka "Richard Henderson <address@hidden>"
# gpg:                 aka "Richard Henderson <address@hidden>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC  16A4 AD12 70CC 4DD0 279B

* remotes/rth/tags/pull-s390-20170717:
  target/s390x: Fix risbg handling
  target/s390x: Allow to enable "idtes" feature for TCG
  target/s390x: Mark ETF3 and ETF3_ENH facilities as available
  target/s390x: Implement TRTR
  target/s390x: Implement SRSTU
  target/s390x: Tidy SRST
  target/s390x: Implement CONVERT UNICODE insns
  target/s390x: Implement CSST

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/9d836fc552cc...ff3351d4495c
reply via email to
[Prev in Thread] Current Thread [Next in Thread]