qemu-commits
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-commits] [qemu/qemu] d9a7b1: qdev-properties.h: Explicitly set the


From: GitHub
Subject: [Qemu-commits] [qemu/qemu] d9a7b1: qdev-properties.h: Explicitly set the default valu...
Date: Tue, 18 Jul 2017 03:40:15 -0700

  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: d9a7b125d6b8048a503d10117ee8b7cbc44cc889
      
https://github.com/qemu/qemu/commit/d9a7b125d6b8048a503d10117ee8b7cbc44cc889
  Author: Peter Maydell <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M include/hw/qdev-properties.h

  Log Message:
  -----------
  qdev-properties.h: Explicitly set the default value for arraylen properties

In DEFINE_PROP_ARRAY, because we use a PropertyInfo (qdev_prop_arraylen)
which has a .set_default_value member we will set the field to a default
value. That default value will be zero, by the C rule that struct
initialization sets unmentioned members to zero if at least one member
is initialized. However it's clearer to state it explicitly.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Marc-André Lureau <address@hidden>
Message-id: address@hidden


  Commit: 5cc56cc6872122af318f07088b7d599c3781719f
      
https://github.com/qemu/qemu/commit/5cc56cc6872122af318f07088b7d599c3781719f
  Author: Peter Maydell <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M hw/core/qdev.c
    M include/hw/qdev-core.h
    M include/hw/qdev-properties.h

  Log Message:
  -----------
  qdev: support properties which don't set a default value

In some situations it's useful to have a qdev property which doesn't
automatically set its default value when qdev_property_add_static is
called (for instance when the default value is not constant).

Support this by adding a flag to the Property struct indicating
whether to set the default value.  This replaces the existing test
for whether the PropertyInfo set_default_value function pointer is
NULL, and we set the .set_default field to true for all those cases
of struct Property which use a PropertyInfo with a non-NULL
set_default_value, so behaviour remains the same as before.

This gives us the semantics of:
 * if .set_default is true, then .info->set_default_value must
   be not NULL, and .defval is used as the the default value of
   the property
 * otherwise, the property system does not set any default, and
   the field will retain whatever initial value it was given by
   the device's .instance_init method

We define two new macros DEFINE_PROP_SIGNED_NODEFAULT and
DEFINE_PROP_UNSIGNED_NODEFAULT, to cover the most plausible use cases
of wanting to set an integer property with no default value.

Suggested-by: Markus Armbruster <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Marc-André Lureau <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Message-id: address@hidden


  Commit: 8d92e26b452f8961ec90df3f93cf5f3b7a9d158f
      
https://github.com/qemu/qemu/commit/8d92e26b452f8961ec90df3f93cf5f3b7a9d158f
  Author: Peter Maydell <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M target/arm/cpu.c

  Log Message:
  -----------
  target/arm: Make Cortex-M3 and M4 default to 8 PMSA regions

The Cortex-M3 and M4 CPUs always have 8 PMSA MPU regions (this isn't
a configurable option for the hardware).  Make the default value of
the pmsav7-dregion property be set per-cpu, so we don't need to have
every user of these CPUs set it manually.  (The existing default of
16 is correct for the other PMSAv7 core, the Cortex-R5.)

This fixes a bug where we were creating the M3 and M4 with
too many regions; most guest software would not notice or
care, though, since it would just not use the registers
associated with the unexpected extra regions.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Marc-André Lureau <address@hidden>
Message-id: address@hidden


  Commit: df0311e634828fdc99ca59352aef68503d631aad
      
https://github.com/qemu/qemu/commit/df0311e634828fdc99ca59352aef68503d631aad
  Author: Alex Bennée <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M include/exec/exec-all.h

  Log Message:
  -----------
  include/exec/exec-all: document common exit conditions

As a precursor to later patches attempt to come up with a more
concrete wording for what each of the common exit cases would be.

CC: Emilio G. Cota <address@hidden>
CC: Richard Henderson <address@hidden>
CC: Lluís Vilanova <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: e8d5230221851e8933811f1579fd13371f576955
      
https://github.com/qemu/qemu/commit/e8d5230221851e8933811f1579fd13371f576955
  Author: Alex Bennée <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm/translate: make DISAS_UPDATE match declared semantics

DISAS_UPDATE should be used when the wider CPU state other than just
the PC has been updated and we should therefore exit the TCG runtime
and return to the main execution loop rather assuming DISAS_JUMP would
do that.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: abd1fb0ee2c58b99f4b2d15718f1825fe4984e12
      
https://github.com/qemu/qemu/commit/abd1fb0ee2c58b99f4b2d15718f1825fe4984e12
  Author: Alex Bennée <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M target/arm/translate.h

  Log Message:
  -----------
  target/arm/translate.h: expand comment on DISAS_EXIT

We already have an exit condition, DISAS_UPDATE which will exit the
run-loop. Expand on the difference with DISAS_EXIT in the comments.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 4cae8f56fbab2798586576a56cc669f0127d04fb
      
https://github.com/qemu/qemu/commit/4cae8f56fbab2798586576a56cc669f0127d04fb
  Author: Alex Bennée <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm/translate: ensure gen_goto_tb sets exit flags

As the gen_goto_tb function can do both static and dynamic jumps it
should also set the is_jmp field. This matches the behaviour of the
a64 code.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[tweak to multiline comment formatting]
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 0b609cc128ba5ef16cc841bcade898d1898f1dc3
      
https://github.com/qemu/qemu/commit/0b609cc128ba5ef16cc841bcade898d1898f1dc3
  Author: Alex Bennée <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: use gen_goto_tb for ISB handling

While an ISB will ensure any raised IRQs happen on the next
instruction it doesn't cause any to get raised by itself. We can
therefore use a simple tb exit for ISB instructions and rely on the
exit_request check at the top of each TB to deal with exiting if
needed.

Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: b29fd33db578decacd14f34933b29aece3e7c25e
      
https://github.com/qemu/qemu/commit/b29fd33db578decacd14f34933b29aece3e7c25e
  Author: Alex Bennée <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M target/arm/translate-a64.c
    M target/arm/translate.c

  Log Message:
  -----------
  target/arm: use DISAS_EXIT for eret handling

Previously DISAS_JUMP did ensure this but with the optimisation of
8a6b28c7 (optimize indirect branches) we might not leave the loop.
This means if any pending interrupts are cleared by changing IRQ flags
we might never get around to servicing them. You usually notice this
by seeing the lookup_tb_ptr() helper gainfully chaining TBs together
while cpu->interrupt_request remains high and the exit_request has not
been set.

This breaks amongst other things the OPTEE test suite which executes
an eret from the secure world after a non-secure world IRQ has gone
pending which then never gets serviced.

Instead of using the previously implied semantics of DISAS_JUMP we use
DISAS_EXIT which will always exit the run-loop.

CC: Etienne Carriere <address@hidden>
CC: Joakim Bech <address@hidden>
CC: Jaroslaw Pelczar <address@hidden>
CC: Peter Maydell <address@hidden>
CC: Emilio G. Cota <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>


  Commit: 2eb5578b4794d387e03cd424faa1f0e15c245ab9
      
https://github.com/qemu/qemu/commit/2eb5578b4794d387e03cd424faa1f0e15c245ab9
  Author: Peter Maydell <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/arm/Makefile.objs
    A hw/arm/mps2.c

  Log Message:
  -----------
  hw/arm/mps2: Implement skeleton mps2-an385 and mps2-an511 board models

Model the ARM MPS2/MPS2+ FPGA based development board.

The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger
FPGA but is otherwise the same as the 2). Since the CPU itself
and most of the devices are in the FPGA, the details of the board
as seen by the guest depend significantly on the FPGA image.

We model the following FPGA images:
 "mps2_an385" -- Cortex-M3 as documented in ARM Application Note AN385
 "mps2_an511" -- Cortex-M3 'DesignStart' as documented in AN511

They are fairly similar but differ in the details for some
peripherals.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Alex Bennée <address@hidden>


  Commit: 775df84e48bffba8cb188eecdf7872923d6e15d7
      
https://github.com/qemu/qemu/commit/775df84e48bffba8cb188eecdf7872923d6e15d7
  Author: Peter Maydell <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/char/Makefile.objs
    A hw/char/cmsdk-apb-uart.c
    M hw/char/trace-events
    A include/hw/char/cmsdk-apb-uart.h

  Log Message:
  -----------
  hw/char/cmsdk-apb-uart.c: Implement CMSDK APB UART

Implement a model of the simple "APB UART" provided in
the Cortex-M System Design Kit (CMSDK).

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Alex Bennée <address@hidden>


  Commit: 977a15f4805b0fcc72243581fd9a4e4b6ac4d3b4
      
https://github.com/qemu/qemu/commit/977a15f4805b0fcc72243581fd9a4e4b6ac4d3b4
  Author: Peter Maydell <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M hw/arm/mps2.c
    M hw/char/cmsdk-apb-uart.c

  Log Message:
  -----------
  hw/arm/mps2: Add UARTs

Add the UARTs to the MPS2 board models.

Unfortunately the details of the wiring of the interrupts through
various OR gates differ between AN511 and AN385 so this can't
be purely a data-driven difference.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden


  Commit: 5dd85b4b48653993335ca20d6e4d7b80129cca97
      
https://github.com/qemu/qemu/commit/5dd85b4b48653993335ca20d6e4d7b80129cca97
  Author: Peter Maydell <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/timer/Makefile.objs
    A hw/timer/cmsdk-apb-timer.c
    M hw/timer/trace-events
    A include/hw/timer/cmsdk-apb-timer.h

  Log Message:
  -----------
  hw/char/cmsdk-apb-timer: Implement CMSDK APB timer device

Implement a model of the simple timer device found in the CMSDK.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: 3d53904a68ff0532a056e799d7bea6c625ade9ce
      
https://github.com/qemu/qemu/commit/3d53904a68ff0532a056e799d7bea6c625ade9ce
  Author: Peter Maydell <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M hw/arm/mps2.c

  Log Message:
  -----------
  hw/arm/mps2: Add timers

Add the CMSDK APB timers to the MPS2 board.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: dd73185b7d3f36e9cbb160d739aa1151e55382d0
      
https://github.com/qemu/qemu/commit/dd73185b7d3f36e9cbb160d739aa1151e55382d0
  Author: Peter Maydell <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M default-configs/arm-softmmu.mak
    M hw/misc/Makefile.objs
    A hw/misc/mps2-scc.c
    M hw/misc/trace-events
    A include/hw/misc/mps2-scc.h

  Log Message:
  -----------
  hw/misc/mps2_scc: Implement MPS2 Serial Communication Controller

Implement a model of the Serial Communication Controller (SCC) found
in MPS2 FPGA images.

The primary purpose of this device is to communicate with the
Motherboard Configuration Controller (MCC) which is located on
the MPS board itself, outside the FPGA image. This is used
for programming the MPS clock generators. The SCC also has
some basic ID registers and an output for the board LEDs.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: 6dbdf4ec3332dd976ce2b45a431909dedc31bcae
      
https://github.com/qemu/qemu/commit/6dbdf4ec3332dd976ce2b45a431909dedc31bcae
  Author: Peter Maydell <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M hw/arm/mps2.c

  Log Message:
  -----------
  hw/arm/mps2: Add SCC

Add the SCC to the MPS2 board models.

Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden


  Commit: 3587393922dec51ebcbe6088649aface38cd89f6
      
https://github.com/qemu/qemu/commit/3587393922dec51ebcbe6088649aface38cd89f6
  Author: Peter Maydell <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M hw/arm/mps2.c

  Log Message:
  -----------
  hw/arm/mps2: Add ethernet

The MPS2 FPGA images support ethernet via a LAN9220. We use
QEMU's LAN9118 model, which is software compatible except
that it is missing the checksum-offload feature.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: e5a6a6e64e82a132cebef023d867085b0a2993d7
      
https://github.com/qemu/qemu/commit/e5a6a6e64e82a132cebef023d867085b0a2993d7
  Author: Peter Maydell <address@hidden>
  Date:   2017-07-17 (Mon, 17 Jul 2017)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add entries for MPS2 board

Add entries to the MAINTAINERS file for the new MPS2
board and devices.

Since the CMSDK devices are not specific to the MPS2 board,
extend the existing 'PrimeCell' section to cover CMSDK
devices as well; in both cases these are devices implemented
by ARM and provided as RTL that may be used in multiple
SoCs and boards.

Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>


  Commit: 6c4591566d6f1257683d2ccc94b9360ee8315474
      
https://github.com/qemu/qemu/commit/6c4591566d6f1257683d2ccc94b9360ee8315474
  Author: Peter Maydell <address@hidden>
  Date:   2017-07-18 (Tue, 18 Jul 2017)

  Changed paths:
    M MAINTAINERS
    M default-configs/arm-softmmu.mak
    M hw/arm/Makefile.objs
    A hw/arm/mps2.c
    M hw/char/Makefile.objs
    A hw/char/cmsdk-apb-uart.c
    M hw/char/trace-events
    M hw/core/qdev.c
    M hw/misc/Makefile.objs
    A hw/misc/mps2-scc.c
    M hw/misc/trace-events
    M hw/timer/Makefile.objs
    A hw/timer/cmsdk-apb-timer.c
    M hw/timer/trace-events
    M include/exec/exec-all.h
    A include/hw/char/cmsdk-apb-uart.h
    A include/hw/misc/mps2-scc.h
    M include/hw/qdev-core.h
    M include/hw/qdev-properties.h
    A include/hw/timer/cmsdk-apb-timer.h
    M target/arm/cpu.c
    M target/arm/translate-a64.c
    M target/arm/translate.c
    M target/arm/translate.h

  Log Message:
  -----------
  Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170717' 
into staging

target-arm queue:
 * new model of the ARM MPS2/MPS2+ FPGA based development board
 * clean up DISAS_* exit conditions and fix various regressions
   since commits e75449a346 8a6b28c7b5 (in particular including
   ones which broke OP-TEE guests)
 * make Cortex-M3 and M4 correctly default to 8 PMSA regions

# gpg: Signature made Mon 17 Jul 2017 13:43:45 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# gpg:                 aka "Peter Maydell <address@hidden>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170717:
  MAINTAINERS: Add entries for MPS2 board
  hw/arm/mps2: Add ethernet
  hw/arm/mps2: Add SCC
  hw/misc/mps2_scc: Implement MPS2 Serial Communication Controller
  hw/arm/mps2: Add timers
  hw/char/cmsdk-apb-timer: Implement CMSDK APB timer device
  hw/arm/mps2: Add UARTs
  hw/char/cmsdk-apb-uart.c: Implement CMSDK APB UART
  hw/arm/mps2: Implement skeleton mps2-an385 and mps2-an511 board models
  target/arm: use DISAS_EXIT for eret handling
  target/arm: use gen_goto_tb for ISB handling
  target/arm/translate: ensure gen_goto_tb sets exit flags
  target/arm/translate.h: expand comment on DISAS_EXIT
  target/arm/translate: make DISAS_UPDATE match declared semantics
  include/exec/exec-all: document common exit conditions
  target/arm: Make Cortex-M3 and M4 default to 8 PMSA regions
  qdev: support properties which don't set a default value
  qdev-properties.h: Explicitly set the default value for arraylen properties

Signed-off-by: Peter Maydell <address@hidden>


Compare: https://github.com/qemu/qemu/compare/a778cd5610b4...6c4591566d6f

reply via email to

[Prev in Thread] Current Thread [Next in Thread]